ILX548K 5340 pixel × 3 line CCD Linear Sensor (Color) For the availability of this product, please contact the sales office. Description The ILX548K is a reduction type CCD linear sensor developed for color image scanner. This sensor reads A4-size documents at a density of 600DPI. 22 pin DIP (Cer-DIP) Features • Number of effective pixels: 16020 pixels (5340 pixels × 3) • Pixel size: 4µm × 4µm (4µm pitch) • Distance between line: 32µm (8 lines) • Single-sided readout • Ultra low lag/High sensitivity • Single 12V power supply • Maximum data rate: 5MHz/Color • Input clock pulse: CMOS 5V drive • Number of output: 3 (R, G, B) • Package: 22 pin Cer-DIP (400mil) 22 pin Plastic DIP (400mil) Red 11 φROG-B φ2 10 12 φROG-G Driver Driver φ1 21 22 φCLP 1 R 5340 1 1 G 5340 D18 D19 B D69 S1 5340 S5340 D70 12 φROG-G 13 11 1 φROG-B φRS 13 φ1 4 10 VDD φ2 2 14 φROG-R GND 9 CCD register NC Blue 15 NC Output amplifier 8 VOUT-B 20 NC 16 NC CCD register 7 Green NC Read out gate 17 NC Output amplifier 6 3 NC VOUT-G 18 NC CCD register 5 Read out gate NC Output amplifier 19 VOUT-R 19 4 VOUT-R VDD GND 20 VOUT-B D18 D19 3 D18 D19 VOUT-G 21 GND D69 S1 2 D69 S1 GND 22 φCLP S5340 D70 1 D74 D75 φRS S5340 D70 Pin Configuration (Top View) D74 D75 V °C Read out gate 14 φROG-R Driver Block Diagram D74 D75 Absolute Maximum Ratings • Supply voltage VDD 15 • Operating temperature –10 to +55 22 pin DIP (Plastic) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00429-PS ILX548K Pin Description Pin No. Symbol Pin No. Description Symbol Description 1 φRS Clock pulse input 12 φROG-G Clock pulse input 2 GND GND 13 φ1 Clock pulse input 3 VOUT-G Signal output (green) 14 φROG-R Clock pulse input 4 VDD 12V power supply 15 NC NC 5 NC NC 16 NC NC 6 NC NC 17 NC NC 7 NC NC 18 NC NC 8 NC NC 19 VOUT-R Signal output (red) 9 NC NC 20 VOUT-B Signal output (blue) 10 φ2 Clock pulse input 21 GND GND 11 φROG-B Clock pulse input 22 φCLP Clock pulse input Recommended Supply Voltage Item VDD Min. Typ. Max. Unit 11.4 12 12.6 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φ1, φ2 Cφ1, Cφ2 — 500 — pF Input capacity of φRS CφRS — 10 — pF Input capacity of φCLP CφCLP — 10 — pF Input capacity of φROG CφROG — 10 — pF Clock Frequency Symbol Min. Typ. Max. Unit fφ1, fφ2, fφRS, fφCLP — 1 5 MHz Item φ1, φ2, φRS, φCLP Input Clock Pulse Voltage Condition Min. Typ. Max. Unit High level 4.75 5.0 5.25 V Low level — 0 0.1 V Item φ1, φ2, φRS, φCLP, φROG pulse voltage –2– ILX548K Electrooptical Characteristics (Note 1) (Ta = 25°C, VDD = 12V, fφRS = 1MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Item Symbol Min. Typ. Max. Unit Remarks Red RR 1.8 2.7 3.6 Green RG 2.1 3.3 4.5 V/(lx · s) Note 2 Blue RB 1.7 2.6 3.5 Sensitivity nonuniformity PRNU — 4 20 % Note 3 Saturation output voltage VSAT 2 2.5 — V Note 4 Red SER 0.56 0.93 — Green SEG 0.44 0.76 — lx · s Note 5 Blue SEB 0.57 0.96 — Dark voltage average VDRK — 2 5 mV Dark signal nonuniformity DSNU — 4 12 mV Image lag IL — 0.02 — % Note 7 Supply current IVDD — 25 50 mA — Total transfer efficiency TTE 92 98 — % — Output impedance Zo — 450 — Ω — Offset level VOS — 7.3 — V Note 8 Sensitivity Saturation exposure Note 6 Notes) 1. In accordance with the given electrooptical characteristics, the black level is defined as the average value of D18, D19 to D67. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT-G= 500mV (Typ.) PRNU = (VMAX – VMIN)/2 VAVE × 100 [%] Where the 5340 pixels are divided into blocks of 100, the maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4. Use below the minimum value of the saturation output voltage. 5. Saturation exposure is defined as follows. SE = VSAT R Where R indicates RR, RG, RB, and SE indicates SER, SEG, SEB. ;;; 6. Optical signal accumulated time τint stands at 5.5ms. 7. VOUT-G = 500mV (Typ.) 8. Vos is defined as indicated below. VOUT indicates VOUT-R, VOUT-G and VOUT-B. VOUT VOS GND –3– –4– VOUT φCLP φRS φ2 φ1 φROG D75 D74 5415 D71 D70 S5340 S5339 S5338 S2 S1 D69 D68 D19 D18 D17 D3 4 1-line output period (5415 pixels) Dummy signal (69 pixels) Optical black (50 pixels) ; ; ;; D67 D2 3 2 Note) The transfer pulses (φ1, φ2) must have more than 5415 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. φROG indicates φROG-R, φROG-G, φROG-B. 0 5 0 5 0 5 0 5 0 5 1 D1 Clock Timing Chart 1 ILX548K ILX548K Clock Timing Chart 2 t4 t5 φROG t2 t6 φ1 t7 t1 t3 φ2 Clock Timing Chart 3 t6 t7 φ1 φ2 t9 φRS t10 t8 t16 t15 t14 t17 φCLP t13 ; ;;; ; ; t12 t11 VOUT –5– ILX548K Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 — ns φROG pulse high level period t2 3 5 — µs φROG, φ1 pulse timing t3 1 2 — µs φROG pulse rise time t4 0 5 — ns φROG pulse fall time t5 0 5 — ns φ1 pulse rise time/φ2 pulse fall time t6 0 20 — ns φ1 pulse fall time/φ2 pulse rise time t7 0 — ns φRS pulse high level period t8 30 20 50∗1 — ns φRS pulse rise time t9 0 20 — ns φRS pulse fall time t10 0 20 — ns t11 — 50 — ns t12 — 20 — ns t13 40 100 — ns t14 40 100 — ns t15 10 50 — ns φCLP pulse rise time t16 0 20 — ns φCLP pulse fall time t17 0 20 — ns Signal output delay time φCLP pulse high level period φCLP pulse timing ∗1 These timing is the recommended condition under fφRS = 1MHz. –6– –7– 47µF/16V ∗ Data rate fφRS = 1MHz 0.1µF 12V Application Circuit∗ φRS 1 2 100Ω 5.1kΩ 3 Tr1 4 VOUT-G 5 6 IC1: 74AC04 Tr1: 2SC2785 7 8 9 IC1 2Ω φ2 10 11 φROG-B 100Ω 12 13 14 15 16 17 100Ω 18 2Ω φROG-G 19 100Ω φ1 20 100Ω Tr1 VOUT-R φROG-R 21 Tr1 VOUT-B 5.1kΩ 22 100Ω 5.1kΩ IC1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. IC1 100Ω 100Ω IC1 φRS φCLP GND GND VOUT-G VOUT-B VDD VOUT-R NC NC NC NC NC NC NC NC NC φROG-R φ2 φ1 φROG-B φROG-G φCLP ILX548K ILX548K Example of Representative Characteristics (VDD = 12V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 1.0 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 450 500 550 600 Wavelength [nm] Dark voltage rate vs. Ambient temperature (Standard characteristics) 10 Output voltage rate Dark voltage rate 700 Output voltage rate vs. Integration time (Standard characteristics) 100 10 1 0.1 –10 650 1 0.1 0 10 20 30 40 50 Ta – Ambient temperature [°C] 60 1 Offset level vs. Supply voltage (Standard characteristics) 5 τ int – Integration time [ms] 10 Offset level vs. Ambient temperature (Standard characteristics) 10 10 Ta = 25°C 8 Vos – Offset level [V] Vos – Offset level [V] 8 6 4 ∆Vos ≈ 0.7 ∆VDD 2 0 11.4 6 4 ∆Vos ≈ 1mV/°C ∆Ta 2 12 VDD – Supply voltage [V] 0 –10 12.6 –8– 0 10 20 30 40 50 Ta – Ambient temperature [°C] 60 ILX548K Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. ;; ;;;;; ;;;; ;;;; ;;; ;;;; ; ; ; ;; ; ;; ;; ;; 2) Notes on Handling CCD Packages The following points should be observed when handling and installing packages. a) Remain within the following limits when applying static load to the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N Lower ceramic layer 29N 0.9Nm 29N Low-melting glass (1) (2) (3) (4) Cover glass Plastic portion 29N 39N 0.9Nm 29N Adhesive Ceramic portion (1) (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the package to crack or dust to be generated. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. (6) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer. (7) Applying the metal a crash or a rub against the plastic portion. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. –9– ILX548K 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 10 – ILX548K Package Outline Unit: mm 22pin DIP (400mil) No.1 Pixel (Green) H 11 0.25 1 10.16 10.0 ± 0.5 V (AT STAND OFF) 12 22 5.0 ± 0.5 0° to 9° 32.0 ± 0.5 21.36 (4µm × 5340Pixels) 6.22 ± 0.5 1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm. 3.4 ± 0.5 2.7 4.0 ± 0.5 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 0.51 2.54 0.3 M PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 3.0g DRAWING NUMBER LS-D15(E) 22pin DIP (400mil) 21.36 (4µmX5340Pixels) 6.22 ± 0.3 12 No.1 Pixel (Green) 10.16 10.0 ± 0.3 5.0 ± 0.3 22 V 0˚ to 9˚ 32.0 ± 0.3 H 11 0.25 1 2.54 2.8 ± 0.5 4.0 ± 0.5 2.1 1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 0.51 0.3 M PACKAGE STRUCTURE PACKAGE MATERIAL Plastic,Ceramic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42ALLOY PACKAGE MASS 2.21g DRAWING NUMBER LS-D13-01(E) – 11 – Sony Corporation