FAIRCHILD SPT5400

SPT5400
13-BIT, OCTAL VOLTAGE-OUTPUT DAC
WITH PARALLEL INTERFACE
FEATURES
APPLICATIONS
•
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•
•
•
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•
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Full 13-bit performance without external adjustments
Eight DACs in one package
Buffered voltage outputs
Guaranteed monotonic to 13 bits
Unipolar or bipolar output swing to ±4.5 V
Output settling time of 7 µs to ±1/2 LSB
Double-buffered digital inputs
Automatic test equipment
Flat-panel displays
Arbitrary function generators
Instrumentation
Process control
DESCRIPTION
The SPT5400 has eight 13-bit voltage output digital-toanalog converters on one chip. It operates from ±5 V
power supplies and has maximum voltage output swings
of up to ±4.5 V without the addition of external components. Novel circuit topology allows for a guaranteed
monotonicity of 13 bits without the need for additional
circuitry. The SPT5400 has four separate reference voltage inputs, one for each pair of DACs. Four separate
BLOCK DIAGRAM
VDD
D12–D0
analog ground pins allow for separate offset voltages for
each DAC pair. Each DAC can be asynchronously loaded
through a common 13-bit bus into a double-buffered set
of latches. All logic inputs are TTL/CMOS compatible.
The SPT5400 is available in a 44-lead PLCC package
over the commercial temperature range of 0 °C to
+70 °C.
REFAB REFCD
REFEF REFGH
–
+
VOUTA
INPUT
LATCH A
DAC
LATCH A
DAC A
INPUT
LATCH B
DAC
LATCH B
DAC B
–
+
VOUTB
INPUT
LATCH C
DAC
LATCH C
DAC C
–
+
VOUTC
INPUT
LATCH D
DAC
LATCH D
DAC D
–
+
VOUTD
INPUT
LATCH E
DAC
LATCH E
DAC E
–
+
VOUTE
INPUT
LATCH F
DAC
LATCH F
DAC F
–
+
VOUTF
INPUT
LATCH G
DAC
LATCH G
DAC G
–
+
VOUTG
INPUT
LATCH H
DAC
LATCH H
DAC H
AGNDAB
AGNDCD
DATA BUS
CS
AGNDEF
AGNDGH
–
+
CONTROL
LOGIC
WR
A0–A2
LDAB
LDCD
LDEF
LDGH
CLR
VSS GND
VOUTH
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD to GND ............................................. –0.3 to +6 V
VSS to GND ............................................. –6 to +0.3 V
AGNDxx ..................... (GND – 0.3 V) to (VDD + 0.3 V)
Input Voltages
Digital Input Voltage to GND .. –0.3 V to (VDD + 0.3 V)
REFxx .................. (AGNDxx – 0.3 V) to (VDD + 0.3 V)
Maximum Current into REFxx Pin ................. ±10 mA
Output
VOUTxx ...................................................... VDD to VSS
Temperature
Operating Temperature, Ambient .............. 0 to +70 °C
Junction Temperature .................................... +165 °C
Lead Temperature, (soldering 10 seconds) ... +300 °C
Storage Temperature .......................... –65 to +150 °C
Power Dissipation ....................................... 1000 mW
Note 1: Operation at any Absolute Maximum Rating is not implied. Operation beyond the ratings may cause damage to the
device. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
VDD = +5 V, VSS = –5 V, REFxx = 4.096 V, AGNDxx = GND = 0 V, RL = 10 kΩ, CL = 50 pF, TA = TMIN to TMAX, unless otherwise
specified. Typical values are at TA = +25 °C.
PARAMETERS
DC Performance
Resolution
Integral Linearity
Differential Linearity
Zero Code Error1
Gain Error2
Power Supply Rejection Ratio3
∆Gain/∆VDD
∆Gain/∆VSS
Load Regulation
TEST
CONDITIONS
TEST
LEVEL
MIN
13
VI
VI
VI
VI
Guaranteed Monotonic
Reference Input
Ref Input Range4,5
Ref Input Resistance5
IV
VI
Analog Output
Maximum Output Voltage
Minimum Output Voltage
Output Slew Rate
Output Settling Time6
Digital Feedthrough
Digital Crosstalk
V
V
V
V
V
V
To ±1/2 LSB of Full Scale
±0.5
±10.0
±1.0
VI
VI
V
RL = ∞ to 10 kΩ
SPT5400
TYP
±0.4
AGND
5
MAX
UNITS
±4.0
±1.0
±20
±15
Bits
LSB
LSB
LSB
LSB
±0.0025
±0.0025
VDD
VDD – 0.5
VSS + 0.5
2.4
7.0
5
50
Digital Inputs (VDD = 5 V ±5%)
Input Voltage High
Input Voltage Low
Input Current (VIN = 0 V or VDD)
Input Capacitance
VI
VI
VI
IV
2.4
Power Supplies
Positive Supply Range (VDD)
Negative Supply Range (VSS)
Positive Supply Current
Negative Supply Current
Power Dissipation7
VI
VI
VI
VI
VI
4.75
–5.25
15
16
155
%/%
%/%
LSB
V
kΩ
V
V
V/µs
µs
nV-s
nV-s
0.8
10.0
10
V
V
µA
pF
5.25
–4.75
25
25
250
V
V
mA
mA
mW
1Deviation
of actual DAC output when all 0s are loaded to the DAC from the ideal output of –4.096 V.
of actual DAC output span from the ideal span of 8.191 V.
3PSSR is tested by changing the respective supply voltage by ±5%.
4For best performance, REF should be greater than AGND + 2 V and less than VDD – 0.6 V. The device operates
with reference inputs outside this range, but performance may degrade.
5Reference input resistance is code dependent.
6Typical settling time with 1000 pF capacitive load is 8 µs.
7Does not include reference power.
2Deviation
SPT5400
2
5/15/00
TEST LEVEL CODES
TEST LEVEL
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level
column indicates the specific device
testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and characterization data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed over
specified temperature range.
Figure 1 – Timing Diagram
t1
CS
t5
t6
t2
WR
t10
t9
A0–A2
t7
t8
D0–D12
t4
NOTES:
1. All input rise and fall times
are measured from 10% to
90% of +5 V. tR = tF = 5 ns.
2. If LD is activated while WR is
low, LD must stay low for t3 or
longer after WR goes high.
t3
LD
Table I – Timing Parameters
PARAMETER
SYMBOL MIN TYP MAX
CS Pulse Width Low
t1
50
WR Pulse Width Low
t2
50
LD Pulse Width Low
t3
50
CLR Pulse Width Low
t4
100
CS to WR Low
t5
0
CS High to WR High
t6
0
Data Valid to WR Setup
t7
20
Data Valid to WR Hold
t8
0
Address Valid to WR Setup t9
10
Address Valid to WR Hold
t10
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPT5400
3
5/15/00
GENERAL CIRCUIT DESCRIPTION
Table II – DAC Addressing
A2
0
0
0
0
1
1
1
1
The SPT5400 contains eight 13-bit, voltage-output
DACs. It uses a novel circuit topology to convert the
13-bit digital inputs into equivalent output voltages that
are proportionate to the applied reference voltages. The
SPT5400 has four separate reference voltage (REFxx)
and analog ground (AGNDxx) inputs for each DAC pair.
The REFxx inputs allow for separate full-scale output
voltages for each DAC pair. The AGNDxx inputs allow for
separate offset voltages for each DAC pair.
VOLTAGE REFERENCE AND ANALOG
GROUND INPUTS
The REFxx and AGNDxx inputs set the output range of
the corresponding DAC pair. For a detailed description of
the relationship between the DAC output range and the
REFxx and AGNDxx input voltages, see the Analog Outputs section of this datasheet.
The reference input impedance is code dependent. It is at
its highest value when the input code of the corresponding DAC pair is all 1s. It is at its lowest value when the
input code is all 0s. Because the input impedance is code
dependent, load regulation of the reference is critical.
MULTIPLYING OPERATION
Because the reference of the SPT5400 accepts both AC
and DC signals, it can be used for multiplying applications. The REFxx inputs (which set the full-scale output
voltage for the respective DACs) only accept positive
voltages, so the multiplying operation is limited to two
quadrants. Note that when applying AC signals to the reference, do not bypass the inputs.
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Function
DAC A input latch
DAC B input latch
DAC C input latch
DAC D input latch
DAC E input latch
DAC F input latch
DAC G input latch
DAC H input latch
The control inputs of the SPT5400 are level triggered,
and are shown in table III. The input latch is controlled by
CS and WR, and the transfer of data to the DAC latch is
controlled by LDxx. When CS and WR are low, the input
latch is transparent. When LDxx is low the DAC latch is
transparent. To avoid transferring data to the wrong DAC,
the address lines (A0–A2) must be valid through the time
CS and WR are low. See the timing diagram for specific
timing values. When CS and WR are high, the data is
latched into the input latch. When LDxx is high, the data is
latched into the DAC latch. If LDxx is low when CS and WR
are low, then it must be held low for t3 or longer after CS or
WR goes high.
When CLR is low, all DAC outputs are set to their corresponding AGNDxx. When CLR toggles from low to high,
1000hex is latched into all input and DAC latches.
Table III – Interface Truth Table
CLR LDxx WR
1
1
1
1
1
1
1
0
DIGITAL INPUTS AND
MICROPROCESSOR INTERFACE
All digital inputs are TTL/CMOS compatible. The
SPT5400 is compatible with microprocessors having a
minimum 13-bit-wide data bus. The microprocessor interface is double-buffered to allow all the DACs to be simultaneously updated.
0
1
1
x
x
x
0
x
0
1
x
0
1
x
x
x
CS
0
x
1
0
x
1
x
x
Function
Both latches transparent
Both latches latched
Both latches latched
Input latch transparent
Input latch latched
Input latch latched
DAC latch transparent
All input and DAC latches at
1000hex, outputs at AGNDxx
DAC ADDRESSING AND LATCHING
DIGITAL CODE
Each DAC has an input latch that receives data from the
data bus, and a DAC latch that receives data from the
input latch. The address lines (A0–A2) for each DAC input latch are shown in table II. Data is transferred from
the input latch to the DAC latch when LDxx is asserted.
The analog output of each DAC reflects the data held in
its corresponding DAC latch. In addition to being latched,
data can be transferred to the DAC directly through
transparent latches.
The SPT5400 uses offset binary coding. Conversion to a
13-bit offset binary code from a 13-bit twos-complement
code can be achieved by adding 212 = 4096.
SPT5400
4
5/15/00
POWER SUPPLY SEQUENCING
The required power-up sequence is as follows: VSS (or
VDD) first, VDD (or VSS) second, and then REF_. The
sequence in which VDD and VSS come up is not critical.
However, REF_ must come up after VDD and VSS are
established.
Fairchild strongly recommends that the digital input pins
be driven only after VDD and VSS are established. Driving
a digital input prior to establishing supplies will violate a
condition outlined in the Input Voltages section (see the
Absolute Maximum Ratings on page 2 of this data sheet)
and cause damage to the part. If either REF_ or the digital inputs must come up before VDD and VSS, due to system constraints, limit the current to the REF_ or digital
input pins to less than 1 mA.
This recommended power-up sequence must be
executed in reversed order for power-down. It should be
noted that none of the Absolute Maximum Rating conditions are violated during power-up and power-down.
ANALOG OUTPUTS
The voltage outputs to the SPT5400 are buffered internally by precision amplifiers with a 2.4 V/µs typical slew
rate. The typical settling time to ±1/2 LSB, with a fullscale transition at the outputs, is 7 µs. Each DAC output
is protected against a short to GND or AGNDxx. The typical short-circuit currents are 25 mA when the DAC is
at positive full scale, and 2.5 mA when the DAC is at
negative full scale.
BIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = 0 V)
For symmetrical bipolar operation, AGNDxx should be
tied to the system ground. The relationship between the
output voltage and the digital code is shown in table IV.
The output voltage of the DAC ladder (VDAC) is multiplied by 2 and level-shifted by the reference voltage. The
output voltage of the amplifier is given by the following
equation:
VOUT = 2(VDAC) – REFxx
Where VDAC is the voltage at the noninverting input of
the amplifier and REFxx is the voltage at the reference
input of the DAC.
With AGNDxx connected to the system ground, the output voltage of the DAC ladder is:
VDAC = (D/213)REFxx
Where D is the numeric value of the DAC’s binary input
code.
Replacing VDAC in the equation gives the output
voltage.






VOUTxx=2 213  (REFxx) − REFxx = REFxx  212 − 1 = REFxx  4096 − 1
D
D
1 LSB = REFxx
D
 1 
 4096 
D ranges from 0 to 8191 (213 –1).
Table IV – Input Code/Output Tables
Bipolar (AGNDxx = 0 V)
Input
1 1111 1111 1111
1 0000 0000 0001
1 0000 0000 0000
0 1111 1111 1111
0 0000 0000 0001
0 0000 0000 0000
Output
+REFxx (4095/4096)
+REFxx (1/4096)
0V
–REFxx (1/4096)
–REFxx (4095/4096)
–REFxx
Positive Unipolar (AGNDxx = REFxx/2)
Input
Output
1 1111 1111 1111
+REFxx (8191/8192)
1 0000 0000 0000
+REFxx/2
0 0000 0000 0000
0V
POSITIVE UNIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = REFxx/2)
For positive unipolar operation, AGNDxx should be set to
REFxx/2. The relationship between the output voltage
and the digital code is shown in table IV. For example, if a
4.096 V reference is used, AGNDxx should be offset by
2.048 V. This results in a unipolar output voltage of 0 to
4.0955 V, where 1 LSB = 500 µV. the maximum current
out of any AGNDxx pin is:
I AGNDXX =
 REFxx − AGNDxx 


5 kΩ
CUSTOM OUTPUT VOLTAGE RANGE
If the voltage at the REFxx input is higher than the voltage at the AGNDxx input, the AGNDxx inputs can be offset by any voltage within the supply rails. One way to
achieve this is to add positive offset to AGNDxx by selecting the reference voltage and the voltage at AGNDxx
such that the resulting output voltages do not come within
±0.5 V of the supply rails. Another way is to digitally offset
AGNDxx by connecting one DAC output to one or more
AGNDxx inputs. Note that a DAC output should not be
connected to its own AGNDxx input.
SPT5400
5
5/15/00
The relationship between the reference, AGNDxx and
output voltage is shown in table V.
Table V – Relationship between Reference, AGNDxx and Output
BIPOLAR OPERATION
PARAMETER
(AGNDxx = 0 V)
Bipolar Zero Level or Unipolar Mid-Scale
AGNDxx = 0 V
(Code = 1000000000000)
Differential Reference Voltage (VDR)
POSITIVE
UNIPOLAR OPERATION
(AGND = REFxx/2)
AGNDxx = REFxx/2
CUSTOM OPERATION
AGNDxx
REFxx/2
REF – AGNDxx
REFxx
Negative Full-Scale Output (Code = All 0s)
–REFxx
0V
AGNDxx – VDR
Positive Full-Scale Output (Code = All 1s)
(4095/4096)(REFxx)
(8191/8192)(REFxx)
AGNDxx + (4095/4096)(VDR)
LSB Weight
VOUTxx as a Function of Digital Code
(D, 0 to 8191)
(REFxx/4096)
(REFxx/8192)
(VDR/4096)
((D/4096)–1)(REFxx)
(D/8192)(REFxx)
AGNDxx + ((D/4096)–1)(VDR)
Figure 2 – Typical Interface Circuit (shown for unipolar operation)
Notes
CMOS/TTL Control Source
R
VOUTA
D9
Analog Buffer
CMOS/TTL Data Source
LDGH
LDEF
D10
LDED
LDAB
CLR
CS
WR
D11
A2
A1
A0
D12
R = 22 Ω
C1 = 1.0 µF
C2 = 0.1 µF
REF = 0 – VDD V
FB = Ferrite Bead
VOUTB
D8
VOUTC
D7
VOUTD
D6
VOUTE
D5
VOUTF
D4
VOUTG
SPT5400
D3
VOUTH
D2
R
D1
D0 (LSB)
C1
VDD
C1
VDD
VSS
+A5 V
-A5 V
For Bipolar Operation
AGNDxx
AGNDxx
C2
VSS
GND
R
REFxx
FB
+
R
C2
+
–
C2
+
1 kΩ
–
1 kΩ
REF
SPT5400
6
5/15/00
PACKAGE OUTLINE
44L PLCC
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
L
INCHES
MIN
MAX
0.5 typ
0.650
0.655
0.685
0.695
0.165
0.180
0.100
0.110
0.020
0.05 typ
0.026
0.032
0.013
0.021
0.590
0.630
0.145
0.156
0.009
0.011
MILLIMETERS
MIN
MAX
12.70 typ
16.51
16.64
17.40
17.65
4.19
4.57
2.54
2.79
0.51
1.27 typ
0.66
0.81
0.33
0.53
14.99
16.00
3.68
3.96
0.23
0.28
K
L
Pin 1
G
H I
TOP
VIEW
B C
J
F
A
B
C
E
D
SPT5400
7
5/15/00
PIN ASSIGNMENTS
VOUTF
VOUTE
VSS
REFEF
AGNDEF
CLR
AGNDCD
REFCD
VSS
VOUTD
VOUTC
6
VOUTB
VOUTA
VDD
REFAB
AGNDAB
Name
VDD
1 44
40
39
7
LDAB
LDCD
CS
Top View
WR
A2
A1
17
29
18
VOUTG
VOUTH
VDD
REFGH
AGNDGH
GND
LDGH
LDEF
D0
D1
D2
28
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
A0
PIN FUNCTIONS
Name
CLR
AGNDCD
REFCD
VSS
VOUTD
VOUTC
VOUTB
VOUTA
Function
Clear input (active low). Driving this asynchronous
input low sets the content of all latches to 1000hex.
All DAC outputs are reset to AGNDxx.
Analog ground for DAC C and DAC D.
Reference voltage input for DAC C and DAC C.
Bypass to AGNDCD with a 0.1 to 1 µF capacitor.
Negative power supply, –5 V (two pins). Connect
both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1 µF capacitor.
DAC D output voltage.
DAC C output voltage.
DAC B output voltage.
DAC A output voltage.
Function
Positive power supply, +5 V (two pins). Connect
both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1 µF capacitor.
REFAB
Reference voltage input for DAC A and DAC B.
Bypass to AGNDAB with a 0.1 to 1 µF capacitor.
AGNDAB Analog ground for DAC A and DAC B.
LDAB
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
A and B to the respective DAC latches.
LDCD
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
C and D to the respective DAC latches.
CS
Chip select (active low).
WR
Write input (active low). WR along with CS load data
into the DAC input latch selected by A0–A2.
A2
Address bit 2.
A1
Address bit 1.
A0
Address bit 0.
D12–D0
Data bits 12–0. (D0 = LSB)
LDEF
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
E and F to the respective DAC latches.
LDGH
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
G and H to the respective DAC latches.
GND
Digital ground.
AGNDGH Analog ground for DAC G and DAC H.
REFGH
Reference voltage input for DAC G and DAC H.
Bypass to AGNDGH with a 0.1 to 1 µF capacitor.
VOUTH
DAC H output voltage.
VOUTG
DAC G output voltage.
VOUTF
DAC F output voltage.
VOUTE
DAC E output voltage.
REFEF
Reference voltage input for DAC E and DAC F.
Bypass to AGNDEF with a 0.1 to 1 µF capacitor.
AGNDEF Analog ground for DAC E and DAC F.
ORDERING INFORMATION
PART NUMBER
SPT5400SCP
TEMPERATURE RANGE
PACKAGE
0 to +70 °C
44L PLCC
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component is any component of a life support device or
1. Life support devices or systems are devices or systems which, (a) are
system whose failure to perform can be reasonably expected to cause
intended for surgical implant into the body, or (b) support or sustain life,
the failure of the life support device or system, or to affect its safety or
and whose failure to perform, when properly used in accordance with
effectiveness.
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
www.fairchildsemi.com
© Copyright 2002 Fairchild Semiconductor Corporation
SPT5400
8
5/15/00