PD55003L-E RF POWER TRANSISTOR The LdmoST Plastic FAMILY General features ■ Excellent thermal stability ■ Common source configuration ■ POUT =3W mith 17dB gain@500MHz/12.5V ■ New leadless plastic package ■ Esd protection ■ Supplied in tape & reel of 3K units ■ In compliance with 2002/95/EC european directive PowerFLAT™ (5x5) Description The PD55003L-E is a common source NChannel, enhancement-mode lateral Field-Effect RF power transistor. It is designed for high gain, broadband commercial and industrial application. It operates at 12V in common source mode at frequencies of up to 1GHz. PD5500L-E boasts the excellent gain, linearity and reliability of STH1LV latest LD-MOS technology mounted in the innovative leadless SMD plastic package, PowerFLAT™. PIN configuration PD5500L-E’s superior linearity performances makes it an ideal solution for car mobile radio. TOP VIEW Order codes Sales Type Marking Package Packaging PD55003L-E 55003 PowerFLAT™(5x5) TAPE & REEL February 2006 Rev1 1/19 www.st.com 19 Contents: PD55003L-E Contents: 1 2 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Typical performances ....................................... 6 2.2 Typical performance (broadband) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Test circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Test circuit photomaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 Rev1 PD55003L-E Electrical data 1 Electrical data 1.1 Maximum Ratings Table 1. Absolute maximum ratings (TCASE=25°C) Symbol Parameter Value Unit V(BR)DSS Drain-Source Voltage 40 V VGS Gate-Source Volatge -0.5 to+15 V Drain Current 2.5 A Power Dissipation (@TC = 70°C) 14 W – 65 to +150 °C 150 °C Value Unit 5.7 °C/W ID PDISS Tstg Tj Storage Temperature Operating Junction Temperature 1.2 Thermal data Table 2. Thermal data Symbol Rth(j-c) Parameter Junction-Case Thermal Resistance Rev1 3/19 Electrical specification 2 PD55003L-E Electrical specification (TCASE=25°C) Table 3. Static Symbol Test Condictions IDSS Min. Max. Unit VGS=0V, VDS=28V 1 µA IGSS VGS=20V, VDS=0V 1 µA VGS(Q) VDS=10V, ID=50mA 5.0 V VDS(ON) VGS=10V, ID=0.5A 0.36 V gfs VDS=10V, ID=1A 1.0 mho VGS=0V, VDS=12.5V, f=1MHz 34 23 1.8 pF pF pF 2.0 Ciss Coss Crss Table 4. Typ. Dynamic Symbol Test Condictions Min. P1dB VDD=12.5V, IDQ=50mA, f=500MHz 3 GP VDD=12.5V, IDQ=50mA, POUT=3W, f=500MHz 17 19 dB ηD VDD=12.5V, IDQ=50mA, POUT=3W, f=500MHz 50 52 % Load mismatch VDD=12.5V, IDQ=50mA, POUT=3W, f=500MHz 20:1 Table 5. Table 6. 4/19 Typ. Max. W VSWR Switching on/off (inductive load) Test Condictions Class Human Body Model 2 Machine Model M3 Switching energy (inductive load) Test Methodology Rating J-STD-020B MSL 3 Rev1 Unit PD55003L-E Electrical specification Figure 1. Typical Input/Drain load Impedances D ZDL Typical Input Impedance Typical Drain Load Impedance G Zin S Table 7. Impedance Data FREQ. MHz ZIN(Ω) ZDL(Ω) 480 1.79 - j 4.96 10.68 + j 7.45 500 1.88 - j 5.93 10.28 + j 8.92 520 2.10 - j 7.03 9.86 + j 10.18 Rev1 5/19 Electrical specification PD55003L-E 2.1 Typical performances Figure 2. Capacitance Vs supply Voltage Figure 3. 1 00 0 Output Power Vs Input Power 6 f = 1 MHz 5 Idq = 70 mA Idq = 50 mA 10 0 4 Pout (W) C (pF) C is s 3 C oss 10 2 C rs s 1 Vds = 12.5 V f = 500 MHz 1 0 0 2 Figure 4. 4 6 8 Vd s (V) 10 12 14 16 Power Gain Vs Output Power 0 Figure 5. 24 25 50 Pin (mW) 75 100 125 Efficiency Vs Output Power 70 22 60 Idq = 50 mA Idq = 70mA 20 50 Nd (%) Gp (dB) Idq = 50 mA 18 Idq = 30 mA 16 40 Idq = 70 mA 30 Idq = 20 mA 14 20 12 10 Vds = 12.5 V f = 500 MHz Vds = 12.5 V f = 500 MHz 10 0 0.0 Figure 6. 0.5 1.0 1.5 2.0 2.5 Pout (W) 3.0 3.5 4.0 4.5 5.0 0.0 Input Return Loss Vs Output Power Figure 7. 0.5 1.0 1.5 2.0 2.5 Pout (W ) 3.0 3.5 4.0 4.5 5.0 Output Power Vs Bias Current 7 0 6 -5 5 Pout (W) RL (dB) -10 Idq = 50 mA -15 4 3 Idq = 70 mA -20 2 -25 Pin = 20 dBm f = 500 MHz Vdd = 12.5 V 1 Vds = 12.5 V f = 500 MHz 0 -30 0.0 6/19 0.5 1.0 1.5 2.0 2.5 Pout (W) 3.0 3.5 4.0 4.5 0 5.0 Rev1 50 100 150 200 250 Idq (mA) 300 350 400 450 500 PD55003L-E Efficiency Vs Bias Current Figure 9. 80 8 70 7 60 6 50 5 Pout (W) Nd (%) Figure 8. Electrical specification 40 Output Power Vs Supply Voltage 4 3 30 2 20 Pin = 20 dBm f = 500 MHz Vdd = 12.5 V 10 Idq = 50 mA Pin = 20 dBm f = 500 MHz 1 0 0 0 50 100 150 200 250 Idq (mA) 300 350 400 450 5 500 6 7 8 9 10 Vds (V) 11 12 13 14 15 Figure 10. Output Power Vs Gate-Source Voltage 7 6 Pout (W) 5 4 3 2 Pin = 20 dBm Vdd = 12.5 V f = 500 MHz 1 0 0.0 0.5 1.0 1.5 2.0 Vgs (V) 2.5 3.0 3.5 4.0 Rev1 7/19 Electrical specification 2.2 PD55003L-E Typical performance (broadband) Figure 11. Power Gain Vs Frequency Figure 12. Efficiency Vs Frequency 60 20 18 50 16 40 12 Nd (%) Gp (dB) 14 10 30 8 20 6 4 10 Vd s = 1 2.5 V Id q = 50 m A P o ut = 3 W 2 0 0 47 0 48 0 4 90 50 0 51 0 f (MHz ) 5 20 53 0 4 70 5 40 Figure 13. Return Loss Vs Frequency 0 -5 RL (dB) - 10 - 15 - 20 - 25 Vds = 12.5 V Id q = 5 0 m A P ou t = 3 W - 30 4 70 8/19 Vd s = 1 2.5 V Idq = 50 m A P out = 3 W 4 80 49 0 500 510 f (MHz ) 5 20 53 0 54 0 Rev1 48 0 49 0 5 00 51 0 f (MHz ) 52 0 5 30 540 PD55003L-E 3 Test circuit schematic Test circuit schematic VGG 2 1 C13 B1 + C8 C7 C6 R1 VDD B2 C14 R3 1 2 C15 C16 L C5 R4 Z7 Z8 Z9 Z10 C12 RF out C1 Z1 Z2 Z3 Z4 Q RF in N1 Table 8. C2 C3 C4 N2 Z6 Z5 C9 C10 C11 Z1 0.709” X 0.08” Z2 0.551” X 0.08” Z3 0.217” X 0.08” Z4 0.059” X 0.08” Z5 0.452” X 0.223” Z6 0.260” X 0.223” Z7 0.118” X 0.08” Z8 0.315” X 0.08” Z9 Z10 0.866” X 0.08” 0.512” X 0.08” Test Circuit Component List Component Description B1, B2 FERRIDE BEAD C1, C12 3000Pf, 100B ATC CHIP CAPACITOR C2, C3 15pF, 100B ATC CHIP CAPACITOR C4, C9 0 -:- 20 pF VARIABLE CAPACITOR JOHANSON C5, C13 120pF 100B ACT CHIP CAPACITOR C6, C14 0.1mF 100B ACT CAPACITOR C7, C15 1200pF 100B ACT CAPACITOR C8, C16 10µF, 35V, SMD ELECTROLYTIC CAPACITOR C10 0.5 -:- 5pF VARIABLE CAPACITOR JOHANSON C11 0.8 -:- 10pF VARIABLE CAPACITOR JOHANSON R1 33KΩ CHIP RESISTOR 1W R2, R3 15Ω MELF RESISTOR 1W R4 1KΩ CHIP RESISTOR 1W N1, N2 TYPE N FLANGE MOUNT BOARD ROGER ULTRA LAM 2000 THK 0.030” εr = 2.55 2OZ ED Cu BOTH SIDES Rev1 9/19 Test circuit schematic PD55003L-E Test Circuit 3.2 Test circuit photomaster 4 inches 3.1 6.4 inches 10/19 Rev1 PD55003L-E Test circuit schematic Table 9. S-Parameter (PD55003L) (VDS=12.5V, IDS=0.15A) FREQ IS11I S11∠Φ IS21I S21∠Φ IS12I S12∠Φ IS22I S22∠Φ (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 0.808 0.772 0.771 0.779 0.794 0.809 0.824 0.839 0.853 0.865 0.874 0.885 0.894 0.901 0.906 0.911 0.916 0.918 0.922 0.925 0.925 0.928 0.927 0.928 0.929 0.927 0.927 0.925 0.922 0.922 -110 -141 -152 -157 -161 -163 -165 -166 -168 -169 -171 -172 -173 -174 -175 -176 -177 -178 -179 180 179 178 177 176 175 175 174 173 172 172 20.14 11.77 7.86 5.80 4.50 3.62 2.98 2.50 2.13 1.83 1.59 1.39 1.23 1.10 0.97 0.88 0.79 0.72 0.65 0.59 0.54 0.50 0.46 0.43 0.40 0.37 0.34 0.32 0.30 0.28 112 93 82 73 66 60 54 49 44 40 36 33 29 26 23 20 18 15 13 11 9 7 5 4 2 1 -1 -2 -4 -5 0.039 0.042 0.041 0.040 0.038 0.035 0.033 0.031 0.028 0.025 0.023 0.021 0.018 0.016 0.015 0.012 0.011 0.010 0.008 0.007 0.007 0.006 0.007 0.008 0.010 0.011 0.011 0.012 0.014 0.016 22 5 -5 -11 -17 -22 -26 -30 -32 -34 -36 -36 -37 -37 -36 -32 -28 -22 -13 -7 8 21 38 51 56 61 65 68 72 73 0.672 0.633 0.642 0.665 0.694 0.721 0.750 0.774 0.796 0.818 0.837 0.852 0.867 0.880 0.890 0.902 0.909 0.918 0.922 0.928 0.934 0.938 0.941 0.944 0.947 0.953 0.951 0.952 0.954 0.957 -109 -138 -147 -151 -154 -155 -157 -159 -160 -161 -163 -164 -165 -166 -167 -169 -169 -171 -171 -172 -173 -174 -175 -176 -176 -177 -178 -178 -179 -180 Rev1 11/19 Test circuit schematic Table 10. PD55003L-E S-Parameter (PD55003L) (VDS=12.5V, IDS=0.8A) 12/19 FREQ IS11I S11∠Φ IS21I S21∠Φ IS12I S12∠Φ IS22I S22∠Φ (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 0.841 0.800 0.800 0.803 0.812 0.822 0.830 0.837 0.848 0.857 0.866 0.874 0.882 0.887 0.893 0.898 0.903 0.904 0.909 0.911 0.914 0.916 0.917 0.917 0.918 0.917 0.917 0.914 0.912 0.911 -124 -150 -159 -163 -166 -168 -169 -170 -172 -172 -174 -174 -175 -176 -177 -178 -179 -180 179 179 178 177 176 176 175 174 173 173 172 171 22.20 12.84 8.59 6.38 5.00 4.07 3.39 2.87 2.47 2.15 1.89 1.67 1.49 1.33 1.19 1.08 0.98 0.89 0.82 0.75 0.69 0.64 0.59 0.55 0.51 0.47 0.44 0.42 0.39 0.36 107 92 83 76 70 64 59 55 50 46 42 39 35 32 29 26 23 21 19 16 14 12 10 8 6 5 3 1 0 -2 0.029 0.031 0.031 0.030 0.028 0.027 0.025 0.024 0.022 0.020 0.018 0.017 0.015 0.013 0.012 0.011 0.010 0.009 0.008 0.008 0.008 0.008 0.009 0.010 0.010 0.012 0.013 0.013 0.015 0.016 21 6 -2 -8 -11 -15 -17 -20 -23 -23 -25 -23 -24 -22 -16 -15 -11 -1 7 16 27 35 43 48 57 62 63 67 71 72 0.651 0.654 0.666 0.684 0.702 0.721 0.740 0.760 0.777 0.795 0.813 0.825 0.839 0.853 0.863 0.875 0.885 0.893 0.901 0.904 0.911 0.916 0.919 0.923 0.929 0.929 0.934 0.936 0.938 0.941 -130 -153 -159 -161 -163 -163 -164 -165 -166 -166 -167 -168 -168 -169 -170 -171 -172 -173 -173 -174 -175 -175 -176 -177 -177 -178 -179 -179 -180 179 Rev1 PD55003L-E Test circuit schematic Table 11. S-Parameter (PD55003L) (VDS=12.5V, IDS=1.5A) FREQ IS11I S11∠Φ IS21I S21∠Φ IS12I S12∠Φ IS22I S22∠Φ (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 0.837 0.799 0.801 0.809 0.823 0.835 0.845 0.855 0.866 0.876 0.882 0.892 0.898 0.903 0.907 0.909 0.912 0.915 0.917 0.917 0.918 0.920 0.920 0.920 0.919 0.919 0.918 0.917 0.914 0.912 -114 -143 -154 -159 -163 -165 -167 -169 -170 -171 -173 -174 -175 -176 -177 -178 -179 -180 179 178 178 177 176 175 174 174 173 172 172 171 18.43 10.49 6.99 5.15 4.00 3.22 2.66 2.23 1.91 1.65 1.44 1.26 1.12 1.00 0.90 0.81 0.73 0.67 0.61 0.56 0.51 0.47 0.44 0.41 0.38 0.35 0.33 0.31 0.29 0.27 111 93 82 74 67 61 56 52 47 43 39 36 33 29 27 24 21 19 17 15 13 11 9 7 6 4 3 1 0 -1 0.030 0.033 0.032 0.031 0.029 0.028 0.025 0.024 0.022 0.020 0.018 0.016 0.015 0.013 0.011 0.010 0.009 0.009 0.008 0.008 0.008 0.009 0.010 0.010 0.012 0.013 0.014 0.015 0.016 0.018 24 6 -3 -9 -14 -18 -20 -24 -26 -24 -25 -25 -25 -20 -17 -10 -6 1 17 24 32 40 48 57 59 61 63 68 70 71 0.588 0.632 0.656 0.680 0.701 0.726 0.750 0.768 0.789 0.812 0.828 0.836 0.844 0.857 0.868 0.883 0.889 0.894 0.905 0.907 0.908 0.912 0.919 0.922 0.926 0.931 0.928 0.929 0.933 0.935 -132 -152 -158 -160 -162 -163 -164 -165 -166 -167 -167 -168 -169 -170 -171 -171 -172 -173 -174 -174 -175 -176 -177 -177 -178 -179 -179 -180 180 179 Rev1 13/19 Package mechanical data 4 PD55003L-E Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 14/19 Rev1 PD55003L-E Package mechanical data Table 12. PowerFLAT™ Mechanical Data mm inch Dim. MIN. TYP. MAX. A 0.90 A1 0.02 A3 0.24 MIN. TYP. MAX. 1.00 0.035 0.039 0.05 0.001 0.002 0.009 AA 0.15 0.25 0.35 0.006 0.01 0.014 b 0.43 0.51 0.58 0.017 0.020 0.023 c 0.64 0.71 0.79 0.025 0.028 0.031 D 5.00 0.197 d 0.30 0.011 E 5.00 0.197 E2 2.49 2.57 2.64 0.098 0.101 e 1.27 0.050 f 3.37 0.132 g 0.74 0.03 h 0.21 0.008 0.104 Figure 14. PowerFLAT™ Package Dimensions Rev1 15/19 Package mechanical data Table 13. PD55003L-E PowerFLAT™ Tape & Reel Dimensions mm. DIM. MIN. TYP MAX. Ao 5.15 5.25 5.35 Bo 5.15 5.25 5.35 Ko 1.0 1.1 1.2 Figure 15. PowerFLAT™ Tape & Reel 16/19 Rev1 PD55003L-E Table 14. Package mechanical data Recommended FOOTPRINT Rev1 17/19 Revision history PD55003L-E 5 Revision history Table 15. Document revision history Date Revision 14-Feb-2006 1 18/19 Changes First Issue Rev1 PD55003L-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Rev1 19/19