FAIRCHILD FDD5810-F085

FDD5810
N-Channel Logic Level Trench® MOSFET
60V, 36A, 27mΩ
Applications
„ RDS(ON) = 22mΩ (Typ.), VGS = 5V, ID = 29A
„ Motor / Body Load Control
„ Qg(5) = 13nC (Typ.), VGS = 5V
„ ABS Systems
„ Low Miller Charge
„ Powertrain Management
„ Low Qrr Body Diode
„ Injection System
„ UIS Capability (Single Pulse / Repetitive Pulse)
„ DC-DC converters and Off-line UPS
„ Qualified to AEC Q101
„ Distributed Power Architecture and VRMs
„ RoHS Compliant
„ Primary Switch for 12V and 24V systems
A
REE I
DF
M ENTATIO
LE
N
MP
LE
Features
D
D
G
S
G
D-PAK
TO-252
(TO-252)
©2006 Fairchild Semiconductor Corporation
FDD5810 Rev. A (W)
S
1
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FDD5810 N-Channel Logic Level Trench® MOSFET
October 2007
Symbol
VDSS
Drain to Source Voltage
Ratings
60
Units
V
VGS
Gate to Source Voltage
±20
V
Drain Current Continuous (VGS = 10V)
37
A
Drain Current Continuous (VGS = 5V)
33
A
7.4
A
ID
Parameter
Continuous (TA = 25oC, VGS = 10V, with RθJA = 52oC/W)
Pulsed
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Figure 4
A
45
mJ
Power Dissipation
72
W
Derate above 25oC
0.48
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
RθJC
RθJA
Maximum Thermal resistance Junction to Case TO-252
Thermal Resistance Junction to Ambient TO-252,
1in2
copper pad area
2.1
oC/W
52
oC/W
Package Marking and Ordering Information
Device Marking
FDD5810
Device
FDD5810
Package
TO-252AA
Reel Size
330mm
Tape Width
16mm
Quantity
2500 units
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
60
-
-
-
V
-
1
-
-
250
VGS = ±20V
-
-
±100
nA
VGS = VDS, ID = 250μA
1
1.6
2
V
ID = 32A, VGS = 10V
-
18
22
ID = 29A, VGS = 5V
-
22
27
ID = 32A, VGS = 10V,
TJ = 175oC
-
43
53
-
1420
1890
pF
-
150
200
pF
-
65
100
pF
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250μA, VGS = 0V
VDS = 48V
VGS = 0V
TC = 150oC
μA
On Characteristics
VGS(TH)
RDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
mΩ
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
RG
Gate Resistance
f = 1MHz
-
3.5
-
Ω
Qg
Total Gate Charge at 10V
VGS = 0V to 10V
-
24
34
nC
Qg
Total Gate Charge at 5V
VGS = 0V to 5V
-
13
18
nC
Qg(th)
Threshold Gate Charge
VGS = 0V to 1V
-
1.3
-
nC
Qgs
Gate to Source Gate Charge
-
4.0
-
nC
Qgs2
Gate Charge Threshold to Plateau
-
2.7
-
nC
Qgd
Gate to Drain “Miller” Charge
-
5.0
-
nC
FDD5810 Rev. A (W)
VDS = 25V, VGS = 0V,
f = 1MHz
2
VDD = 30V
ID = 35A
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FDD5810 N-Channel Logic Level Trench® MOSFET
Absolute Maximum Ratings TC = 25°C unless otherwise noted
ton
Turn-On Time
-
-
130
ns
td(on)
Turn-On Delay Time
-
12
-
ns
tr
Rise Time
-
75
-
ns
td(off)
Turn-Off Delay Time
-
26
-
ns
tf
Fall Time
-
34
-
ns
toff
Turn-Off Time
-
-
90
ns
ISD = 32A
-
-
1.25
V
ISD = 16A
-
-
1.0
V
VDD = 30V, ID = 35A
VGS = 5V, RGS = 11Ω
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
IF = 35A, di/dt = 100A/μs
-
-
39
ns
Qrr
Reverse Recovery Charge
IF = 35A, di/dt = 100A/μs
-
-
35
nC
Notes:
1: Starting TJ = 25°C, L = 110μH, IAS = 28A, VDD = 54V, VGS = 10V.
FDD5810 Rev. A (W)
3
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FDD5810 N-Channel Logic Level Trench® MOSFET
Switching Characteristics
40
1.0
ID , DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
30
VGS = 10V
20
VGS = 5V
10
0.2
0
25
0
0
25
50
75
100
150
125
TC , CASE TEMPERATURE
175
50
(oC)
75
TC, CASE
Figure 1. Normalized Power Dissipation vs Case
Temperature
100
125
150
175
TEMPERATURE(oC)
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x RθJC + TC
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
IDM, PEAK CURRENT (A)
600
TC = 25oC
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
100
VGS = 5V
30
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
FDD5810 Rev. A (W)
4
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FDD5810 N-Channel Logic Level Trench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
500
10us
10
100us
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(on)
1
IAS, AVALANCHE CURRENT (A)
ID , DRAIN CURRENT (A)
200
100
SINGLE PULSE
1ms
TJ = MAX RATED
o
TC = 25 C
10ms
DC
0.1
1
10
100
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
200
0.001
0.01
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
1
10
100
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
60
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
VDD = 6V
VGS = 4.5V
VGS = 10V
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
60
0.1
tAV, TIME IN AVALANCHE (ms)
40
TJ = 25oC
20
VGS = 5V
VGS = 4V
40
VGS = 3.5V
20
VGS = 3V
TJ = 175oC
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
TJ = -55oC
0
2.0
1.0
4.0
3.0
5.0
0
Figure 7. Transfer Characteristics
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
26
ID = 35A
22
ID = 1A
14
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
FDD5810 Rev. A (W)
1.5
2.0
2.5
2.8
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
2
1.0
Figure 8. Saturation Characteristics
30
18
0.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
RDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
TC = 25oC
0
0
2.4
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
2.0
1.6
1.2
0.8
0.4
-80
ID = 32A
VGS = 10V
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE(oC)
160
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
5
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FDD5810 N-Channel Logic Level Trench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
1.4
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250μA
1.1
0.8
0.5
ID = 250μA
1.1
1.0
0.9
0.2
-80
-40
0
40
80
120
160
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
40
80
120
160
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10
VGS , GATE TO SOURCE VOLTAGE (V)
10000
Ciss
C, CAPACITANCE (pF)
0
TJ , JUNCTION TEMPERATURE (oC)
1000
Coss
Crss
100
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 35A
ID = 1A
2
VGS = 0V, f = 1MHz
10
0
1
0.1
10
60
0
VDS , DRAIN TO SOURCE VOLTAGE (V)
10
15
20
25
Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source
Voltage
FDD5810 Rev. A (W)
5
Figure 14. Gate Charge Waveforms for Constant
Gate Current
6
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FDD5810 N-Channel Logic Level Trench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Definition
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I31
© 2007 Fairchild Semiconductor Corporation
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