February 2009 NDT451AN N-Channel Enhancement Mode Field Effect Transistor General Description Features Power SOT N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. 7.2A, 30V. RDS(ON) = 0.035Ω @ VGS = 10V RDS(ON) = 0.05Ω @ VGS = 4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ________________________________________________________________________________ D D G Absolute Maximum Ratings Symbol Parameter VDSS S T A= 25°C unless otherwise noted NDT451AN Units Drain-Source Voltage 30 V VGSS Gate-Source Voltage ± 20 V ID Drain Current - Continuous ± 7.2 A (Note 1a) - Pulsed PD Maximum Power Dissipation ± 25 (Note 1a) (Note 1b) (Note 1c) TJ,TSTG Operating and Storage Temperature Range 3 W 1.3 1.1 -65 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W @ 2009 Fairchild Semiconductor Corporation NDT451AN Rev. D1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 V TJ = 55°C 1 µA 10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA 3 V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 7.2 A 1 TJ = 125°C 0.7 TJ = 125°C VGS = 4.5 V, ID = 6.0 A TJ = 125°C ID(on) gFS On-State Drain Current Forward Transconductance VGS = 10 V, VDS = 5 V 25 VGS = 4.5 V, VDS = 5 V 15 1.6 1.2 2.2 0.03 0.035 0.042 0.063 0.042 0.05 0.058 0.09 Ω A VDS = 10 V, ID = 7.2 A 11 S VDS = 15 V, VGS = 0 V, f = 1.0 MHz 720 pF 370 pF 250 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 10 V, ID = 1 A, VGEN = 10 V, RGEN = 6 Ω VDS = 10 V, ID = 7.2 A, VGS = 10 V 12 20 ns 13 30 ns 29 50 ns 10 20 ns 19 30 nC 2.3 nC 5.5 nC NDT451AN Rev. D1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 2.3 A DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 7.2A trr Reverse Recovery Time VGS = 0 V, IF = 1.25 A, dIF/dt = 100 A/µs 0.9 (Note 2) 1.3 V 100 ns Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = T J−TA R θJ A(t ) = T J−TA R θJ C+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 42oC/W when mounted on a 1 in2 pad of 2oz copper. b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper. c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDT451AN Rev. D1 Typical Electrical Characteristics VGS =10V 20 3 6.0 5.0 4.5 R DS(ON), NORMALIZED 4.0 15 3.5 10 3.0 5 0 0 0.5 1 1.5 2 V DS , DRAIN-SOURCE VOLTAGE (V) 2.5 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) 25 VGS = 3.0V 2.5 6.0 10 0 5 10 15 I D , DRAIN CURRENT (A) 20 25 2 VGS = 10V ID = 7.2A 1.4 R DS(ON), NORMALIZED VGS =10V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 5.0 1 1.6 1.75 TJ = 125°C 1.5 1.25 25°C 1 -55°C 0.75 0.5 150 Figure 3. On-Resistance Variation with Temperature. 0 5 10 15 I D , DRAIN CURRENT (A) 20 25 Figure 4. On-Resistance Variation with Drain Current and Temperature. 1.2 V DS = 10V 25°C 125°C V th, NORMALIZED 20 TJ = -55°C 15 10 5 1 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 6 GATE-SOURCE THRESHOLD VOLTAGE 25 ID , DRAIN CURRENT (A) 4.5 1.5 Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. Figure 1. On-Region Characteristics. 0 4.0 2 0.5 3 3.5 V DS = VGS I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 125 150 TJ , JUNCTION TEMPERATURE (°C) Figure 6. Gate Threshold Variation with Temperature. NDT451AN Rev. D1 Typical Electrical Characteristics 25 I D = 250µA 1.05 1 0.95 0.9 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 1 TJ = 125°C 25°C -55°C 0.1 0.01 0.001 0.2 0.4 0.6 0.8 1 1.2 1.4 V SD , BODY DIODE FORWARD VOLTAGE (V) Figure 7. Breakdown Voltage Variation with Temperature. Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. 10 2000 I D = 7.2A V GS , GATE-SOURCE VOLTAGE (V) 1500 1000 CAPACITANCE (pF) VGS =0V 10 I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 C iss C oss 500 f = 1 MHz 200 C rss V GS = 0V 100 0.1 0.2 0.5 V DS 1 2 5 10 20 30 , DRAIN TO SOURCE VOLTAGE (V) V DS = 5V 10V 8 20V 6 4 2 0 0 5 10 15 Q g , GATE CHARGE (nC) 20 25 Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. g FS, TRANSCONDUCTANCE (SIEMENS) 20 V DS = 10V TJ = -55°C 16 25°C 12 125°C 8 4 0 0 5 10 15 20 25 I D , DRAIN CURRENT (A) Figure 11. Transconductance Variation with Drain Current and Temperature. NDT451AN Rev. D1 Typical Thermal Characteristics 8 1a 3 2.5 2 1.5 1b 1c 1 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 10 RD ID , DRAIN CURRENT (A) 5 O S( LIM N) 10 IT 1m 10 1 1s 10 s DC 0.5 0.2 VGS = 1 0 V 0.1 10 0m 1a 7 6 5 1b 1c 4.5"x5" FR-4 Board 4 TA = 2 5 o C Still Air VG S = 1 0 V 3 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 13. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figure 12. SOT-223 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 30 I D , STEADY-STATE DRAIN CURRENT (A) STEADY-STATE POWER DISSIPATION (W) 3.5 0u s s ms s SINGLE PULSE 0.05 R θJ A = See Note 1c T A = 25°C 0.01 0.1 0.2 0.5 1 2 5 10 V DS , DRAIN-SOURCE VOLTAGE (V) 30 50 Figure 14. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.005 R JA (t) = r(t) * R JA θ θ R JA = See Note 1 c θ P(pk) t1 0.01 Single Pulse 0.002 0.001 0.0001 t2 TJ - TA = P * R (t) θJA Duty Cycle, D = t 1 / t 2 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDT451AN Rev. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I38 NDT451AN Rev. D1