FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET Features General Description ■ 5.5 A, 30 V. These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. RDS(ON) = 38 mΩ @ VGS = 10 V RDS(ON) = 50 mΩ @ VGS = 4.5 V Fast switching speed Low gate charge High performance trench technology for extremely low RDS(ON) High power and current handling capability ■ ■ ■ ■ D2 These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. D2 5 4 6 3 7 2 8 1 D1 D1 SO-8 Pin 1 S1 G1 S2 G2 Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage Ratings Units 30 V ± 20 V 5.5 A VGSS Gate-Source Voltage ID Drain Current PD Power Dissipation for Dual Operation (Note 1) 2 Power Dissipation for Single Operation (Note 1a) 1.6 (Note 1b) 1 – Continuous (Note 1a) – Pulsed 20 (Note 1c) TJ, TSTG W 0.9 Operating and Storage Junction Temperature Range –55 to 150 °C Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS6930B FDS6930B 13" 12mm 2500 units ©2010 Fairchild Semiconductor Corporation FDS6930B Rev. A1 1 www.fairchildsemi.com FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET March 2010 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V VDS = 24 V, VGS = 0 V, TJ = 55°C IGSS Gate–Source Leakage VGS = ±20 V, VDS = 0 V On Characteristics 30 V mV/°C 26 1 10 µA ±100 nA (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA ∆VGS(th) ∆TJ Gate Threshold Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C –4.6 RDS(on) Static Drain–Source On–Resistance VGS = 10 V, ID = 5.5 A VGS = 4.5 V, ID = 4.8 A VGS = 10 V, ID = 5.5 A, TJ = 125°C 31 40 45 1 1.9 3 V mV/°C 38 50 62 20 mΩ ID(on) On–State Drain Current VGS = 10 V, VDS = 5 V gFS Forward Transconductance VDS = 5 V, ID = 5.5 A 19 A VDS = 15 V, V GS = 0 V, f = 1.0 MHz 310 412 90 120 pF 40 60 pF S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Resistance Switching Characteristics VGS = 15 mV, f = 1.0 MHz pF Ω 1.9 (Note 2) td(on) Turn–On Delay Time tr Turn–On Rise Time td(off) tf 6 12 ns 6 12 ns Turn–Off Delay Time 16 28 ns Turn–Off Fall Time 2 4 ns 2.7 3.8 Qg Total Gate Charge Qgs Gate–Source Charge Qgd Gate–Drain Charge VDD = 15 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω VDS = 15 V, ID = 5.5 A, VGS = 5 V nC 1.0 nC 0.7 nC Drain–Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain–Source Diode Forward Current 1.3 A VSD Drain–Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) 0.8 1.2 V trr Diode Reverse Recovery Time (note3) IF = 5.5 A, diF/dt = 100 A/µs 16 32 Qrr Diode Reverse Recovery Charge 6 nS nC Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 78°C/W when mounted on a 0.5 in2 pad of 2 oz copper b) 125°C/W when mounted on a 0.02 in2 pad of 2 oz copper c) 135°C/W when mounted on a minimum pad. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% 3. Trr parameter will not be subjected to 100% production testing. 2 FDS6930B Rev. A1 www.fairchildsemi.com FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET Electrical Characteristics TA = 25°C unless otherwise noted 20 2 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 4.0V VGS = 10V ID, DRAIN CURRENT (A) 16 4.5V 6.0V 3.5V 12 8 3.0V 4 0 1.8 VGS = 3.5V 1.6 1.4 4.0V 4.5V 5.0V 1.2 6.0V 10.0V 1 0.8 0 0.5 1 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 2 0 Figure 1. On-Region Characteristics. 16 20 0.12 ID = 5.5A VGS = 10.0V ID = 2.75A RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 8 12 ID, DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 1.4 1.2 1 0.8 0.6 0.1 0.08 TA = 125°C 0.06 0.04 TA = 25°C 0.02 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (oC) 125 150 2 Figure 3. On-Resistance Variation with Temperature. 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 20 100 VGS = 0V IS, REVERSE DRAIN CURRENT (A) VDS = 5V 16 I D, DRAIN CURRENT (A) 4 12 8 TA = 125° C -55°C 4 25°C 0 10 TA = 125°C 1 25°C 0.1 -55°C 0.01 0.001 0.0001 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5 0 1.2 Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. Figure 5. Transfer Characteristics. 3 FDS6930B Rev. A1 0.2 0.4 0.6 0.8 1 VSD, BODY DIODE FORWARD VOLTAGE (V) www.fairchildsemi.com FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics 500 10 f = 1 MHz VGS = 0 V VGS, GATE-SOURCE VOLTAGE (V) ID = 5.5A 400 VDS = 5V CAPACITANCE (pF) 8 15V 6 10V 4 300 Ciss 200 Coss 2 100 0 0 Crss 0 1 2 3 4 Qg, GATE CHARGE (nC) 5 0 6 Figure 7. Gate Charge Characteristics. 50 P(pk), PEAK TRANSIENT POWER (W) 100µs ID, DRAIN CURRENT (A) 20 Figure 8. Capacitance Characteristics. 100 RDS(ON) LIMIT 10 1ms 10ms 100ms 1s 1 10s DC VGS = 10.0V SINGLE PULSE RθJA = 135°C/W 0.1 TA = 25°C 0.01 0.01 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) SINGLE PULSE RθJA = 135°C/W TA = 25°C 40 30 20 10 0 0.001 100 0.01 0.1 1 t1, TIME (sec) 10 100 Figure 10. Single Pulse Maximum Power Dissipation. Figure 9. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 D = 0.5 RθJA(t) = r(t) * RθJA 0.2 0.1 RθJA = 135°C/W 0.1 P(pk) 0.05 0.02 0.01 t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.01 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. 4 FDS6930B Rev. A1 www.fairchildsemi.com FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I48