MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR <Application <Application Specific Specific Intelligent Intelligent Power Power Module> Module> ARY N I M I PREL PS11017 PS11017 . ge. ation ecific ct to chan je nal sp ot a fiits are sub n is is e: Th tric lim Notice parame Som FLAT-BASE FLAT-BASE TYPE TYPE INSULATED INSULATED TYPE TYPE PS11017 INTEGRATED FUNCTIONS AND FEATURES • 3-phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technologies. • Circuit for dynamic braking of motor regenerative energy. • Inverter output current capability IO (Note 1): 100% load Type Name 150% over load 17.0A (rms) 25.5A (rms), 1min PS11017 (Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO × √ 2 INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS: • For P-Side IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short-circuit protection (SC), Bootstrap circuit supply scheme (Single drive-power-supply) and Under voltage protection (UV). • For N-Side IGBTs : Drive circuit, Short circuit protection (SC), Control-supply Under voltage and Over voltage protection (OV/UV), System Over-temperature protection (OT), Fault output (FO ) signaling circuit, and Current-Limit warning signal output (CL) • For Brake circuit IGBT : Drive circuit • Warning and Fault signaling : FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side control supply abnormality locking (OV/UV) FO3 : System over-temperature protection (OT). CL : Warning for inverter current overload condition • For system feedback control : Analogue signal feedback reproducing actual inverter phase current (3φ). • Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection. APPLICATION Acoustic noise-less 3.7kW/AC200V class 3 phase inverter and other motor control applications. PACKAGE OUTLINES 4-R2 1 7 5 2 ± 0.3 20.4 ± 1 MOUNTING HOLE 23 0.5 4-R5 5 (102) 63 ± 0.8 4-φ 60 ± 0.5 5 (22) 15.5 6 ± 0.3 1 5 3 36 10 31 1 ± 0.3 15.5 32 41 ± 0.5 50 76 ± 1 15.5 0.5 10 56 ± 0.8 4-φ4.5 12.7 ± 0.3 63.5 ± 0.8 4-φ3.2 3 17.5 17 ± 0.8 105 ± 0.5 115 ± 1 Terminals Assignment: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CBU+ CBU– CBV+ CBV– CBW+ CBW– GND NC VDH CL FO1 FO2 FO3 CU CV CW UP VP WP UN VN WN Br 31 32 33 34 35 36 P Br N U V W 96 13 LABEL 8.5 2.5 (Fig. 1) Jan. 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> RY INA ELIM PS11017 on. ange. ificati h l spec ct to c a finaare subje t o n is its is m h li T e: tric Notice parame Som PR Protection Circuit CBW+ CBW– CBV+ CBV– CBU+ Application Specific Intelligent Power Module INTERNAL FUNCTIONS BLOCK DIAGRAM CBU– FLAT-BASE TYPE INSULATED TYPE Level shifter Drive Circuit P Brake resistor connection, Inrush prevention circuit, etc. B AC 200V line input R U V W S T Z M AC 200V line output C T S N Z : Surge absorber. C : AC filter (Ceramic condenser 2.2~6.5nF) [Note : Additionally an appropriate Line-to line surge absorber circuit may become necessary depending on the application environment]. Current sensing circuit CU CV CW Drive Circuit Input signal conditioning Fo Logic UP V P W P UN V N W N B r CL, FO1, FO2, FO3 Analogue signal output corresponding to PWM input each phase current (5V line) Note 1) (5V line) Note 2) Protection circuit Control supply fault sense Fault output (5V line) Note 3) GND VDH Note 1) To prevent chances of signal oscillation, a series resistor (1kΩ) coupling at each output is recommended. Note 2) By virtue of integrating an photo-coupler inside the module, direct coupling to CPU, without any external opto or transformer isolation is possible. Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra precaution, a small film snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC power input pins. (Fig. 2) MAXIMUM RATINGS (Tj = 25°C) INVERTER PART (Including Brake Part) Symbol VCC Item Supply voltage VCC(surge) Supply voltage (surge) VP or VN VP(S) or VN(S) ±IC(±ICP) IC(ICP) IF (IFP) Condition Applied between P-N Ratings 450 Unit V 500 V 600 V 600 V ±50 (±100) A 15 (30) 15 (30) A Ratings Unit 20 V –0.5 ~ 7.5 V Applied between FO1 · FO2 · FO3-GND Sink current of FO1 · FO2 · FO3 –0.5 ~ 7 15 V mA Applied between CL-GND Sink current of CL –0.5 ~ 7 15 V mA ±1 mA Applied between P-N, Surge-value Applied between P-U, V, W, Br or U, V, W, Each output IGBT collector-emitter static voltage Br-N Each output IGBT collector-emitter Applied between P-U, V, W, Br or U, V, W, switching surge voltage Br-N Each output IGBT collector current TC = 25°C Brake IGBT collector current Brake diode anode current Note: “( )” means IC peak value A CONTROL PART Symbol Item VDH , VDB Supply voltage V CIN Input signal voltage V FO I FO Fault output supply voltage V CL I CL I CO Fault output current Current-limit warning (CL) output voltage CL output current Analogue current signal output current Condition Applied between VDH-GND, CBU+-CBU–, CBV+-CBV–, C BW+-CBW– Applied between UP · VP · WP · UN · VN · WN · Br-GND Sink current of CU · CV · CW Jan. 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> RY INA ELIM PS11017 on. ange. ificati h l spec ct to c a finaare subje t o n is its is m h li T e: tric Notice parame Som PR FLAT-BASE TYPE INSULATED TYPE TOTAL SYSTEM Symbol Ratings Unit (Note 2) –20 ~ +125 °C (Fig. 3) –40 ~ +125 –20 ~ +100 °C °C 2500 Vrms 0.98 ~ 1.47 N·m Condition Tj Item Junction temperature T stg TC Storage temperature Module case operating temperature Viso Isolation voltage — 60 Hz sinusoidal AC applied between all terminals and the base plate for 1 minute. Mounting screw: M4.0 Mounting torque Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. However, these power elements can endure instantaneous junction temperature as high as 150°C instantaneously . To make use of this additional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use. CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface) LABEL Tc (Fig. 3) THERMAL RESISTANCE Symbol Rth(j-c) Q Rth(j-c) F Rth(j-c)Q Rth(j-c) F Rth(c-f) Min. Ratings Typ. Max. Inverter IGBT (1/6) Inverter FWDi (1/6) — — — — 1.75 2.4 Brake IGBT Brake FWDi — — — — 2.9 4.5 Case to fin, thermal grease applied — — 0.031 Min. — — Ratings Typ. — — Max. 2.9 2.9 — — 3.5 V Condition Item Junction to case Thermal Resistance Contact Thermal Resistance Unit °C/W °C/W °C/W °C/W °C/W ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted) Symbol VCE(sat) VEC VCE(sat)Br VFBr ton tc(on) toff tc(off) trr Condition Item Collector-emitter saturation voltage FWDi forward voltage Brake IGBT Collector-emitter saturation voltage Brake diode forward voltage Switching times FWD reverse recovery time Short circuit endurance VDH = VDB = 15V, Input = ON, Tj = 25°C, Ic = 50A Tj = 25°C, Ic = –50A, Input = OFF VDH = 15V, Input = ON, Tj = 25°C, Ic = 15A Unit V V Tj = 25°C, IF = 15A, Input = OFF — — 2.9 1/2 Bridge inductive, Input = ON VCC = 300V, Ic = 50A, Tj = 125°C 0.40 — 0.8 0.40 2.0 1.0 V µs µs — — 1.5 0.6 2.4 1.3 µs µs — 0.15 — µs VDH = 15V, VDB = 15V Note : ton, toff include delay time of the internal control circuit (Output, Arm, and Load, VCC ≤ 400V, Input = ON (one-shot) Tj = 125°C start Short Circuit Modes) 13.5V ≤ VDH = VDB ≤ 16.5V Switching SOA Ic < IOL(CL) operation level, Input = ON, 13.5V ≤ VDH = VDB ≤ 16.5V IDH Circuit current VDH = 15V, VCIN = 5V Vth(on) Vth(off) Input on threshold voltage Input off threshold voltage — 0.8 2.5 — 1.4 3.0 150 2.0 4.0 Ri Input pull-up resister Integrated between input terminal-VDH — 150 — VCC ≤ 400V, Tj ≤ 125°C, • No destruction • FO output by protection operation • No destruction • No protecting operation • No FO output mA V V kΩ Jan. 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> RY INA ELIM PS11017 on. ange. ificati h l spec ct to c a finaare subje t o n is its is m h li T e: tric Notice parame Som PR FLAT-BASE TYPE INSULATED TYPE ELECTRICAL CHARACTERISTICS (Tj = 25°C, V DH = 15V, VDB = 15V unless otherwise noted) Item Symbol fPWM txx tdead tint VCO Condition PWM input frequency Allowable input on-pulse width Allowable input signal dead time for blocking arm shoot-through Relates to corresponding input (Except break part) Input inter-lock sensing V C+(200%) Analogue signal linearity with output current V C–(200%) Offset change area vs temperature |∆VCO | VC+ VC– TC ≤ 100°C, Tj ≤ 125°C (Note 3) VDH = 15V, TC = –20°C ~ +100°C Relates to corresponding inputs, (Except brake part), TC = –20°C ~ +100°C Analogue signal output voltage limit ∆VC(200%) Analogue signal over all linear variation Ic = 0A Ic = IOP (200%) Ic = –I OP(200%) VDH = 15V TC = –20°C ~ 100°C (Fig. 4) VDH = 15V, TC = –20°C ~ 100°C Ic > IOP (200%), VDH = 15V (Fig. 4) Analogue signal data hold accuracy |VCO-VC±(200%)| Correspond to max. 500µs data hold period (Fig. 5) only, Ic = IOP (200%) td(read) Analogue signal reading time After input signal trigger point ICL(H) ICL(L) ±IOL Signal output current of CL operation rCH SC OT OTr UVDH UVDHr OVDH OVDHr UVDB UVDBr tdV IFO(H) IFO(L) Idle Active CL warning operation level Short circuit over current trip level Trip level Over temperature protection Reset level Trip level (Fig. 8) Open collector output VD = 15V, TC = –20°C ~ 100°C Tj = 25°C (Note 4) (Fig. 7) (Note 5) VDH = 15V Reset level Trip level Supply circuit under & over voltage protection Reset level Trip level T C = –20 ~ +100°C, Tj ≤ 125°C Reset level Filter time Fault output current Idle Active Open collector output Min. — 1 Ratings Typ. — — Max. 15 500 2.5 — — µs — 65 2.27 1.17 100 2.57 1.47 ns 3.37 15 3.67 — — — 0.7 V 4.0 — — 1.1 — — V V –5 — 5 % 1.87 0.77 2.97 — Unit kHz µs V V V mV — 3 — µs — — 1 — 48.2 79.2 100 1 60.0 102 110 — 72.0 — 120 µA mA — 11.05 90 12.00 — 12.75 °C V 11.55 12.50 13.25 18.00 16.50 19.20 17.50 20.15 18.65 V V 10.0 10.5 — 11.0 11.5 10 12.0 12.5 — — — — 1 1 — A A °C V V V µs µA mA (Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only. (b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its F O1 pin of the ASIPM indicating a short circuit situation. RECOMMENDED CONDITIONS Symbol VCC Item Supply voltage Condition Applied across P-N terminals VDH , VDB Control Supply voltage Applied between V DH-GND, CBU+-CBU– , CBV+-CBV–, CBW+ -CBW– ∆VDH, ∆V DB Supply voltage ripple Input on voltage VCIN(on) VCIN(off) fPWM tdead Input off voltage PWM Input frequency Arm shoot-through blocking time Using application circuit Using application circuit Ratings 400 (max.) Unit V 15±1.5 V ±1 (max.) V/µs 0 ~ 0.3 4.8 ~ 5.0 V V 2 ~ 15 2.5 (min.) kHz µs Jan. 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> RY INA ELIM PS11017 on. ange. ificati h l spec ct to c a finaare subje t o n is its is m h li T e: tric Notice parame Som PR FLAT-BASE TYPE INSULATED TYPE Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING LINEARITY Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING “DATA HOLD” DEFINITION 5 VC VC– 4 min VDH=15V TC= –20~100˚C max 500µs VC–(200%) 3 0V VCH(5µs) VCH(505µs) VC(V) VC0 2 rCH= VCH(505µs)-VCH(5µs) VC+(200%) 1 Analogue output signal data hold range 0 –400 –300 –200 –100 0 VC+ VCH(5µs) Note ; Ringing happens around the point where the signal output voltage changes state from “analogue” to “data hold” due to test circuit arrangement and instrumentational trouble. Therefore, the rate of change is measured at a 5 µs delayed point. 100 200 300 400 Real load current peak value.(%)(Ic=Io✕ 2) (Fig. 4) Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART Input signal VCIN(p) of each phase upper arm 0V Input signal VCIN(n) of each phase lower arm 0V Gate signal Vo(p) of each phase upper arm (ASIPM internal) 0V Gate signal Vo(n) of each phase upper arm (ASIPM internal) 0V Error output FO1 0V Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in “LOW” level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F O” signal is outputted. After an “input interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION Input signal VCIN of each phase upper arm 0V Short circuit sensing signal VS 0V Gate signal Vo of each phase upper arm(ASIPM internal) Error output FO1 SC delay time 0V 0V Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”). Jan. 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> RY INA ELIM PS11017 on. ange. ificati h l spec ct to c a finaare subje t o n is its is m h li T e: tric Notice parame Som PR FLAT-BASE TYPE INSULATED TYPE Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART N-side IGBT Current N-side FWDi Current off VCIN on on V(hold) off IC 0 +ICL (VS) 0 –ICL t(hold) VC Ref 0 off VCL on Delay time td(read) Fig. 9 START-UP SEQUENCE Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph 5V ASIPM 5.1kΩ DC-Bus voltage Control voltage supply Boot-strap voltage VPN 0 PWM starts a) VDH 0 VDB 0 N-Side input signal VCIN(N) P-Side input signal VCIN(P) on Brake input signal VCIN(Br) on FO1 output signal FOI on R UP,VP,WP,UN,VN,WN,Br R CPU F01,F02,F03,CL 10kΩ b) CU,CV,CW 0.1nF 0.1nF GND(Logic) on a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20µs number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) FO1 resetting sequence: Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order. Jan. 2000