TI SN74LVCC3245APWR

SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
FEATURES
•
•
•
•
•
DB, DBQ, DW, NS, OR PW PACKAGE
(TOP VIEW)
Bidirectional Voltage Translator
2.3 V to 3.6 V on A Port and 3 V to 5.5 V on B
Port
Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCCB
NC
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track
VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track VCCA, which operates at 2.3
V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a
3.3-V system environment and vice versa.
The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
ORDERING INFORMATION
PACKAGE (1)
TA
SN74LVCC3245ADW
Reel of 2000
SN74LVCC3245ADWR
SOP – NS
Reel of 2000
SN74LVCC3245ANSR
LVCC3245A
SSOP – DB
Reel of 2000
SN74LVCC3245ADBR
LH245A
SN74LVCC3245ADBQR
LVCC3245A
SSOP (QSOP) – DBQ Reel of 2500
TSSOP – PW
(1)
TOP-SIDE MARKING
Tube of 25
SOIC – DW
–40°C to 85°C
ORDERABLE PART NUMBER
Tube of 60
SN74LVCC3245APW
Reel of 2000
SN74LVCC3245APWR
Reel of 250
SN74LVCC3245APWT
LVCC3245A
LH245A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH TRANSCEIVER)
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2005, Texas Instruments Incorporated
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
2
22
OE
A1
3
21
B1
To Seven Other Channels
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
VCCA
VCCB
Supply voltage range
VI
Input voltage range
–0.5
MAX
6 V
All A ports (2)
–0.5
VCCA + 0.5
All B ports (3)
–0.5
VCCB + 0.5
Except I/O
ports (2)
UNIT
–0.5
VCCA + 0.5
All A ports
–0.5
VCCA + 0.5
All B ports
–0.5
VCCB + 0.5
V
VO
Output voltage range (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCCA, VCCB, or GND
θJA
Package thermal impedance (4)
DB package
63
DBQ package
61
DW package
46
NS package
65
PW package
Tstg
(1)
(2)
(3)
(4)
2
Storage temperature range
V
°C/W
88
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 4.6 V maximum.
This value is limited to 6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
www.ti.com
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
Recommended Operating Conditions
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
(1)
VCCA
VCCB
MIN
NOM
MAX
UNIT
VCCA
Supply voltage
2.3
3.3
3.6
V
VCCB
Supply voltage
3
5
5.5
V
2.3 V
VIHA
VIHB
VILA
High-level input voltage
High-level input voltage
Low-level input voltage
VILB
Low-level input voltage
High-level input voltage (control pins)
(referenced to VCCA)
VIH
Low-level input voltage (control pins)
(referenced to VCCA)
VIL
3V
1.7
2.7 V
3V
2
3V
3.6 V
2
3.6 V
5.5 V
2
2.3 V
3V
2
2.7 V
3V
2
3V
3.6 V
2
3.6 V
5.5 V
3.85
2.3 V
3V
0.7
2.7 V
3V
0.8
3V
3.6 V
0.8
3.6 V
5.5 V
0.8
2.3 V
3V
0.8
2.7 V
3V
0.8
3V
3.6 V
0.8
3.6 V
5.5 V
2.3 V
3V
1.7
2.7 V
3V
2
3V
3.6 V
2
3.6 V
5.5 V
2
2.3 V
3V
0.7
2.7 V
3V
0.8
3V
3.6 V
0.8
3.6 V
5.5 V
0.8
V
V
V
V
1.65
V
V
VIA
Input voltage
0
VCCA
V
VIB
Input voltage
0
VCCB
V
VOA
Output voltage
0
VCCA
V
VOB
Output voltage
0
VCCB
V
IOHA
IOHB
IOLA
(1)
High-level output current
High-level output current
Low-level output current
2.3 V
3V
–8
2.7 V
3V
–12
3V
3V
–24
2.7 V
4.5 V
–24
2.3 V
3V
–12
2.7 V
3V
–12
3V
3V
–24
2.7 V
4.5 V
–24
2.3 V
3V
8
2.7 V
3V
12
3V
3V
24
2.7 V
4.5 V
24
mA
mA
mA
All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
Recommended Operating Conditions (continued)
IOLB
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
4
VCCA
VCCB
MIN
2.3 V
3V
12
2.7 V
3V
12
3V
3V
24
2.7 V
4.5 V
24
–40
NOM
MAX
UNIT
mA
10
ns/V
85
°C
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
MIN
TYP
3V
3V
2.9
3
2.3 V
3V
2
2.7 V
3V
2.2
2.5
3V
3V
2.4
2.8
3V
3V
2.2
2.6
2.7 V
4.5 V
2
2.3
3V
3V
2.9
3
2.3 V
3V
2.4
2.7 V
3V
2.4
2.8
3V
3V
2.2
2.6
2.7 V
4.5 V
3.2
4.2
3V
3V
IOL = 8 mA
2.3 V
3V
IOL = 12 mA
2.7 V
3V
0.1
0.5
3V
3V
0.2
0.5
0.2
0.5
IOH = –100 µA
IOH = –8 mA
VOHA
IOH = –12 mA
IOH = –24 mA
IOH = –100 µA
IOH = –12 mA
VOHB
IOH = –24 mA
IOL = 100 µA
VOLA
IOL = 24 mA
VOLB
MAX
V
V
0.1
0.6
2.7 V
4.5 V
IOL = 100 µA
3V
3V
0.1
IOL = 12 mA
2.3 V
3V
0.4
3V
3V
2.7 V
IOL = 24 mA
0.2
0.5
4.5 V
0.2
0.5
3.6 V
±0.1
±1
5.5 V
±0.1
±1
II
Control inputs
VI = VCCA or GND
IOZ (1)
A or B ports
VO = VCCA/B or GND,
VI = VIL or VIH
3.6 V
3.6 V
±0.5
±5
A port = VCCA or GND,
IO = 0
3.6 V
Open
5
50
B port = VCCB or GND,
IO = 0
3.6 V
3.6 V
5
50
5.5 V
5
50
3.6 V
5
50
5.5 V
8
80
ICCA
B to A
ICCB
3.6 V
A to B
A port = VCCA or GND,
A port
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
OE at GND and DIR at VCCA
3.6 V
3.6 V
0.35
0.5
OE
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
DIR at VCCA
3.6 V
3.6 V
0.35
0.5
DIR
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
OE at GND
3.6 V
3.6 V
0.35
0.5
∆ICCB (2)
B port
VI = VCCB – 2.1 V, Other inputs at VCCB or GND,
OE at GND and DIR at GND
3.6 V
5.5 V
1
1.5
Ci
Control inputs
VI = VCCA or GND
Open
Open
Cio
A or B ports
VO = VCCA/B or GND
3.3 V
5V
∆ICCA (2)
(1)
(2)
IO = 0
3.6 V
UNIT
V
V
µA
µA
µA
µA
mA
mA
4
pF
18.5
pF
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated VCC.
5
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4)
PARAMETER
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCA = 2.5 V
± 0.2 V,
VCCB = 3.3 V
± 0.3 V
VCCA = 2.7 V TO
3.6 V,
VCCB = 5 V
± 0.5 V
VCCA = 2.7 V TO
3.6 V,
VCCB = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
1
9.4
1
6
1
7.1
1
9.1
1
5.3
1
7.2
1
11.2
1
5.8
1
6.4
1
9.9
1
7
1
7.6
1
14.5
1
9.2
1
9.7
1
12.9
1
9.5
1
9.5
1
13
1
8.1
1
9.2
1
12.8
1
8.4
1
9.9
1
7.1
1
7
1
6.6
1
6.9
1
7.8
1
6.9
1
8.8
1
7.3
1
7.5
1
8.9
1
7
1
7.9
UNIT
ns
ns
ns
ns
ns
ns
Operating Characteristics
VCCA = 3.3 V, VCCB = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50,
f = 10 MHz
TYP
38
4.5
UNIT
pF
Power-Up Considerations (1)
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. To guard against such power-up problems, take these
precautions:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
(1)
6
Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR A PORT
VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH - 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR B PORT
VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH - 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR B PORT
VCCA = 3.6 V and vCCB = 5.5 V
2 × VCC
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
B-Port
Input
50% VCC
50% VCC
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
1.5 V
Input
1.5 V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
0V
tPHL
tPLH
B-Port
Output
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
2.7 V
Output
Control
1.5 V
1.5 V
0V
tPZL
tPLZ
VCC
50% VCC
VOL + 0.3 V
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
VOL
tPHZ
50% VCC
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
9
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT
VCCA AND VCCB = 3.6 V
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
tw
2.7 V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
1.5 V
Input
1.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
2.7 V
Output
Control
1.5 V
1.5 V
0V
tPZL
tPLZ
3.5 V
1.5 V
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LVCC3245ADBQRE4
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
74LVCC3245ADBQRG4
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LVCC3245ADBLE
OBSOLETE
SSOP
DB
24
SN74LVCC3245ADBQR
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LVCC3245ADBR
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245ADBRE4
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245ADWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245ADWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245ADWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245ANSR
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245ANSRE4
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245APW
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245APWE4
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245APWLE
OBSOLETE
TSSOP
PW
24
SN74LVCC3245APWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245APWRE4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245APWT
ACTIVE
TSSOP
PW
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCC3245APWTE4
ACTIVE
TSSOP
PW
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
TBD
Lead/Ball Finish
Call TI
Call TI
MSL Peak Temp (3)
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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