FSAM75SM60A SPMTM (Smart Power Module) General Description Features FSAM75SM60A is an advanced smart power module (SPM) that Fairchild has newly developed and designed to provide very compact and low cost, yet high performance ac motor drives mainly targeting medium speed low-power inverter-driven application like air conditioners. It combines optimized circuit protection and drive matched to low-loss IGBTs. Highly effective short-circuit current detection/ protection is realized through the use of advanced current sensing IGBT chips that allow continuous monitoring of the IGBTs current. System reliability is further enhanced by the built-in over-temperature and integrated under-voltage lock-out protection. The high speed built-in HVIC provides opto-coupler-less IGBT gate driving capability that further reduce the overall size of the inverter system design. In addition the incorporated HVIC facilitates the use of singlesupply drive topology enabling the FSAM75SM60A to be driven by only one drive supply voltage without negative bias. Inverter current sensing application can be achieved due to the devided nagative dc terminals. • UL Certified No. E209204 • 600V-75A 3-phase IGBT inverter bridge including control ICs for gate driving and protection • Divided negative dc-link terminals for inverter current sensing applications • Single-grounded power supply due to built-in HVIC • Typical switching frequency of 5kHz • Built-in thermistor for over-temperature monitoring • Isolation rating of 2500Vrms/min. • Very low leakage current due to using DBC (Direct Bonded Copper) substrate • Adjustable current protection level by varying series resistor value with sense-IGBTs Applications • AC 100V ~ 253V three-phase inverter drive for small power ac motor drives • Home appliances applications like air conditioners drive system External View Top View Bottom View 60mm 31mm Fig. 1. ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A May 4, 2006 FSAM75SM60A Integrated Power Functions • 600V-75A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3) Integrated Drive, Protection and System Control Functions • For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting Control circuit under-voltage (UV) protection Note) Available bootstrap circuit example is given in Figs. 13 and 14. • For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC) Control supply circuit under-voltage (UV) protection • Temperature Monitoring: System over-temperature monitoring using built-in thermistor Note) Available temperature monitoring circuit is given in Fig. 14. • Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side control supply circuit) • Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input Pin Configuration Top View (1)VCC(L) (2)COM(L) (3)IN(UL) (4)IN(VL) (5)IN(WL) (6)COM(L) (24)VTH (25)RTH (26)NU (27)NV (7)VFO (8)CFOD (9)CSC (28)NW (10)RSC (11)IN(UH) (29)U (12)VCC(UH) (13)VB(U) Case Temperature(TC) Detecting Point (30)V (14)VS(U) (15)INV(H) (16)COM(H) (17)VCC(VH) (31)W (18)VB(V) DBC Substrate (19)VS(V) (20)IN(WH) (32)P (21)VCC(WH) (22)VB(W) (23)VS(W) Fig. 2. ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A Pin Descriptions Pin Number 1 Pin Name VCC(L) Pin Description Low-side Common Bias Voltage for IC and IGBTs Driving 2 COM(L) 3 IN(UL) Signal Input Terminal for Low-side U Phase 4 IN(VL) Signal Input Terminal for Low-side V Phase 5 IN(WL) Signal Input Terminal for Low-side W Phase 6 COM(L) Low-side Common Supply Ground 7 VFO 8 CFOD Capacitor for Fault Output Duration Time Selection 9 CSC Capacitor (Low-pass Filter) for Short-Circuit Current Detection Input 10 RSC 11 IN(UH) 12 VCC(UH) 13 VB(U) High-side Bias Voltage for U Phase IGBT Driving 14 VS(U) High-side Bias Voltage Ground for U Phase IGBT Driving 15 IN(VH) Signal Input for High-side V Phase 16 COM(H) High-side Common Supply Ground 17 VCC(VH) High-side Bias Voltage for V Phase IC 18 VB(V) High-side Bias Voltage for V Phase IGBT Driving 19 VS(V) High-side Bias Voltage Ground for V Phase IGBT Driving 20 IN(WH) 21 VCC(WH) 22 VB(W) High-side Bias Voltage for W Phase IGBT Driving 23 VS(W) High-side Bias Voltage Ground for W Phase IGBT Driving 24 VTH Thermistor Bias Voltage 25 RTH Series Resistor for the Use of Thermistor (Temperature Detection) 26 NU Negative DC–Link Input Terminal for U Phase 27 NV Negative DC–Link Input Terminal for V Phase 28 NW 29 U Low-side Common Supply Ground Fault Output Resistor for Short-circuit Current Detection Signal Input for High-side U Phase High-side Bias Voltage for U Phase IC Signal Input for High-side W Phase High-side Bias Voltage for W Phase IC Negative DC–Link Input Terminal for W Phase Output for U Phase 30 V Output for V Phase 31 W Output for W Phase 32 P Positive DC–Link Input ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A Internal Equivalent Circuit and Input/Output Pins (22) VB(W) (21) VCC(WH) (20) IN(WH) (23) VS(W) (18) VB(V) (17) VCC(VH) (16) COM(H) (15) IN(VH) (19) VS(V) (13) VB(U) (12) VCC(UH) (11) IN(UH) (14) VS(U) P (32) VB VCC COM IN OUT W (31) VS VB VCC COM IN OUT VS V (30) VB VCC COM IN OUT U (29) VS (10) RSC (9) CSC (8) CFOD (7) VFO (6) COM(L) (5) IN(WL) (4) IN(VL) (3) IN(UL) (2) COM(L) (1) VCC(L) C(SC) OUT(WL) C(FOD) NW (28) VFO IN(WL) OUT(VL) IN(VL) NV (27) IN(UL) COM(L) OUT(UL) VCC NU (26) RTH (25) THERMISTOR VTH (24) Note 1. Inverter low-side is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving, current sensing and protection functions. 2. Inverter power side is composed of four inverter dc-link input pins and three inverter output pins. 3. Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT. Fig. 3. ©2006 Fairchild Semiconductor Corporation May 4, 2006 Unless Otherwise Specified) Inverter Part Item Symbol VDC Supply Voltage Supply Voltage (Surge) Condition Applied to DC - Link VPN(Surge) Collector-emitter Voltage Applied between P- N VCES Rating 450 Unit V 500 V 600 V Each IGBT Collector Current ± IC TC = 25°C 75 A Each IGBT Collector Current ± IC TC = 100°C 37 A Each IGBT Collector Current (Peak) ± ICP TC = 25°C , Under 1ms pulse width 110 A Collector Dissipation PC TC = 25°C per One Chip 189 W Operating Junction Temperature TJ (Note 1) -20 ~ 125 °C Note 1. It would be recommended that the average junction temperature should be limited to TJ ≤ 125°C (@TC ≤ 100°C) in order to guarantee safe operation. Control Part Item Control Supply Voltage Symbol Condition VCC Applied between VCC(UH), VCC(VH), VCC(WH) COM(H), VCC(L) - COM(L) Rating 20 Unit V 20 V V High-side Control Bias Voltage VBS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) VS(W) Input Signal Voltage VIN Applied between IN(UH), IN(VH), IN(WH) - COM(H) IN(UL), IN(VL), IN(WL) - COM(L) -0.3 ~ VCC+0.3 Fault Output Supply Voltage VFO Applied between VFO - COM(L) -0.3 ~ VCC+0.3 V Fault Output Current IFO Sink Current at VFO Pin 5 mA Current Sensing Input Voltage VSC Applied between CSC - COM(L) -0.3 ~ VCC+0.3 V Total System Item Self Protection Supply Voltage Limit (Short Circuit Protection Capability) Module Case Operation Temperature Symbol Condition VPN(PROT) Applied to DC - Link, VCC = VBS = 13.5 ~ 16.5V TJ = 125°C, Non-repetitive, less than 5µs TC Storage Temperature TSTG Isolation Voltage VISO ©2006 Fairchild Semiconductor Corporation Note Fig. 2 60Hz, Sinusoidal, AC 1 minute, Connection Pins to Heat-sink Plate Rating 400 Unit V -20 ~ 100 °C -20 ~ 125 °C 2500 Vrms May 4, 2006 FSAM75SM60A Absolute Maximum Ratings (TJ = 25°C, Thermal Resistance Item Junction to Case Thermal Resistance Contact Thermal Resistance Symbol Rth(j-c)Q Condition Inverter IGBT part (per 1/6 module) Min. Typ. - Rth(j-c)F Inverter FWDi part (per 1/6 module) - Rth(c-f) Ceramic Substrate (per 1 Module) Thermal Grease Applied (Note 3) - Max. 0.56 Unit °C/W - 0.98 °C/W - 0.06 °C/W Note 2. For the measurement point of case temperature(TC), please refer to Fig. 2. 3. The thickness of thermal grease should not be more than 100um. Package Marking and Ordering Information Device Marking Device Package Real Size Tape Width Quantity FSAM75SM60A FSAM75SM60A SPM32-DA - - 8 Electrical Characteristics Inverter Part (TJ = 25°C, Unless Otherwise Specified) Item Collector - emitter Saturation Voltage Symbol VCE(SAT) VCC = VBS = 15V VIN = 0V Condition IC = 50A, TJ = 25°C Typ. - Max. 2.4 - Unit V FWDi Forward Voltage VFM VIN = 5V - 2.1 V Switching Times tON VPN = 300V, VCC = VBS = 15V IC = 75A, TJ = 25°C VIN = 5V ↔ 0V, Inductive Load (High-Low Side) - 0.76 - µs - 0.44 - µs - 1.42 - µs - 0.46 - µs (Note 4) - 0.10 - µs VCE = VCES, TJ = 25°C - - 250 µA tC(ON) tOFF tC(OFF) trr Collector - emitter Leakage Current ICES IC = 50A, TJ = 25°C Min. - Note 4. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally. For the detailed information, please see Fig. 4. ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A Absolute Maximum Ratings 100% IC VCE VIN(ON) IC IC V IN t ON FSAM75SM60A t rr VCE V IN t OFF t C(ON) 90% IC 10% IC 10% VCE V IN(OFF) (a) Turn-on tC(OFF) 10% VCE 10% I C (b) Turn-off Fig. 4. Switching Time Definition ©2006 Fairchild Semiconductor Corporation May 4, 2006 (TJ = 25°C, Unless Otherwise Specified) Control Part Item Symbol Quiescent VCC Supply Cur- IQCCL VCC = 15V rent IN(UL, VL, WL) = 5V Condition VCC(L) - COM(L) Min. - Typ. Max. Unit 26 mA IQCCH VCC = 15V IN(UH, VH, WH) = 5V VCC(UH), VCC(VH), VCC(WH) COM(H) - - 130 uA Quiescent VBS Supply Current IQBS VBS = 15V IN(UH, VH, WH) = 5V VB(U) - VS(U), VB(V) -VS(V), VB(W) - VS(W) - - 420 uA Fault Output Voltage VFOH VSC = 0V, VFO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V VFOL VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 1.1 V Short-Circuit Trip Level Sensing Voltage of IGBT Current Supply Circuit UnderVoltage Protection Fault Output Pulse Width VCC = 15V (Note 5) 0.45 0.51 0.56 V RSC = 26 Ω, RSU = RSV = RSW = 0 Ω and IC = 100A (Fig. 6) 0.45 0.51 0.56 V UVCCD Detection Level 11.5 12 12.5 V UVCCR Reset Level 12 12.5 13 V UVBSD Detection Level 7.3 9.0 10.8 V UVBSR Reset Level 8.6 10.3 12 V CFOD = 33nF (Note 6) 1.4 1.8 2.0 ms VSC(ref) VSEN tFOD ON Threshold Voltage VIN(ON) OFF Threshold Voltage VIN(OFF) ON Threshold Voltage VIN(ON) OFF Threshold Voltage VIN(OFF) Resistance of Thermistor RTH High-Side Low-Side Applied between IN(UH), IN(VH), IN(WH) - COM(H) - - 0.8 V 3.0 - - V Applied between IN(UL), IN(VL), IN(WL) - COM(L) - - 0.8 V 3.0 - - V @ TTH = 25°C (Note Fig. 5) (Note 7) - 50 - kΩ @ TTH = 100°C (Note Fig. 5) (Note 7) - 3.0 - kΩ Note: 5. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be selected around 26 Ω in order to make the SC trip-level of about 100A at the shunt resistors (RSU,RSV,RSW) of 0Ω . For the detailed information about the relationship between the external sensing resistor (RSC) and the shunt resistors (RSU,RSV,RSW), please see Fig. 6. 6. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F] 7. TTH is the temperature of thermistor itself. To know case temperature (TC), please make the experiment considering your application. Recommended Operating Conditions Item Symbol Condition Values Min. - Typ. 300 Max. 400 Unit Supply Voltage VPN Applied between P - NU, NV, NW Control Supply Voltage VCC Applied between VCC(UH), VCC(VH), VCC(WH) COM(H), VCC(L) - COM(L) 13.5 15 16.5 V High-side Bias Voltage VBS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) 13.0 15 18.5 V Blanking Time for Preventing Arm-short tdead For Each Input Signal 3.5 - - us fPWM TC ≤ 100°C, TJ ≤ 125°C - 5 - kHz 3 - - us PWM Input Signal Minimum Input Pulse Width PWIN(OFF) 200 ≤ VPN ≤ 400V, 13.5 ≤ VCC ≤ 16.5V, 13.0 ≤ VBS ≤ 18.5V, 0 ≤ IC ≤ 110A, -20 ≤ TJ ≤ 125°C VIN = 5V ↔ 0V, Inductive Load (Note 8) V Input ON Threshold Voltage VIN(ON) Applied between IN(UH), IN(VH), IN(WH) COM(H), IN(UL), IN(VL), IN(WL) - COM(L) 0 ~ 0.65 V Input OFF Threshold Voltage VIN(OFF) Applied between IN(UH), IN(VH), IN(WH) COM(H), IN(UL), IN(VL), IN(WL) - COM(L) 4 ~ 5.5 V Note: 8. SPM might not make response if the PWIN(OFF) is less than the recommended minimum value. ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A Electrical Characteristics FSAM75SM60A R-T Curve 70k 60k Resistance[kΩ] 50k 40k 30k 20k 10k 0 20 30 40 50 60 70 80 90 100 110 120 Temperature TTH[℃] Fig. 5. R-T Curve of The Built-in Thermistor 50 40 Rsc[Ω ] 30 ① 20 10 ② 0 0.000 0.005 0.010 0.015 0.020 0.025 0.030 R su ,R sv ,R sw [Ω ] Fig. 6. RSC Variation by change of Shunt Resistors ( RSU, RSV, RSW) for Short-Circuit Protection ① @ Current Trip Level ≒ 75A, ② @ Current Trip Level ≒ 100A ©2006 Fairchild Semiconductor Corporation May 4, 2006 Item Mounting Torque Limits Condition Mounting Screw: M4 (Note 9 and 10) DBC Flatness Units Recommended 10Kg•cm Min. 8 Typ. 10 Max. 12 Kg•cm Recommended 0.98N•m 0.78 0.98 1.17 N•m 0 - +120 µm - 32 - g Note Fig.7 Weight (+) (+) (+) Fig. 7. Flatness Measurement Position of The DBC Substrate Note: 9. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction. 10.Avoid one side tightening stress. Fig.8 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to be damaged. 2 1 Fig. 8. Mounting Screws Torque Order (1 → 2) ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A Mechanical Characteristics and Ratings FSAM75SM60A Time Charts of SPMs Protective Function Input Signal Internal IGBT Gate-Emitter Voltage Control Supply Voltage P3 P5 UV detect P1 P2 UV reset P6 Output Current P4 Fault Output Signal P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : Fault signal generation P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 9. Under-Voltage Protection (Low-side) Input Signal Internal IGBT Gate-Emitter Voltage Control Supply Voltage VBS P3 P5 UV detect P1 P2 UV reset P6 Output Current Fault Output Signal P4 P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : No fault signal P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 10. Under-Voltage Protection (High-side) ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A P5 Input Signal P6 Internal IGBT Gate-Emitter Voltage SC Detection P1 P4 P7 Output Current P2 SC Reference Voltage (0.5V) Sensing Voltage RC Filter Delay Fault Output Signal P3 P8 P1 : Normal operation - IGBT ON and conducting currents P2 : Short-circuit current detection P3 : IGBT gate interrupt / Fault signal generation P4 : IGBT is slowly turned off P5 : IGBT OFF signal P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation P7 : IGBT OFF state P8 : Fault-output reset and normal operation start Fig. 11. Short-circuit Current Protection (Low-side Operation only) ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A 5V-Line SPM RPF = 4.7kΩ RPL = 2kΩ RPH= 4.7kΩ 100 Ω IN(UH) , IN(VH) , IN(WH) 100 Ω CPU IN(UL) , IN (VL) , IN(WL) 100 Ω VFO CPF = 1nF 1nF CPL = 0.47nF CPH= 1.2nF COM Note: 1) It would be recommended that by-pass capacitors for the gating input signals, IN(UL), IN(VL), IN(WL), IN(UH), IN(VH) and IN(WH) should be placed on the SPM pins and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible. 2) The logic input is compatible with standard CMOS or LSTTL outputs. 3) RPLCPL/RPHCPH/RPFCPF coupling at each SPM input is recommended in order to prevent input/output signals’ oscillation and it should be as close as possible to each of SPM pins. Fig. 12. Recommended CPU I/O Interface Circuit These Values depend on PWM Control Algorithm R E(H) 15V-Line One-Leg Diagram of FSAM75SM60A R BS P D BS 0.1uF 47uF Vcc VB IN HO COM VS Inverter Output Vcc 470uF 1uF IN OUT COM N Note: 1) It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics. 2) The bootstrap resistor (RBS) should be 3 times greater than RE(H). The recommended value of RE(H) is 5.6Ω, but it can be increased up to 20Ω for a slower dv/dt of high-side. 3) The ceramic capacitor placed between VCC-COM should be over 1µF and mounted as close to the pins of the SPM as possible. Fig. 13. Recommended Bootstrap Operation Circuit and Parameters ©2006 Fairchild Semiconductor Corporation May 4, 2006 RE(VH) RE(UH) 5V line RBS DBS (22) VB(W) (21) VCC(WH) RPH RS CBS Gating WH CBSC (20) IN(WH) (23) VS(W) CPH RBS DBS (18) VB(V) (17) VCC(VH) RPH RS (16) COM(H) CBS Gating VH CBSC (15) IN(VH) (19) VS(V) CPH C P U DBS RBS (13) VB(U) (12) VCC(UH) RPH RS CBS Gating UH CPH CBSC RF RS Gating WH Gating VH Gating UH (9) CSC (8) CFOD CFOD (7) VFO (6) COM(L) RS (5) IN(WL) RS (4) IN(VL) RS (3) IN(UL) (2) COM(L) CBPF P (32) VB VCC OUT COM IN W (31) VS VB VCC OUT COM IN VS CPL CPL CPL CPF (1) VCC(L) VB VCC CDCS OUT COM IN Vdc U (29) VS C(SC) OUT(WL) C(FOD) NW (28) RSW NV (27) RSV VFO IN(WL) OUT(VL) IN(VL) IN(UL) COM(L) OUT(UL) VCC NU (26) CSP15 M V (30) (10) RSC RCSC CSC Fault (11) IN(UH) (14) VS(U) RSC 5V line RPL RPL RPL RPF FSAM75SM60A RE(WH) 15V line CSPC15 RSU 5V line VTH (24) THERMISTOR RTH (25) RTH Temp. Monitoring CSPC05 CSP05 RFW W-Phase Current V-Phase Current U-Phase Current RFV RFU CFW CFV CFU Note: 1) RPLCPL/RPHCPH /RPFCPF coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each SPM input pin. 2) By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3) VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance. Please refer to Fig. 12. 4) CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended. 5) VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin8) and COM(L)(pin2). (Example : if CFOD = 33 nF, then tFO = 1.8 ms (typ.)) Please refer to the note 6 for calculation method. 6) Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ (at high side input) or 2kΩ (at low side input) resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0.22~2nF by-pass capacitor should be used across each power supply connection terminals. 7) To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible. 8) In the short-circuit protection circuit, please select the RFCSC time constant in the range 3~4 µs. 9) Each capacitor should be mounted as close to the pins of the SPM as possible. 10)To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency noninductive capacitor of around 0.1~0.22 µF between the P&N pins is recommended. 11)Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays. It is recommended that the distance be 5cm at least. Fig. 14. Application Circuit ©2006 Fairchild Semiconductor Corporation May 4, 2006 FSAM75SM60A Detailed Package Outline Drawings SPM32-DA 28x2.00 ±0.30=(56.0) (2.00) MAX1.05 MAX1.00 2.00 ±0.30 0.60 ±0.10 0.60 ±0.10 0.40 0.40 28.0 ±0.30 #23 36.05 ±0.50 Ø4.30 (34.80) 13.6 ±0.30 +0.10 0.70 -0.05 #32 5.5°) (2.5°~ 31.0 ±0.50 #1 #24 19.86±0.30 7.20 ±0.5 53.0 ±0.30 12.30 ±0.5 60.0 ±0.50 3x7.62 ±0.30=(22.86) 3x4.0 ±0.30=(12.0 ) 11.0 ±0.30 (3.70) 2.00 ±0.30 (3.50) MAX1.00 MAX8.20 (10.14) 0.80 0.80 0.40 1.30±0.10 1.30±0.10 0.60±0.10 MAX3.20 MAX2.50 MAX1.60 Dimmensions in Millimeters ©2006 Fairchild Semiconductor Corporation May 4, 2006 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS™ EnSigna™ FACT™ FACT Quiet Series™ FAST® FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER® SMART START™ Star* Power™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET® VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only. ©2006 Fairchild Semiconductor Corporation May 4, 2006