PCM1801 PCM 1801 49% FPO SBAS131A – MAY 2001 16-Bit, Stereo, Audio ANALOG-TO-DIGITAL CONVERTER FEATURES ● SYSTEM CLOCK: 256fS, 384fS, or 512fS ● DUAL 16-BIT MONOLITHIC ∆Σ ADC ● SINGLE +5V POWER SUPPLY ● SINGLE-ENDED VOLTAGE INPUT ● SMALL SO-14 PACKAGE ● 64X OVERSAMPLING DECIMATION FILTER: Passband Ripple: ±0.05dB Stopband Attenuation: –65dB DESCRIPTION ● ANALOG PERFORMANCE: THD+N: –88dB (typ) SNR: 93dB (typ) Dynamic Range: 93dB (typ) Internal High-Pass Filter ● PCM AUDIO INTERFACE: Left Justified, I2S ● SAMPLING RATE: 4kHz to 48kHz PCM1801 is a low-cost, single chip stereo Analog-to-Digital Converter (ADC) with single-ended analog voltage inputs. The PCM1801 uses a delta-sigma modulator with 64x oversampling, a digital decimation filter, and a serial interface which supports Slave mode operation and two data formats. The PCM1801 is suitable for a wide variety of costsensitive consumer applications where good performance is required. PCM1801 VINL (+) Single-Endedto-Differential Converter (–) 5th-Order ∆Σ Modulator BCK x1/64 Decimation and High-Pass Filter VREF1 Reference VREF2 VINR (–) Single-Endedto-Differential Converter (+) 5th-Order ∆Σ Modulator Serial Data Interface LRCK DOUT Format Control FMT BYPAS Clock/Timing Control Power Supply VCC AGND DGND SCKI VDD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER PCM1801U SO-14 235 –25°C to +85°C PCM1801U " " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA PCM1801U PCM1801U/2K Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1801U/2K” will get a single 2000-piece Tape and Reel. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage: +VDD, +VCC .............................................................. +6.5V Supply Voltage Differences ............................................................... ±0.1V GND Voltage Differences .................................................................. ±0.1V Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V) Analog Input Voltage ................................................ –0.3V to (VCC + 0.3V) Input Current (any pin except supplies) .......................................... ±10mA Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C (reflow, 10s) ..................................................... +235°C PIN CONFIGURATION This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN ASSIGNMENTS Top View SO PIN NAME I/O DESCRIPTION VINL IN Analog Input, Lch. 2 VINR IN Analog Input, Rch. 3 DGND — Digital Ground 4 VDD — Digital Power Supply 5 SCKI IN System Clock Input; 256fS, 384fS, or 512fS. Bit Clock Input 1 1 VREF1 14 VINL 2 VINR VREF2 13 6 BCK IN 3 DGND AGND 12 7 LRCK IN 8 DOUT OUT 9 BYPAS IN HPF Bypass Control(1) L: HPF Enabled 10 FMT IN Audio Data Format(1) L: MSB-First, Left-Justified 11 VCC — Analog Power Supply 12 AGND — Analog Ground 13 VREF2 — Reference 2 Decoupling Capacitor 14 VREF1 — Reference 1 Decoupling Capacitor PCM1801U 4 VDD 5 SCKI 6 BCK 7 LRCK VCC 11 Sampling Clock Input Audio Data Output H: HPF Disabled FMT 10 BYPAS 9 DOUT 8 H: MSB-First, I2S NOTE: (1) With 100kΩ typical pull-down resistor. 2 PCM1801 SBAS131A ELECTRICAL CHARACTERISTICS All specifications at +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and 16-bit data, SYSCLK = 384fS, unless otherwise noted. PCM1801U PARAMETER CONDITIONS MIN RESOLUTION DIGITAL INPUT/OUTPUT Input Logic Level: VIH(1) VIL(1) Input Logic Current: IIN(2) IIN(3) Output Logic Level: VOH(4) VOL(4) Sampling Frequency System Clock Frequency DC ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift DYNAMIC PERFORMANCE(5) THD+N at FS (–0.5dB) THD+N at –60dB Dynamic Range Signal-To-Noise Ratio Channel Separation ANALOG INPUT Input Range Center Voltage Input Impedance Anti-Aliasing Filter Frequency Response IOH = –1.6mA IOL = +3.2mA 256fS 384fS 512fS High-Pass Filter Bypass High-Pass Filter Bypass EIAJ, A-weighted EIAJ, A-weighted 0.8 V V ±1 +100 µA µA 0.5 48 12.2880 18.4320 24.5760 V V kHz MHz MHz MHz 4.5 4 1.024 1.536 2.024 90 90 88 FS (VIN = 0dB) 44.1 11.2896 16.9344 22.5792 ±1.0 ±2.0 ±20 ±2.0 ±20 ±2.5 ±5.0 % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C –88 –90 93 93 91 –80 dB dB dB dB dB 2.828 2.1 30 170 –3dB Vp-p V kΩ kHz 0.454fS 0.583fS 0.019fS Hz Hz dB dB sec mHz +5.5 +5.5 25 125 VDC VDC mA mW +85 +125 °C °C °C/W ±0.05 –65 17.4/fS –3dB +VCC +VCC +VCC +VDD = +VDD = +5V = +VDD = +5V +4.5 +4.5 UNITS Bits 2.0 POWER SUPPLY REQUIREMENTS Voltage Range TEMPERATURE RANGE Operation Storage Thermal Resistance, θJA MAX 16 DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time (Latency) High Pass Frequency Response Supply Current(6) Power Dissipation TYP +5.0 +5.0 18 90 –25 –55 100 NOTES: (1) Pins 5, 6, 7, 9, and 10 (SCKI, BCK, LRCK, BYPAS, FMT). (2) Pins 5, 6, 7 (SCKI, BCK, LRCK) Schmitt-Trigger input. (3) Pins 9, 10 (BYPAS, FMT) Schmitt-Trigger input with 100kΩ typical pull-down resistor). (4) Pin 8 (DOUT). (5) fIN = 1kHz, using Audio Precisions System II, r ms Mode with 20kHz LPF and 400Hz HPF enabled. (6) No load on DOUT (pin 8). PCM1801 SBAS131A 3 BLOCK DIAGRAM PCM1801 (+) Single-Endedto-Differential Converter VINL 5th-Order ∆Σ Modulator (–) BCK Reference VREF2 (–) Single-Endedto-Differential Converter VINR Serial Data Interface x1/64 Decimation and High-Pass Filter VREF1 5th-Order ∆Σ Modulator (+) LRCK DOUT Format Control FMT BYPAS Clock/Timing Control Power Supply VCC AGND DGND SCKI VDD ANALOG FRONT-END (Single-Channel) 1.0µF + 1 VINL 30kΩ 1kΩ 1kΩ 13 (+) (–) Delta-Sigma Modulator VREF2 + 4.7µF VREF 4.7µF + 14 4 VREF1 PCM1801 SBAS131A TYPICAL CHARACTERISTICS At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. ANALOG DYNAMIC PERFORMANCE 2.8 95 95 2.4 93 2.2 0 25 50 75 85 94 93 SNR 92 100 92 –25 0 25 50 75 85 Temperature (°C) Temperature (°C) TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE vs SUPPLY VOLTAGE 2.8 –60dB 0.004 2.6 –0.5dB 0.003 2.4 0.002 SNR (dB) 0.005 THD+N at –60dB (%) 3.0 4.75 5.0 5.25 96 96 95 95 Dynamic Range 94 94 SNR 93 2.2 4.5 93 92 5.5 92 4.5 4.75 5.0 5.25 5.5 Supply Voltage (V) Supply Voltage (V) TOTAL HARMONIC DISTORTION + NOISE vs SAMPLING RATE SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE vs SAMPLING RATE 0.005 3.0 96 96 2.8 95 95 –60dB 0.004 2.6 –0.5dB 0.003 2.4 SNR (dB) 0.006 100 Dynamic Range 94 94 93 93 SNR 0.002 2.2 32 44.1 Sampling Rate (kHz) PCM1801 SBAS131A 48 Dynamic Range (dB) 0.003 Dynamic Range 94 92 92 32 44.1 48 Sampling Rate (kHz) 5 Dynamic Range (dB) 2.6 –0.5dB SNR (dB) 0.004 0.006 THD+N at –0.5dB (%) 96 –60dB 0.002 –25 THD+N at –0.5dB (%) 96 THD+N at –60dB (%) 0.005 3.0 THD+N at –60dB (%) THD+N at –0.5dB (%) 0.006 Dynamic Range (dB) SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE vs TEMPERATURE TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. ANALOG DYNAMIC PERFORMANCE (cont.) SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 20 20 ICC + IDD ICC + IDD 16 12 Supply Current (mA) Supply Current (mA) 16 ICC 8 IDD 4 12 ICC 8 IDD 4 0 –25 0 25 50 75 0 4.25 100 4.5 Temperature (°C) 4.75 5.0 5.5 5.75 Supply Voltage (V) SUPPLY CURRENT vs SAMPLING RATE 20 ICC + IDD Supply Current (mA) 16 12 ICC 8 IDD 4 0 0 10 20 30 40 50 Sampling Rate (kHz) 6 PCM1801 SBAS131A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. OUTPUT SPECTRUM –60dBFS FFT 0 –20 –20 –40 –40 Amplitude (dB) Amplitude (dB) Full-Scale FFT 0 –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 20 0 5 10 15 Frequency (kHz) Frequency (kHz) TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 20 0.1 100 THD+N (%) THD+N (%) 10 1 0.1 0.01 0.001 0.01 0.001 –100 0.0001 –80 –60 –40 Amplitude (dBV) PCM1801 SBAS131A –20 0 20 100 1k 10k 20k Frequency (Hz) 7 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. DIGITAL FILTER OVERALL CHARACTERISTICS STOPBAND ATTENUATION CHARACTERISTICS 0 0 –20 Amplitude (dB) Amplitude (dB) –50 –100 –40 –60 –150 –80 –200 –100 0 8 16 24 32 0 0.25 Normalized Frequency (x fS Hz) 0.50 0.75 1.00 Normalized Frequency (x fS Hz) PASSBAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 –1 –2 –0.2 Amplitude (dB) Amplitude (dB) 0.0 –0.4 –0.6 –3 –4 –5 –6 –7 –8 –0.8 –9 –1.0 0 0.1 0.2 0.3 0.4 –10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 0.5 Normalized Frequency (x fS Hz) Normalized Frequency (x fS Hz) HIGH PASS FILTER RESPONSE HIGH PASS FILTER RESPONSE 0 0.2 –10 0.0 –30 Amplitude (dB) Amplitude (dB) –20 –40 –50 –60 –70 –80 –0.2 –0.4 –0.6 –0.8 –90 –100 –1.0 0 0.05 0.1 0.15 0.2 0.25 0.3 Normalized Frequency (x fS /1000Hz) 8 -0.35 0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (x fS /1000Hz) PCM1801 SBAS131A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. ANTI-ALIASING ANTI-ALIASING FILTER PASSBAND CHARACTERISTICS 0 0 –10 –0.2 Amplitude (dB) Amplitude (dB) ANTI-ALIASING FILTER STOPBAND CHARACTERISTICS –20 –30 –0.4 –0.6 –0.8 –40 –1 –50 1 PCM1801 SBAS131A 10 100 1k 10k Frequency (Hz) 100k 1M 10M 1 10 1K 100 Frequency (Hz) 10K 100K 9 THEORY OF OPERATION The 64fS, 1-bit stream from the modulator is converted to 1fS, 16-bit digital data by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. The DC components are removed by a digital highpass filter, and the filtered output is converted to timemultiplexed serial signals through a serial interface which provides flexible serial formats. PCM1801 consists of a bandgap reference, two channels of a single-to-differential converter, a fully differential 5thorder delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The Block Diagram illustrates the total architecture of PCM1801, the Analog Front-End diagram illustrates the architecture of the single-to-differential converter, and the anti-aliasing filter is illustrated in the Block Diagram. Figure 1 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. An internal high precision reference with two external capacitors provides all reference voltages which are required by the converter, and defines the full-scale voltage range of both channels. The internal single-ended to differential voltage converter saves the design, space and extra parts needed for external circuitry required by many delta-sigma converters. The internal full differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at 64x oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a 1-bit DAC (Digital-to-Analog Converter). The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. Analog In X(z) + – SYSTEM CLOCK The system clock for PCM1801 must be either 256fS, 384fS, or 512fS, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 5). PCM1801 also has a system clock detection circuit which automatically senses if the system clock is operating at 256fS, 384fS, or 512fS. When 384fS and 512fS system clock are used, the PCM1801 automatically divides these clocks down to 256fS internally. This 256fS clock is used to operate the digital filter and the modulator. Table I lists the relationship of typical sampling frequencies and system clock frequencies. Figure 2 illustrates the system clock timing. 256fS 384fS 512fS 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9340 18.4320 16.3840 22.5792 24.5760 TABLE I. System Clock Frequencies. – 1st SW-CAP Integrator + SYSTEM CLOCK FREQUENCY (MHz) SAMPLING RATE FREQUENCY (kHz) – 2nd SW-CAP Integrator 3rd SW-CAP Integrator + 4th SW-CAP Integrator 5th SW-CAP Integrator Qn(z) + + + + + + Digital Out Y(z) + + H(z) Comparator 1-Bit DAC Y(z) = STF(z) • X(z) + NTF(z) • Qn(z) Signal Transfer Function Noise Transfer Function STF(z) = H(z) / [1 + H(z)] NTF(z) = 1/ [1 + H(z)] FIGURE 1. Simplified Diagram of the PCM1801 5th-Order Delta-Sigma Modulator. tCLKIH tCLKIL 2.0V SCKI 0.8V System Clock Pulse Width High tCLKIH 12ns (min) System Clock Pulse Width Low tCLKIL 12ns (min) FIGURE 2. System Clock Timing. 10 PCM1801 SBAS131A SERIAL AUDIO DATA INTERFACE RESET PCM1801 has an internal power-on reset circuit, which initializes (resets) when the supply voltage (VCC /VDD) exceeds 4.0V (typ). The PCM1801 stays in the reset state and the digital output is forced to zero. The digital output is valid after reset state release and 18436fS periods. During reset, the logic circuits and the digital filter stop operating. Figure 3 illustrates the internal power-on reset timing. The PCM1801 interfaces the audio system through BCK (pin 6), LRCK (pin 7), and DOUT (pin 8). DATA FORMAT PCM1801 supports two audio data formats in Slave Mode, and are selected by the FMT control input (pin 10) as shown in Table II. FMT DATA FORMAT 0 (L) 16-Bit, Left-Justified 1 (H) 16-Bit, I2S TABLE II. Data Format. 4.4V VCC/VDD 4.0V 3.6V Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock FIGURE 3. Internal Power-On Reset Timing. FMT = L 16-Bit, MSB-First, Left-Justified LRCK L–ch R–ch BCK DOUT 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB 1 LSB FMT = H 16-Bit, MSB-First, I2S L-ch LRCK R-ch BCK DOUT 1 2 3 MSB 14 15 16 LSB 1 2 MSB 3 14 15 16 LSB FIGURE 4. Audio Data Format. PCM1801 SBAS131A 11 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM PCM1801 operates with LRCK synchronized to the system clock (SCKI). PCM1801 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than 6 bit clocks (BCK) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and the digital output is forced to BPZ until resynchronization between LRCK and SCKI is completed. In case of changes less than 5 bit clocks (BCK), resynchronization does not occur and above digital output control and discontinuity does not occur. During undefined data, it may generate some noise in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal makes a discontinuity of data on the digital output, and may generate some noise in the audio signal. BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD PINS The digital and analog power supply lines to the PCM1801 should be bypassed to the corresponding ground pins with both 0.1µF and 10µF capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. Although PCM1801 has two power lines to maximize the potential of dynamic performance, using one common power supply is recommended to avoid unexpected power supply problems, such as latch-up due to power supply sequencing. AGND, DGND PINS To maximize the dynamic performance of the PCM1801, the analog and digital grounds are not internally connected. These points should have very low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the PCM1801 package to reduce potential noise problems. VIN PINS A 1.0µF tantalum capacitor is recommended as an ACcoupling capacitor which establishes a 5.3Hz cut-off frequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding a series resistor to the VIN pins. VREF INPUTS A 4.7µF tantalum capacitor is recommended between the VREF1, VREF2, and AGND references to ensure low source impedance. These capacitors should be located as close as possible to the VREF1 or VREF2 pins to reduce dynamic errors on the ADC’s references. SYSTEM CLOCK The quality of the system clock can influence dynamic performance in the PCM1801. The duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long-term reliability if the maximum power dissipation limit is exceeded. tLRCP 1.4V LRCK tBCKH tBCKL tLRHD tLRSU BCK 1.4V tBCKP tLRDO tCKDO DOUT DESCRIPTION BCK Period BCK Pulse Width HIGH BCK Pulse Width LOW LRCK Set Up Time to BCK Rising Edge LRCK Hold Time to BCK Rising Edge LRCK Period Delay Time BCK Falling Edge to DOUT Valid Delay Time LRCK Edge to DOUT Valid Rising Time of All Signals Falling Time of All Signals 0.5VDD SYMBOL MIN tBCKP tBCKH tBCKL tLRSU tLRHD tLRCP tCKDO tLRDO tRISE tFALL 300 120 120 80 40 20 –20 –20 TYP MAX UNITS 40 40 20 20 ns ns ns ns ns µs ns ns ns ns NOTE: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from 10% to 90% of I/O signals’ swing. Load capacitance of DOUT signal is 20pF. FIGURE 5. Audio Data Interface Timing. 12 PCM1801 SBAS131A Lch IN Rch IN C1(1) + C2(1) + 1 VINL VREF1 14 2 VINR VREF2 13 3 DGND AGND 12 C3(2) Audio Data Processor 4 VDD System Clock 5 Data Clock Latch Enable + C6(3) + C5(3) 0V C4(2) VCC 11 SCKI FMT 10 Format 6 BCK BYPAS 9 Bypass 7 LRCK DOUT 8 +5V Pin Program or Control Data Out NOTES: (1) C1 and C2: A 1µF capacitor gives 5.3Hz (τ = 1µF * 30kΩ) cut-off frequency for input HPF in normal operation and requires power-on setting time of 6ms at power up. (2) C3 and C4: Bypass capacitor 0.1µF ceramic and 30µF tantalum or aluminum electrolytic, depending on layout and power supply. (3) C5 and C6: 4.7µF tantalum or aluminum electrolytic capacitor. FIGURE 6. Typical Circuit Connection. PCM1801 SBAS131A 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2001, Texas Instruments Incorporated