1 EVALUATION KIT AVAILABLE TC530 TC534 5V PRECISION DATA ACQUISITION SUBSYSTEMS 2 FEATURES GENERAL DESCRIPTION ■ ■ ■ The TC530/534 are serial analog data acquisition subsystems ideal for high precision measurements (up to 17 bits plus sign). The TC530 consists of a dual slope integrating A/D converter, negative power supply generator and 3 wire serial interface port. The TC534 is identical to the TC530, but adds a four channel differential input multiplexer. Key A/D converter operating parameters (Auto Zero and Integration time) are programmable, allowing the user to trade-off conversion time for resolution. Data conversion is initiated when the RESET input is brought low. After conversion, data is loaded into the output shift register and EOC is asserted indicating new data is available. The converted data (plus Overrange and polarity bits) is held in the output shift register until read by the processor, or until the next conversion is completed allowing the user to access data at any time. The TC530/534 timebase can be derived from an external crystal of 2MHz (max), or from an external frequency source. The TC530/534 requires a single 5V power supply and features a – 5V, 10mA output which can be used to supply negative bias to other components in the system. ■ ■ ■ ■ ■ ■ ■ Precision (up to 17 Bits) A/D Converter 3 Wire Serial Port Flexible: User Can Trade-Off Conversion Speed Against Resolution Single Supply Operation –5V Output Pin 4 Input, Differential Analog MUX (TC534) Automatic Input Polarity and Overrange Detection Low Operating Current ............................ 5mA Max Wide Analog Input Range ...................... ±4.2V Max Cost Effective ORDERING INFORMATION Part No. Package Temp. Range TC530COI TC530CPJ TC534CKW TC534CPL TC530EV 28-Pin SOIC 0°C to +70°C 28-Pin Plastic DIP (300 Mil.) 0°C to +70°C 44-Pin PQFP 0°C to +70°C 40-Pin Plastic DIP 0°C to +70°C Evaluation Kit for TC530/534 3 4 5 FUNCTIONAL BLOCK DIAGRAM CINT +5V RINT VDD + V (TC530 Only) IN V– IN BUF CAZ CH1 + CH1 – TC534 (Only) CAZ INT IN + IN – CH2 + CH2 – DIF. MUX CH3 + CH3 – (TC534 Only) TC530 TC534 + – CREF CREF TC05 + VREF – VREF CMPTR A ACOM 0.01µF B EOC Oscillator (÷ 4) VSS CAP – Optional Power-On Reset Cap RESET VDD CAP+ 6 VDD Dual Slope A/D Converter DC-TO-DC CONVERTER OSC 100k .01µF State Machine CH4 + CH4 – A0 A1 10k VDD CREF OSCIN 7 R/W Serial Port DIN DOUT DCLK OSCOUT Negative Supply Output 8 TC530/534-3 11/14/96 TELCOM SEMICONDUCTOR, INC. 3-47 5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534 ABSOLUTE MAXIMUM RATINGS* Supply Voltage ........................................................... +6V + – Analog Input Voltage (VIN or VIN ) ....................... VDD to VSS Logic Input Voltage ................. (VDD + 0.3V) to (GND – 0.3V) Ambient Operating Temperature Range Plastic DIP Package .............................................. (C) 0°C to +70°C SOIC Package (C) .............................. 0°C to +70°C PQFP Package (C) .............................. 0°C to +70°C Storage Temperature Range .................... – 65°C to +150°C Lead Temperature (Soldering, 10 sec) ..................... +300°C *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Symbol Parameter VDD VCCD PD Analog Power Supply Voltage Digital Power Supply Voltage TC530/534 Total Power Dissipation Supply Current (VS + PIN) Supply Current (VCCD PIN) IS ICCD TA = +25°C TA = 0°C to +70°C Test Conditions Min Typ Max Min Typ Max Unit VDD = VCCD = 5V 4.5 4.5 — 5.0 5.0 — 5.5 5.5 25 4.5 4.5 — — — — 5.5 5.5 — V V mW fOSC = 1MHz — — 1.8 — 2.5 1.5 — — — — 3.0 1.7 mA mA ELECTRICAL CHARACTERISTICS: VDD = VCCD, CAZ = CREF = 0.47µF, unless otherwise specified. TA = +25°C Symbol Parameter Test Conditions Resolution Zero-Scale Error with Auto Zero Phase End Point Linearity Max Deviation from Best Straight Line Fit Zero-Scale Temperature Coefficient Roll-Over Error Full-Scale Temperature Coefficient Input Current Common-Mode Voltage Range Integrator Output Swing Analog Input Signal Range Voltage Reference Range Zero Crossing Comparator TA = 0°C to +70°C Min Typ Max Min Typ Max Unit Note 1 — — — — ±17 0.5 — — — 0.005 ±17 0.012 Bits % F.S. Note 1 and 2 Notes 1 and 2 — — 0.015 0.008 0.030 0.015 — — 0.015 — 0.045 % F.S. — % F.S. — — — — 1 2 µV/°C — — .012 — — — — — .03 10 — — % F.S. ppm/°C — VSS + 1.5 6 — — — — — pA V VSS + 0.9 VSS + 1.5 VSS + 1 — — — — 2.0 Analog R ZSE ENL NL ZSTC SYE FSTC IIN VCMR VINT VIN VREF tD 3-48 Note 3 Ext. VREF TC = 0ppm/°C VIN = 0V VDD – 1.5 VSS + 1.5 — VDD – 1.5 VDD – 0.9 VSS + 0.9 — VDD – 1.5 VSS + 1.5 — VDD – 1 VDD + 1 — VDD – 0.9 VDD – 1.5 VDD – 1 — — 3.0 — V V V µsec TELCOM SEMICONDUCTOR, INC. 5V PRECISION DATA ACQUISITION SUBSYSTEMS 1 TC530 TC534 ELECTRICAL CHARACTERISTICS: Serial Port Interface: VCCD = +5V, unless otherwise specified. TA = +25°C Symbol Parameter VIH VIL IIN VOL Input Logic HIGH Level Input Logic LOW Level Input Current (DI, DO, DCLK) Logic LOW Output Voltage (EOC) 2 TA = 0°C to +70°C Test Conditions Min Typ Max Min Typ Max Unit IOUT = 250µA 2.5 — — — — — — 0.2 — 0.8 10 0.3 2.5 — — — — — — — — 0.8 — 0.35 V V µA V 3 ELECTRICAL CHARACTERISTICS: Serial Port Interface: VCCD = +5V, unless otherwise specified. TA = +25°C Symbol Parameter Test Conditions tR, tF Rise and Fall Times (EOC, DI, DO) Crystal Frequency External Frequency on OSCIN Read Setup Time Read Delay Time DCLK to DOUT Delay DCLK LOW Pulse Width DCLK HIGH Pulse Width Data Ready Delay CL = 10pF FXTL FEXT tRS tRD tDRS tPWL tPWH tDR TA = 0°C to +70°C Min Typ Max Min Typ Max Unit — — 250 — 250 — nsec — — 1 250 450 150 150 200 — — — — — — — — 2.0 4.0 — — — — — — — — — — — — — — — — 1 250 450 150 150 200 2.0 4.0 — — — — — — MHz MHz µsec nsec nsec nsec nsec nsec 5 6 4 ELECTRICAL CHARACTERISTICS: DC/DC Converter Section: VDD = +5V, unless otherwise specified. TA = +25°C Symbol Parameter Test Conditions ROUT fCLK IOUT Output Resistance Oscillator Frequency VSS Output Current IOUT = 10mA COSC = 0 TA = 0°C To +70°C Min Typ Max Min Typ Max Unit — — — 65 100 — 85 — 10 — — — — — — 100 — 10 Ω kHz mA ELECTRICAL CHARACTERISTICS: Multiplexer: VDD = +5V (Note 4), unless otherwise specified. TA = +25°C Symbol Parameter VINMAX RDSON Maximum Input Voltage Drain/Source ON Resistance Notes: 1. 2. 3. 4. Test Conditions 7 TA = 0°C to +70°C Min Typ Max Min Typ Max Unit – 2.5 — — 6 2.5 10 –2.5 — — — 2.5 — V kΩ Integrate time ≥ 66msec, Auto Zero time ≥ 66msec, VINT (pk) = 4V. End point linearity at ±¹⁄₄, ±¹⁄₂, ±³⁄₄ F.S. after full scale adjustment. Roll-over error is related to capacitor used for CINT (See "Recommended Suppliers for CINT", Table 2). TC534 Only. TELCOM SEMICONDUCTOR, INC. 8 3-49 5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534 PIN CONFIGURATIONS VSS 28 CAP – 1 1 28 CAP – CINT 2 27 AGND 2 27 AGND CAZ 3 26 CAP + CAZ 3 26 CAP + BUF 4 25 VDD BUF 4 25 VDD ACOM – CREF 5 24 NC ACOM – CREF 5 24 N/C 23 OSC 22 VCCD + CREF – V REF + V REF 6 TC530CPJ 23 OSC 6 + TC530COI 10 19 R/W – VIN 10 19 R/W 11 18 DIN DGND 12 18 DIN 17 DCLK + VIN DGND 12 17 DCLK N/C 13 16 DOUT N/C 13 16 DOUT 14 15 OSCIN 1 40 CAP – CINT 2 39 AGND CAZ 3 38 CAP+ BUF 4 37 VDD ACOM – CREF 5 CAZ VSS BUF OSCOUT 15 OSCIN OSCOUT 14 N/C 11 44 43 42 41 40 39 38 37 36 35 N/C EOC VDD 20 EOC 20 CAP + 9 9 + AGND RESET V REF 8 CAP – 21 N/C 21 RESET 8 VSS 7 – V REF 22 VCCD 7 CINT CREF – VIN + VIN 34 N/C 1 33 N/C ACOM – CREF 2 32 OSC 36 N/C 3 31 N/C 6 35 N/C CREF 4 30 VCCD CREF 7 34 OSC 5 29 – V REF N/C 8 33 N/C – V REF + V REF 28 RESET V REF 9 32 VCCD 27 N/C CH4– 10 31 N/C 26 N/C CH3– 11 30 RESET 9 25 N/C CH2– 12 29 N/C EOC CH1– 13 28 10 24 11 23 R/W CH4+ 14 27 EOC CH3+ CH2+ 15 26 R/W 16 25 DIN CH1+ 17 24 DCLK DGND 18 23 DOUT A1 19 22 OSCIN A0 20 21 OSCOUT 12 13 14 14 15 16 17 18 19 20 21 22 DIN CH4+ DCLK CH1– DOUT CH2– OSCIN 8 OSCOUT CH3– A0 7 A1 N/C CH4– TC534CKW DGND TC534CPL 6 CH1+ + + CH3+ CH2+ + 3-50 VSS CINT TELCOM SEMICONDUCTOR, INC. 5V PRECISION DATA ACQUISITION SUBSYSTEMS 1 TC530 TC534 PIN DESCRIPTION Pin No. (TC530 28-Pin PDIP, 300 Mil.) Pin No. (TC530 28-Pin SOIC) 2 Pin No (TC534 40-Pin PDIP) Pin No. (TC534 44-Pin PQFP) Symbol 1 1 1 40 VSS 2 2 2 41 CINT 3 4 3 4 3 4 42 43 CAZ BUF 5 5 5 2 ACOM 6 7 8 9 Not Used 6 7 8 9 Not Used 6 7 8 9 10 3 4 5 6 7 – CREF + CREF – VREF + VREF CH4– Not Used Not Used 11 8 CH3– Not Used Not Used 12 9 CH2– Not Used Not Used 13 10 CH1– Not Used Not Used 14 11 CH4+ Not Used Not Used 15 12 CH3+ Not Used Not Used 16 13 CH2+ Not Used Not Used 17 14 CH1+ 10 11 12 Not Used Not Used 14 10 11 12 Not Used Not Used 14 Not Used Not Used 18 19 20 21 Not Used Not Used 15 16 17 18 – VIN + VIN DGND A1 A0 OSCOUT Description Analog Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to provide negative bias to other devices in the system. Analog Output. Integrator capacitor connection and integrator output. Analog Input. Auto Zero capacitor connection. Analog Output. Integrator capacitor connection and voltage buffer output. Analog Input. This pin is ground for all of the analog switches in the A/D converter. It is grounded for most applications. – ACOM and the input common pin (VIN or Chx–) should be within the common mode range, CMR. Analog Input. Reference cap negative connection. Analog Input. Reference cap positive connection. Analog Input. External voltage reference negative connection. Analog Input. External voltage reference positive connection. Analog Input. Multiplexer channel 4 negative differential analog input. Analog Input. Multiplexer channel 3 negative differential analog input. Analog Input. Multiplexer channel 2 negative differential analog input. Analog Input. Multiplexer channel 1 negative differential analog input. Analog Input. Multiplexer channel 4 positive differential analog input. Analog Input. Multiplexer channel 3 positive differential analog input. Analog Input. Multiplexer channel 2 positive differential analog input. Analog Input. Multiplexer channel 1 positive differential analog input. Analog Input. Negative differential analog voltage input. Analog Input. Positive differential analog voltage input. Analog Input. Ground connection for serial port circuit. Logic Level Input. Multiplexer address MSB. Logic Level Input. Multiplexer address LSB. Analog Input. Timebase for state machine. This pin connects to one side of an AT-cut crystal having an effective series resistance of 100Ω (typ) and a parallel capacitance of 20pF If an external frequency source is used to clock the TC530/534, this pin must be left floating. 3 4 5 6 7 8 TELCOM SEMICONDUCTOR, INC. 3-51 5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534 PIN DESCRIPTION (Cont.) Pin No. Pin No. (TC530 (TC530 28-Pin 28-Pin PDIP, 300 Mil.) SOIC) Pin No (TC534 40-Pin PDIP) Pin No. (TC534 44-Pin PQFP) Symbol 15 15 22 19 OSCIN 16 16 23 20 DOUT 17 17 24 21 DCLK 18 18 25 22 DIN 19 19 26 23 R/W 20 20 27 24 EOC 21 21 30 28 RESET Description Analog Input. This pin connects to the other side of the crystal described in OSCOUT above. The TC530/534 may also be clocked from an external frequency source connected to this pin. The external frequency source must be a pulse wave form with a minimum 30% duty cycle and rise and fall times 15nsec (Max). If an external frequency source is used, OSCOUT must be left floating. A maximum operating frequency of 2MHz (crystal) or 4MHz (external clock source) is permitted. Logic Level Output. Serial port data output pin. This pin is enabled only when R/W is high. Logic Input, Positive and Negative Edge Triggered. Serial port clock. When R/W is high, serial data is clocked out of the TC530/534A (on DOUT) at each HIGH-to-LOW transition of DCLK. A/D initialization data (LOAD VALUE) is clocked into the TC530/534 (on DIN) at each LOW-to-HIGH transition of DCLK. A maximum serial port DCLK frequency of 3MHz is permitted. Logic Level Input. Serial port input pin. The A/D converter integration time (TINT) and Auto Zero time (TAZ) values are determined by the LOAD VALUE byte clocked into this pin. This initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. The LOAD VALUE is clocked into DIN MSB first. Logic Level Input. This pin must be brought low to perform a write to the serial port (e.g. initialize the A/D converter). The DOUT pin of the serial port is enabled only when this pin is high. Open Drain Output. End-of-Conversion (EOC) is asserted any time the TC530/534 is in the AZ phase of conversion. This occurs when either the TC530/534 initiates a normal AZ phase, or when RESET is pulled high. EOC is returned high when the TC530/534 exits AZ. Since EOC is driven low immediately following completion of a conversion cycle, it can be used as a DATA READY processor interrupt. Logic Level Input. It is necessary to force the TC530/534 into the Auto Zero phase when power is initially applied. This is accomplished by momentarily taking RESET high. Using an I/O port line from the microprocessor, or by applying an external system reset signal, or by connecting a 0.01µF capacitor from the RESET input to VSS. Conversions are performed continuously as long as RESET is low and conversion is halted when RESET is high. RESET may therefore be used in a complex system to momentarily suspend conversion (for example while the address lines of an input multiplexer are changing state). In this case, RESET should be pulled high only when the EOC is LOW to avoid excessively long integrator discharge times which could result in erroneous conversion (see Applications Section). 3-52 TELCOM SEMICONDUCTOR, INC. 5V PRECISION DATA ACQUISITION SUBSYSTEMS 1 TC530 TC534 PIN DESCRIPTION (Cont.) Pin No. (TC530 28-Pin PDIP, 300 Mil.) 2 Pin No. (TC530 28-Pin SOIC) Pin No (TC534 40-Pin PDIP) Pin No. (TC534 44-Pin PQFP) Symbol 22 22 32 30 VCCD 23 23 34 32 OSC 25 25 37 35 VDD 26 26 38 36 CAP+ 27 28 27 28 39 40 37 38 AGND CAP– 13, 24 13, 24 28, 29, 31, 1, 25, 26, 27 33, 35, 36 29, 31, 33, 34, 39, 44, Description Analog Input. Power supply connection for digital logic and serial port. Proper power-up sequencing is critical, see the Applications section. Input. The negative power supply converter normally runs at a frequency of 100kHz. This frequency can be slowed down to reduce quiescent current by connecting an external capacitor between this pin and VS+ . (See Typical Characteristics). Analog Input. Power supply connection for the A/D analog section and DC-DC converter. Proper power-up sequencing is critical, see the Applications section. Analog Input. Storage capacitor positive connection for the DC/DC converter. Analog Input. Ground connection for DC/DC converter. Analog Input. Storage capacitor negative connection for the DC/DC converter. No connect. Do not connect any signal to these pins. NC WRITE TIMING READ TIMING tRD R/W 5 R/W tLS EOC tLDL DIN DIN tDLS DOUT tDRS tPWL 4 WRITE DEFAULT TIMING tRS R/W 3 tLDS tPWL DCLK DCLK 6 READ FORMAT R/W EOC DOUT EOC OVR SGN MSB LSB DCLK 7 WRITE FORMAT R/W DOUT MSB LSB DCLK 8 For Polled vs Interrupt Operation and Write Value Modified Cycle Use TC520A Data Sheet Figure 1 & 2. Figure 1. Serial Port Timing TELCOM SEMICONDUCTOR, INC. 3-53 5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534 Conversion Phase AZ Data to Serial Port Transmit Register INT DINT IZ Updated Data Ready AZ Updated Data Ready tDR EOC Figure 2. A/D Converter Timing The TC530/534 dual slope converter operates by integrating the input signal for a fixed time period, then applying an opposite polarity reference voltage while timing the period (counting clocks pulses) for the integrator output to cross 0V (deintegrating). The resulting count is read as conversion data. A simple mathematical expression that describes dual slope conversion is: (1) Integrate Voltage = Deintegrate Voltage ∫ (2) 1/RINTCINT ∫ tINT VIN(t)dt = 1/RINTCINT 0 tDINT VREF 0 from which: (3) (VIN) [ ] (tINT) (RINT)(CINT) = (VREF) [ ] (tDINT) (RINT)(CINT) and therefore: (4) VIN = VREF [ ] tDINT tINT where: VREF = Reference Voltage tINT = Integrate Time tDINT = Reference Voltage Deintegrate Time Inspection of equation (4) shows dual slope converter accuracy is unrelated to integrating resistor and capacitor values, as long as they are stable throughout the measurement cycle. This measurement technique is inherently ratiometric (i.e., the ratio between the tINT and tDINT times is equal to the ratio between VIN and VREF). 3-54 Another inherent benefit is noise immunity. Input noise spikes are integrated (or averaged to zero) during the integration period. The integrating converter has a noise immunity with an attenuation rate of at least –20dB per decade. Interference signals with frequencies at integral multiples of the integration period are, for the most part, completely removed. For this reason, the integration period of the converter is often established to reject 50/60Hz line noise. The ability to reject such noise is shown by the plot of Figure 3. In addition to the two phases required for dual slope measurement (Integrate and Deintegrate), the TC530/534 performs two additional adjustments to minimize measurement error due to system offset voltages. The resulting four internal operations (conversion phases) performed each measurement cycle are: Auto Zero (AZ), Integrator Output Zero (IZ), Input Integrate (INT) and Reference Deintegrate (DINT). The AZ and IZ phases compensate for system offset errors and the INT and DINT phases perform the actual A/D conversion. NORMAL MODE REJECTION (dB) DETAILED DESCRIPTION Dual Slope Integrating Converter 30 T = MEASUREMENT PERIOD 20 10 0 0.1/T 1/T INPUT FREQUENCY 10/T Figure 3. Integrating Converter Normal Mode Rejection TELCOM SEMICONDUCTOR, INC. 5V PRECISION DATA ACQUISITION SUBSYSTEMS 1 TC530 TC534 Auto Zero Phase (AZ) This phase compensates for errors due to buffer, integrator and comparator offset voltages. During this phase, an internal feedback loop forces a compensating error voltage on auto zero capacitor (CAZ). The duration of the AZ phase is programmable via the serial port (see also Programming AZ and INT Phase Duration paragraph of this document). Input Integrate Phase (INT) In this phase, a current directly proportional to differential input voltage is sourced into integrating capacitor CINT. The amount of voltage stored on CINT at the end of the INT phase is directly proportional to the applied differential input voltage. Input signal polarity (sign bit) is determined at the end of this phase. Converter resolution and conversion speed is a function of the duration of the INT phase, which is programmable by the user via the serial port (see also Programming AZ and INT Phase Duration paragraph of this document). The shorter the integration time, the faster the speed of conversion, but the lower the resolution. Conversely, the longer the integration time, the greater the resolution, but at slower the speed of conversion. Reference Deintegrate Phase (DINT) This phase consists of measuring the time for the integrator output to return (at a rate determined by the external reference voltage) from its initial voltage to 0V. The resulting timer data is stored in the output shift register as converted analog data. Integrator Output Zero Phase (IZ) This phase guarantees the integrator output is at zero volts when the AZ phase is entered so that only true system offset voltages will be compensated for. All internal converter timing is derived from the frequency source at OSCIN and OSCOUT. This frequency source must be either an externally provided clock signal, or an external crystal. If an external clock is used, it must be connected to the OSCIN pin and the OSCOUT pin must remain floating. If a crystal is used, it must be connected between OSCIN and OSCOUT and physically located as close to the OSCIN and OSCOUT pins as possible. In either case, the incoming clock frequency is divided by four and the resulting clock serves as the internal TC530/534 timebase. APPLICATIONS Programming the TC530/534 AZ and INT Phase Duration: These two phases have equal duration determined by the crystal (or external) frequency and the timer initialization byte (LOAD VALUE). Timing is selected as follows: TELCOM SEMICONDUCTOR, INC. (1) Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, tINT times of 33msec, 66msec and 132msec maximize 60Hz line rejection. 2 (2) Estimate Crystal Frequency Crystal frequencies as high as 2MHz are allowed. Crystal frequency is estimated using: FIN = 3 2(R) tINT where: R = Desired Converter Resolution (in counts) FIN = Input Frequency (in MHz) INT = Integration Time (in seconds) (3) Calculate LOAD VALUE [LOAD VALUE]10 = 256 – 4 (tINT)(FIN) 1024 FIN can be adjusted to a standard value during this step. The resulting base -10 LOAD VALUE must be converted to a hexadecimal number, then loaded into the serial port prior to initiating A/D conversion. DINT and IZ Phase Timing The duration of the DINT phase is a function of the amount of voltage stored on the integrator capacitor during INT, and the value of VREF. The DINT phase is initiated immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(max)/2). System RESET The TC530/534 must be forced into the AZ state when power is first applied. A .01µF capacitor connected from RESET to VCC (or external system reset logic signal) can be used to momentarily drive RESET high for a minimum of 100msec. Selecting Component Values for the TC530/534 (1) Calculate Integrating Resistor (RINT) The desired full-scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a fullscale current of 20µA. The value of RINT is therefore directly calculated as follows: 3-55 5 6 7 8 5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534 RINT (MΩ) = Table 2. Recommend Capacitor for CINT VINMAX 20 Value where: VINMAX = Maximum Input Voltage (full count voltage) RINT = Integrating Resistor (in MΩ) For loop stability, RINT should be ≥ 50kΩ. (2) Select Reference (CREF) and Auto Zero (CAZ) Capacitors CREF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 1. Larger values for CAZ and CREF may also be used to limit roll-over errors. Table 1. CREF and CAZ Selection Conversions Typical Value of Suggested * Per Second CREF, CAZ (µF) Part Number >7 2 to 7 2 or less 0.1 0.22 0.47 WIMA MK12 .1/63/20 WIMA MK12 .22/63/20 WIMA MK12 .47/63/20 *WIMA Corp. listing on the last page of this data sheet. 3. Calculate Integrating Capacitor (CINT) The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e. |VDD – 0.9V| or |VSS + 0.9V|). Using the 20µA buffer maximum output current, the value of the integrating capacitor is calculated using the following equation: CINT (µF) = (tINT)(20) (VS – 0.9) where: tINT VS CINT = Integration Period = Applied Supply Voltage = Integrator Capacitor Value (in µF) It is critical that the integrating capacitor have a very low dielectric absorption. PPS capacitors are an example of one such chemistry. Table 2 summarizes various capacitors suitable for CINT. 0.1 0.22 0.33 0.47 Suggested Part Number* WIMA MK12 .1/63/20 WIMA MK12 .22/63/20 WIMA MK12 .33/63/20 WIMA MK12 .47/63/20 *WIMA Corp. listing on the last page of this data sheet. 4. Calculate VREF The reference deintegration voltage is calculated using: VREF (in Volts) = (VS – 0.9)(CINT)(RINT) 2(tINT) Serial Port Communication with the TC530/534 is accomplished over a 3 wire serial port. Data is clocked into DIN on the rising edge of DCLK and clocked out of DOUT on the falling edge of DCLK. R/W must be HIGH to read converted data from the serial port and LOW to write the LOAD VALUE to the TC530/ 534. Load Value Write Cycle (Figure 4) Following the power-up reset pulse, the LOAD VALUE (which sets the duration of AZ and INT) must next be transmitted to the serial port. To accomplish this, the processor monitors the state of EOC (which is available as a hardware output or at DOUT). R/W is taken low to initiate the write cycle only when EOC is low (during the AZ phase). (Failure to observe EOC low may cause an offset voltage to be developed across CINT resulting in erroneous readings). The 8 bit LOAD VALUE data on DIN is clocked in by DCLK. The processor then terminates the write cycle by taking R/W high. (Data is transferred from the serial input shift register to the time base counter on the rising edge of R/W, and data conversion is initiated). Data Read Cycle (Figure 5) Data is shifted out of the serial port in the following order: End of Conversion (EOC), Overrange (OVR), Sign (SGN), conversion data (MSB first). When R/W is high, the state of the EOC bit can be polled by simply reading the state of DOUT. This allows the processor to determine if new data is available without connecting an additional wire to the EOC output pin (this is especially useful in a polled environment). Input Multiplexer (TC534 Only) A 4 input, differential multiplexer is included in the TC534. The states of channel address lines A0 and A1 determine which differential VIN pair is routed to the con- 3-56 TELCOM SEMICONDUCTOR, INC. 5V PRECISION DATA ACQUISITION SUBSYSTEMS 1 TC530 TC534 Timing Status Power-up RESET Conversion Phase Undefined Write LOAD VALUE to Serial Port AZ AZ INT R/W brought LOW during AZ for serial port write cycle R/W Converter in Normal Service Converter held in AZ state due to RESET = 1 DINT IZ 2 AZ… Continuous Conversions R/W = HIGH strobes LOAD VALUE into timebase and starts conversion RESET 3 DCLK DIN 1 1 MSB 0 0 1 1 LOAD VALUE 1 4 1 LSB EOC Figure 4. TC530/534 Initialization and Load Value Write Cycle verter input. A0 is the least significant address bit (i.e., channel 1 is selected when A0 = 1 and A1 = 0). The multiplexer is designed to be operated in a differential mode. For single-ended inputs, the CHx– input for the channel under selection must be connected to the ground reference associated with the input signal. 5 APPLICATIONS Design Example R/W DCLK DOUT The charge pump clock operates at a typical frequency of 100kHz. If lower quiescent current is desired, the charge pump clock can be slowed by connecting an external capacitor from the OSC pin to VDD. Reference typical characteristics curves. EOC OVR POL MSB LSB Figure 5. Serial Port Data Read Cycle DC/DC Converter An on-board, TC7660H-type charge pump supplies negative bias to the converter circuitry, as well as to external devices. The charge pump develops a negative output voltage by moving charge from the power supply to the reservoir capacitor at VSS by way of the commutating capacitor connected to the CAP+ and CAP– inputs. TELCOM SEMICONDUCTOR, INC. Figure 6 shows a typical TC534 interrupt-driven application. Timing and component values are calculated from equations and recommendations made in the Dual Slope Integrating Converter and Programming the TC530/534 sections of this document. The EOC connection to the processor INT input is for interrupt-driven applications only. (In polled systems, the EOC output is available on DOUT). GIVEN REQUIRED RESOLUTION: 16 Bits (65,536 counts.) MAXIMUM VIN: ±2V POWER SUPPLY VOLTAGE: +5V 60Hz SYSTEM 1. Pick Integration time (tINT) 66msec 2. Estimate crystal frequency FIN = 2R/tINT = 2 x 65536/66 x 10 –3 = 1.98MHz (use 2MHz) 3-57 6 7 8 5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534 3. Calculate LOAD VALUE LOAD VALUE = 256 – (tINT)(FIN)/1024 = [128]10 [128]10 = 80 hex 7. Calculate VREF VREF (in Volts = (VS – 0.9)(CINT)(RINT) 2(tINT) 4. Calculate RINT RINT (in MΩ) = VINMAX/20 = 2/20 = 100kΩ = (4.1)(0.33x10 –6)(105)/2(.066) = 1.025V 5. Calculate CINT for maximum (4V) integrator output swing CINT (in µF) = (tINT)(20 x 10 –6)/ (VS – 0.9) = (.066)(20 x 10 –6)/(4.1) = .32µF (use closest value: 0.33µF) NOTE: TelCom recommended capacitor: WIMA p/n: MK12 .33/63/10 6. Choose CREF and CAZ based on conversion rate Conversions/sec = 1/(tAZ + tINT + 2tINT + 2msec) = 1/(66msec + 66msec + 132msec + 2msec) = 3.7 conversions/sec from which CAZ = CREF = 0.22µF (see Table 1) NOTE: TelCom recommended capacitor: WIMA p/n: MK12 .22/63/10 Power Supply Sequencing Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur. See Circuit Design/Layout Considerations below. Failing to insure a proper power-up sequence can cause spurious operation. Ciruit Design/Layout Considerations (1) Separate ground return paths should be used for the analog and digital circuitry. Use of ground planes and trace fill on analog circuit sections is highly recommended EXCEPT for in and around the integrator section and CREF, CAZ. (CINT, CREF, CAZ, RINT). Stray capacitance between these nodes and ground appears in parallel with the components themselves and can affect measurement accuracy. +5V +5V C1 .01µF VDD IN2 IN2 Analog Inputs VCCD IN3 IN3 VCCD IN4 100Ω VDD + (Optional) – EOC + R/W I/O DOUT I/O DIN I/O DCLK I/O – 1µF IN4 10µF RESET – IN1 .01µF .01µF + IN1 + – INT PROCESSOR TC534 CIN CAZ 0.33µF 0.22µF CINT OSCIN X1: 2MHz OSCOUT CAZ BUF RINT MUX Channel Control +5V 1µF DGND 100k CREF 0.22µF –5V VSS C+REF – CREF + VREF A0 R2 100k (1.03V) A1 + R1 100k TC04 (1.25V VREF) – VREF CAP ACOM 1µF CAP – Figure 6. TC530/534 Typical Application 3-58 TELCOM SEMICONDUCTOR, INC. 5V PRECISION DATA ACQUISITION SUBSYSTEMS 1 TC530 TC534 (2) Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur in the internal state machines. It is recommended that the digital supply, VCCD, be powered up first. One method of insuring the correct power-up sequence is to delay the analog supply using a series resistor and a capacitor. See Figure 6, TC530/534 Typical Application. (6) Circuit assemblies should be scrupulously clean to prevent the presence of contamination from assembly, handling, or the cleaning itself. Minutely conductive trace contaminates, easily ignored in most applications, can adversely affect the performance of high impedance circuits. The input and integrator sections should be made as compact and close to the TC53x as possible. (3) Decoupling capacitors, preferably a higher value electrolytic or tantulum in parallel with a small ceramic or tantalum, should be used liberally. This includes bypassing the supply connections of all active components and the voltage reference. (7) Digital and other dynamic signal conductors should be kept as far from the TC53x’s analog section as possible. The microcontroller or other host logic should be kept quiet during a measurement cycle. Background activites such as keypad scanning, display refreshing, and power switching can introduce noise. (4) Critical components should be chosen for stability and low noise. The use of a metal-film resistor for RINT and Polypropylene or Polyphenelyne Sulfide (PPS) capacitors for CINT, CAZ, and CREF is highly recommended. (5) The inputs and integrator section are very high impedance nodes. Leakage to or from these critical nodes can contribute measurement error. A guard-ring should be used to protect the integrator section from stray leakage. 2 3 TC530EV Evaluation Kit The TC530EV consists of a 4" x 6" pre-assembled circuit board that connects to the serial port of any PC or dumb terminal. Also included is a WindowsTM* ExcelTM*-based design utility that calculates component and LOAD values based on user input, and prints a finished circuit schematic. Please contact your local TelCom representative for more information, or point your web browser to http://www.telcomsemi.com. 4 5 6 7 8 *All trademarks are the property of their respective owners. TELCOM SEMICONDUCTOR, INC. 3-59 5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534 TYPICAL CHARACTERISTICS Output Voltage vs. Output Current Output Voltage vs Load Current 5 –0 TA = 25°C V+ = 5V 4 TA = 25°C –1 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3 2 1 0 –1 –2 Slope 60Ω –3 –2 –3 –4 –5 –6 –7 –4 –8 –5 0 10 20 30 40 50 LOAD CURRENT (mA) 60 70 80 0 OUTPUT SOURCE RESISTANCE (Ω) OUTPUT RIPPLE (mV PK-PK) 150 CAP = 1µF 125 100 CAP = 10µF 75 50 25 1 2 3 4 5 6 7 8 9 90 12 14 10 20 60 50 0 –25 25 50 75 100 Oscillator Frequency vs. Temperature 10 1 100 OSCILLATOR CAPACITANCE (pF) 1000 OSCILLATOR FREQUENCY (kHz) 150 TA = +25°C V+ = 5V 10 18 TEMPERATURE (°C) 100 1 16 70 Oscillator Frequency vs. Capacitance OSCILLATOR FREQUENCY (kHz) 10 V+ = 5V IOUT = 10mA LOAD CURRENT (mA) 3-60 8 80 40 –50 0 0 6 Output Source Resistance vs. Temperature 100 V+ = 5V, TA = 25°C Osc. Freq. = 100kHz 175 4 OUTPUT CURRENT (mA) Output Ripple vs. Load Current 200 2 V+ = 5V 125 100 75 50 –50 –25 0 25 75 50 TEMPERATURE (°C) 100 125 TELCOM SEMICONDUCTOR, INC. 5V PRECISION DATA ACQUISITION SUBSYSTEMS 1 TC530 TC534 WIMA Corporation Capacitor Representatives (Tables 1 and 2) Australia: ADILAM ELECTRONICS (PTY.) LTD. P.O. Box 664 3 Nicole Close Bayswater 3153 Tel.: 3-7 61 44 66 Fax: 3-7 61 41 61 Canada: R-THETA INC. 130 Matheson Blvd. East, Unit 2 Mississauga, Ont. L4Z1Y6 Tel.: 9 05-8 90-02 21 Fax: 9 05-8 90-16 28 Hong Kong: REALTRONICS CO. LTD. E-3, Hung-On Building 2, King's Road Tel.: 25 70 11 51 Fax: 28 06 84 74 India: SUSAN AGENCIES P.O. Box 2138 Srirampuram P.O. Bangalore-560 021 Tel.: 0 80-3 32 06 62 Fax: 0 80-3 32 43 38 Israel: M.G.R. TECHNOLOGY P.O. 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Box 535 Elmsford, NY 10523-0535 Tel.: 914-347-2474 Fax: 914-347-7230 3 TAW ELECTRONICS, INC. 4215, W. Burbank, Blvd. Burbank, CA, 91505 Tel.: 8 18-8 46-39 11 Fax: 8 18-8 46-11 94 4 Venezuela: MAGNETICA, S.A. Apartado 78117 Caracas 1074 A Tel.: 58-2-2 41 75 09 Fax: 58-2-2 41 55 42 5 Taiwan, R.O.C.: SOLOMON TECHNOLOGY CORP. 7th Floor No. 2 Lane 47, Sec. 3 Nan Kang Road Taipei Tel.: 8 86-2-7 88 89 89 Fax: 8 86-2-7 88 82 75 6 7 8 TELCOM SEMICONDUCTOR, INC. 3-61