OPA354 OPA2354 OPA4354 SBOS233C − MARCH 2002− REVISED APRIL 2004 250MHz, Rail-to-Rail I/O, CMOS OPERATIONAL AMPLIFIERS FEATURES D D D D D D D D D D D D UNITY-GAIN BANDWIDTH: 250MHz WIDE BANDWIDTH: 100MHz GBW HIGH SLEW RATE: 150V/µs LOW NOISE: 6.5nV/√Hz RAIL-TO-RAIL I/O HIGH OUTPUT CURRENT: > 100mA EXCELLENT VIDEO PERFORMANCE: Diff Gain: 0.02%, Diff Phase: 0.095 0.1dB Gain Flatness: 40MHz LOW INPUT BIAS CURRENT: 3pA QUIESCENT CURRENT: 4.9mA THERMAL SHUTDOWN SUPPLY RANGE: 2.5V to 5.5V MicroSIZE AND PowerPAD PACKAGES APPLICATIONS D D D D D D D D D D VIDEO PROCESSING ULTRASOUND OPTICAL NETWORKING, TUNABLE LASERS PHOTODIODE TRANSIMPEDANCE AMPS ACTIVE FILTERS HIGH-SPEED INTEGRATORS ANALOG-TO-DIGITAL (A/D) CONVERTER INPUT BUFFERS DIGITAL-TO-ANALOG (D/A) CONVERTER OUTPUT AMPLIFIERS BARCODE SCANNERS COMMUNICATIONS DESCRIPTION The OPA354 series of high-speed, voltage-feedback CMOS operational amplifiers are designed for video and other applications requiring wide bandwidth. They are unity-gain stable and can drive large output currents. Differential gain is 0.02% and differential phase is 0.09°. Quiescent current is only 4.9mA per channel. The OPA354 series op amps are optimized for operation on single or dual supplies as low as 2.5V (±1.25V) and up to 5.5V (±2.75V). Common-mode input range extends beyond the supplies. The output swing is within 100mV of the rails, supporting wide dynamic range. For applications requiring the full 100mA continuous output current, single and dual SO-8 PowerPAD versions are available. The single version (OPA354), is available in the tiny SOT23-5 and SO-8 PowerPAD packages. The dual version (OPA2354) comes in the miniature MSOP-8 and SO-8 PowerPAD packages. The quad version (OPA4354) is offered in TSSOP-14 and SO-14 packages. Multichannel versions feature completely independent circuitry for lowest crosstalk and freedom from interaction. All are specified over the extended −40°C to +125°C temperature range. OPAx357 RELATED PRODUCTS FEATURES PRODUCT Shutdown Version of OPA354 Family OPAx357 200MHz GBW, Rail-to-Rail Output, CMOS, Shutdown OPAx355 200MHz GBW, Rail-to-Rail Output, CMOS OPAx356 38MHz GBW, Rail-to-Rail Input/Output, CMOS OPAx350/3 75MHz BW G = 2, Rail-to-Rail Output OPAx631 150MHz BW G = 2, Rail-to-Rail Output OPAx634 100MHz BW, Differential Input/Output, 3.3V Supply THS412x V+ −In OPA354 VOUT +In V− Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2002−2004, Texas Instruments Incorporated ! ! www.ti.com "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, V+ to V− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V Signal Input Terminals Voltage(2) . . . (V−) − (0.5V) to (V+) + (0.5V) Current(2) . . . . . . . . . . . . . . . . . . . . . 10mA Output Short-Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Operating Temperature . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. (3) Short-circuit to ground, one amplifier per package. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA354 SO-8 PowerPAD DDA −40°C to +125°C OPA354A OPA354AIDDA OPA354AIDDAR Rails, 97 Tape and Reel, 2500 OPA354 SOT23-5 DBV −40°C to +125°C OABI OPA354AIDBVT OPA354AIDBVR Tape and Reel, 250 Tape and Reel, 3000 OPA2354 SO-8 PowerPAD DDA −40°C to +125°C OPA2354A OPA2354AIDDA OPA2354AIDDAR Rails, 97 Tape and Reel, 2500 OPA2354 MSOP-8 DGK −40°C to +125°C OACI OPA2354AIDGKT OPA2354AIDGKR Tape and Reel, 250 Tape and Reel, 2500 OPA4354 SO-14 D −40°C to +125°C OPA4354A OPA4354AID OPA4354AIDR Rails, 58 Tape and Reel, 2500 OPA4354 TSSOP-14 PW −40°C to +125°C OPA4354A OPA4354AIPWT OPA4354AIPWR Tape and Reel, 250 Tape and Reel, 2500 ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ ″ (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. 2 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 PIN CONFIGURATIONS Top View OPA354 OPA2354 OPA354 NC (1) 1 8 NC (1 ) −In 2 7 V+ +In 3 6 Out V− 4 5 NC (1 ) Out 1 V− 2 +In 3 5 V+ Out A 1 −In A 2 8 V+ 7 Out B 6 −In B 5 +In B A 4 +In A −In 3 B V− 4 SOT23 SO PowerPAD(2) MSOP SO PowerPAD(2) OPA4354 Out A 1 −In A 2 +In A 14 Out D 13 −In D 3 12 +In D V+ 4 11 V− +In B 5 10 +In C A D B C −In B 6 9 −In C Out B 7 8 Out C SO TSSOP NOTES: (1) NC means no internal connection. (2) PowerPAD should be connected to V− or left floating. 3 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V Single-Supply Boldface limits apply over the temperature range, TA = −40°C to +125°C. All specifications at TA = +25°C, RF = 0Ω , RL = 1kΩ connected to VS/2, unless otherwise noted. OPA354AI OPA2354AI, OPA4354AI PARAMETER CONDITIONS MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage VOS vs Temperature dVOS/dT vs Power Supply PSRR ±2 VS = +5V Specified Temperature Range Specified Temperature Range +4 VS = +2.7V to +5.5V, VCM = (VS/2) − 0.15V Specified Temperature Range ±200 ±8 mV +10 mV µV/°C ±800 µV/V ±900 µV/V 3 ±50 pA ±1 ±50 pA INPUT BIAS CURRENT Input Bias Current Input Offset Current IB IOS NOISE Input Voltage Noise Density Current Noise Density en in f = 1MHz 6.5 nV/√Hz f = 1MHz 50 fA/√Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio VCM CMRR (V−) − 0.1 VS = +5.5V, −0.1V < VCM < +3.5V Specified Temperature Range 66 VS = +5.5V, −0.1V < VCM < +5.6V Specified Temperature Range 56 (V+) + 0.1 80 64 V dB dB 68 55 dB dB INPUT IMPEDANCE 1013 || 2 1013 || 2 Differential Common-Mode OPEN-LOOP GAIN AOL Specified Temperature Range VS = +5V, +0.3V < VO < +4.7V VS = +5V, +0.4V < VO < +4.6V 94 110 90 Ω || pF Ω || pF dB dB FREQUENCY RESPONSE Small-Signal Bandwidth f−3dB f−3dB G = +1, VO = 100mVPP, RF = 25Ω 250 MHz G = +2, VO = 100mVPP 90 MHz GBW G = +10 100 MHz f0.1dB SR G = +2, VO = 100mVPP 40 MHz VS = +5V, G = +1, 4V Step VS = +5V, G = +1, 2V Step 150 V/µs 130 V/µs VS = +3V, G = +1, 2V Step G = +1, VO = 200mVPP, 10% to 90% 110 V/µs 2 ns G = +1, VO = 2VPP, 10% to 90% 11 ns VS = +5V, G = +1, 2V Output Step 30 ns 60 ns VIN S Gain = VS 5 ns 2nd-Harmonic G = +1, f = 1MHz, VO = 2VPP, RL = 200Ω, VCM = 1.5V −75 dBc 3rd-Harmonic G = +1, f = 1MHz, VO = 2VPP, RL = 200Ω, VCM = 1.5V −83 dBc Differential Gain Error NTSC, RL = 150Ω 0.02 % Differential Phase Error NTSC, RL = 150Ω 0.09 degrees f = 5MHz −100 dB −84 dB Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Slew Rate Rise-and-Fall Time Settling Time, 0.1% 0.01% Overload Recovery Time Harmonic Distortion Channel-to-Channel Crosstalk OPA2354 OPA4354 (1) See typical characteristics Output Voltage Swing vs Output Current. (2) Specified by design. 4 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V Single-Supply (continued) Boldface limits apply over the temperature range, TA = −40°C to +125°C. All specifications at TA = +25°C, RF = 0Ω , RL = 1kΩ connected to VS/2, unless otherwise noted. OPA354AI OPA2354AI, OPA4354AI PARAMETER CONDITIONS MIN TYP MAX UNITS 0.1 0.3 V OUTPUT Voltage Output Swing from Rail Specified Temperature Range Output Current(1)(2), Single, Dual, Quad IO VS = +5V, RL = 1kΩ, AOL > 94dB VS = +5V, RL = 1kΩ, AOL > 90dB VS = +5V 100 VS = +3V f < 100kHz Closed-Loop Output Impedance Open-Loop Output Resistance 0.4 RO V mA 50 mA 0.05 Ω 35 Ω POWER SUPPLY Specified Voltage Range VS 2.7 Operating Voltage Range Quiescent Current (per amplifier) 5.5 V 6 mA 7.5 mA 2.5 to 5.5 IQ VS = +5V, Enabled, IO = 0 Specified Temperature Range 4.9 V THERMAL SHUTDOWN Junction Temperature Shutdown +160 °C Reset from Shutdown +140 °C TEMPERATURE RANGE Specified Range −40 +125 °C Operating Range −55 +150 °C Storage Range −65 +150 Thermal Resistance qJA °C °C/W SOT23-5, MSOP-8 150 °C/W TSSOP-14 100 °C/W SO-14 100 °C/W SO-8 PowerPAD 65 °C/W (1) See typical characteristics Output Voltage Swing vs Output Current. (2) Specified by design. 5 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 TYPICAL CHARACTERISTICS At TA = +25°C, VS = 5V, G = +1, RF = 0Ω, RL = 1kΩ, and connected to VS/2, unless otherwise noted. NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 3 G = +1 RF = 25Ω VO = 0.1VPP VO = 0.1VPP, RF = 604Ω 0 Normalized Gain (dB) 0 Normalized Gain (dB) INVERTING SMALL−SIGNAL FREQUENCY RESPONSE G = +2, RF = 604Ω −3 G = +5, RF = 604Ω −6 G = +10, RF = 604Ω −9 −12 −3 G = −1 −6 G = −5 G = −10 −12 −15 100k 1M 10M Frequency (Hz) 100M −15 100k 1G 1M 100M 1G Output Voltage (500mV/div) Output Voltage (40mV/div) Time (20ns/div) Time (20ns/div) HARMONIC DISTORTION vs OUTPUT VOLTAGE 0.1dB GAIN FLATNESS 0.4 −50 VO = 0.1VPP Harmonic Distortion (dBc) 0.5 Normalized Gain (dB) 10M Frequency (Hz) NONINVERTING LARGE−SIGNAL STEP RESPONSE NONINVERTING SMALL−SIGNAL STEP RESPONSE 0.3 G = +1 RF = 25Ω 0.2 0.1 0 −0.1 −0.2 G = +2 RF = 604Ω −0.3 −0.4 −0.5 100k 6 G = −2 −9 G = −1 f = 1MHz RL = 200Ω −60 −70 2nd−Harmonic −80 −90 3rd−Harmonic −100 1M 10M Frequency (Hz) 100M 1G 0 1 2 Output Voltage (VPP) 3 4 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = 5V, G = +1, RF = 0Ω, RL = 1kΩ, and connected to VS/2, unless otherwise noted. HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs NONINVERTING GAIN −50 −50 Harmonic Distortion (dBc) −60 −70 2nd−Harmonic −80 −90 VO = 2VPP f = 1MHz RL = 200Ω −60 Harmonic Distortion (dBc) VO = 2VPP f = 1MHz RL = 200Ω −70 2nd−Harmonic −80 3rd−Harmonic −90 3rd−Harmonic −100 −100 1 1 10 10 Gain (V/V) Gain (V/V) HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY −50 −50 Harmonic Distortion (dBc) −60 −70 2nd−Harmonic −80 3rd−Harmonic −90 −60 Harmonic Distortion (dBc) G = +1 VO = 2VPP RL = 200Ω VCM = 1.5V G = +1 VO = 2VPP f = 1MHz VCM = 1.5V −70 2nd−Harmonic −80 3rd−Harmonic −90 −100 −100 100k 1M Frequency (Hz) 100 10M 1k RL (Ω) INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY FREQUENCY RESPONSE FOR VARIOUS RL 10k 3 1k Voltage Noise Normalized Gain (dB) Voltage Noise (nV/√Hz), Current Noise (fA/√Hz) RL = 10kΩ 0 Current Noise 100 10 −3 −6 G = +1 R F = 0Ω VO = 0.1VPP C L = 0pF RL = 1kΩ RL = 100Ω −9 RL = 50Ω −12 1 10 100 1k 10k 100k Frequency (Hz) 1M 10M 100M −15 100k 1M 10M Frequency (Hz) 100M 1G 7 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = 5V, G = +1, RF = 0Ω, RL = 1kΩ, and connected to VS/2, unless otherwise noted. FREQUENCY RESPONSE FOR VARIOUS CL RECOMMENDED RS vs CAPACITIVE LOAD 9 160 G = +1 VO = 0.1VPP R S = 0Ω Normalized Gain (dB) 6 3 For 0.1dB Flatness 140 CL = 100pF 120 0 −3 RS (Ω) 100 CL = 47pF −6 80 60 VIN −9 CL 0 1M 10M Frequency (Hz) 100M 1G 1 1k 10 100 Capacitive Load (pF) COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY FREQUENCY RESPONSE vs CAPACITIVE LOAD 100 3 G = +1 VO = 0.1VPP 0 CL = 5.6pF, RS = 0Ω CMRR 80 CMRR, PSRR (dB) Normalized Gain (dB) 1kΩ 20 −15 100k CL = 47pF, RS = 140Ω −3 CL = 100pF, RS = 120Ω −6 −9 VIN RS VO OPA354 −12 CL −15 100k PSRR+ 60 PSRR− 40 20 1kΩ 0 1M 10M Frequency (Hz) 10k 1G 100M 100k 1M 10M Frequency (Hz) 100M 1G COMPOSITE VIDEO DIFFERENTIAL GAIN AND PHASE OPEN−LOOP GAIN AND PHASE 0.8 180 160 0.7 140 120 dG/dP (%/degrees) Open−Loop Phase (degrees) Open−Loop Gain (dB) VO OPA354 CL = 5.6pF −12 Phase 100 80 60 40 Gain 20 0.6 0.5 dP 0.4 0.3 0.2 0 −20 0.1 −40 0 10 8 RS 40 100 1k 10k 100k 1M Frequency (Hz) 10M 100M 1G dG 1 2 3 Number of 150Ω Loads 4 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = 5V, G = +1, RF = 0Ω, RL = 1kΩ, and connected to VS/2, unless otherwise noted. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT FOR VS = 3V INPUT BIAS CURRENT vs TEMPERATURE 3 1k Output Voltage (V) Input Bias Current (pA) 10k 100 2 +125_ C −55_ C +25_ C 1 10 1 0 −55 −35 −15 5 25 45 65 Temperature (_C) 85 0 105 125 135 20 40 60 80 100 120 Output Current (mA) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT FOR VS = 5V SUPPLY CURRENT vs TEMPERATURE 7 5 4 VS = 5V 5 Output Voltage (V) Supply Current (mA) 6 4 VS = 2.5V 3 2 3 −55_C +25_ C +125_ C 2 1 1 0 0 −55 −35 −15 5 25 45 65 Temperature (_ C) 85 105 125 135 0 25 50 75 100 125 150 175 200 Output Current (mA) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY 6 100 VS = 5.5V 10 Output Voltage (VPP) Output Impedance (Ω) 5 1 0.1 Maximum Output Voltage without Slew−Rate Induced Distortion 4 3 VS = 2.7V 2 OPA354 1 ZO 0.01 100k 0 1M 10M Frequency (Hz) 100M 1G 1 10 100 Frequency (MHz) 9 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = 5V, G = +1, RF = 0Ω, RL = 1kΩ, and connected to VS/2, unless otherwise noted. OUTPUT SETTLING TIME TO 0.1% OPEN−LOOP GAIN vs TEMPERATURE 120 0.5 0.4 Open−Loop Gain (dB) Output Error (%) RL = 1kΩ VO = 2VPP 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 110 100 90 80 −0.4 −0.5 70 0 10 20 30 40 50 60 70 80 90 −55 100 −35 −15 5 Time (ns) 25 45 65 Temperature (_ C) 85 105 125 135 COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs TEMPERATURE OFFSET VOLTAGE PRODUCTION DISTRIBUTION 100 Population CMRR, PSRR (dB) 90 Common−Mode Rejection Ratio 80 Power−Supply Rejection Ratio 70 60 50 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 Offset Voltage (mV) 4 5 6 −55 7 8 −35 −15 5 25 CHANNEL−TO−CHANNEL CROSSTALK Crosstalk, Input−Referred (dB) 0 −20 −40 OPA4354 −60 OPA2354 −80 −100 −120 100k 1M 10M Frequency (Hz) 10 45 65 Temperature (_ C) 100M 1G 85 105 125 135 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 APPLICATIONS INFORMATION The OPA354 is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier designed for video, high-speed, and other applications. It is available as a single, dual, or quad op amp. The amplifier features a 100MHz gain bandwidth, and 150V/µs slew rate, but it is unity-gain stable and can be operated as a +1V/V voltage follower. OPERATING VOLTAGE The OPA354 is specified over a power-supply range of +2.7V to +5.5V (±1.35V to ±2.75V). However, the supply voltage may range from +2.5V to +5.5V (±1.25V to ±2.75V). Supply voltages higher than 7.5V (absolute maximum) can permanently damage the amplifier. Parameters that vary over supply voltage or temperature are shown in the typical characteristics section of this data sheet. RAIL-TO-RAIL INPUT The specified input common-mode voltage range of the OPA354 extends 100mV beyond the supply rails. This is achieved with a complementary input stagean N-channel input differential pair in parallel with a P-channel differential pair, as shown in Figure 1. The N-channel pair is active for input voltages close to the positive rail, typically (V+) − 1.2V to 100mV above the positive supply, while the P-channel pair is on for inputs from 100mV below the negative supply to approximately (V+) − 1.2V. There is a small transition region, typically (V+) − 1.5V to (V+) − 0.9V, in which both pairs are on. This 600mV transition region can vary ±500mV with process variation. Thus, the transition region (both input stages on) can range from (V+) − 2.0V to (V+) − 1.5V on the low end, up to (V+) − 0.9V to (V+) − 0.4V on the high end. A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class AB output stage. RAIL-TO-RAIL OUTPUT A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For high-impedance loads (> 200Ω), the output voltage swing is typically 100mV from the supply rails. With 10Ω loads, a useful output swing can be achieved while maintaining high open-loop gain. See the typical characteristic curve Output Voltage Swing vs Output Current. V+ Reference Current VIN+ VIN− VBIAS1 Class AB Control Circuitry VO VBIAS2 V− (Ground) Figure 1. Simplified Schematic 11 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 OUTPUT DRIVE R2 10kΩ The OPA354’s output stage can supply a continuous output current of ±100mA and still provide approximately 2.7V of output swing on a 5V supply, as shown in Figure 2. For maximum reliability, it is not recommended to run a continuous DC current in excess of ±100mA. Refer to the typical characteristic curve Output Voltage Swing vs Output Current. For supplying continuous output currents greater than ±100mA, the OPA354 may be operated in parallel, as shown in Figure 3. C1 200pF +5V 1µF R1 100kΩ R5 1Ω OPA2354 The OPA354 will provide peak currents up to 200mA, which corresponds to the typical short-circuit current. Therefore, an on-chip thermal shutdown circuit is provided to protect the OPA354 from dangerously high junction temperatures. At 160°C, the protection circuit will shut down the amplifier. Normal operation will resume when the junction temperature cools to below 140°C. R3 100kΩ + − R6 1Ω 2V In = 200mA Out, as Shown RSHUNT 1Ω OPA2354 R4 10kΩ R2 1kΩ + − C1 50pF Laser Diode V1 5V 1µF R1 10kΩ Figure 3. Parallel Operation V+ VIDEO OPA354 + VIN R3 10kΩ − 1V In = 100mA Out, as Shown V− RSHUNT 1Ω R4 1kΩ The OPA354 output stage is capable of driving standard back-terminated 75Ω video cables, as shown in Figure 4. By back-terminating a transmission line, it does not exhibit a capacitive load to its driver. A properly back-terminated 75Ω cable does not appear as capacitance; it presents only a 150Ω resistive load to the OPA354 output. Laser Diode +5V Figure 2. Laser Diode Driver Video In 75Ω 75Ω OPA354 Video Output +2.5V 604Ω 604Ω +2.5V Figure 4. Single-Supply Video Line Driver 12 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 The OPA354 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video black level, by offsetting and AC-coupling the signal. See Figure 5. circuits. The OPA354 series provide an effective means of buffering the A/D converter’s input capacitance and resulting charge injection while providing signal gain. For applications requiring high DC accuracy, the OPA350 series is recommended. DRIVING ANALOG−TO−DIGITAL CONVERTERS Figure 6 illustrates the OPA354 driving an A/D converter. With the OPA354 in an inverting configuration, a capacitor across the feedback resistor can be used to filter high-frequency noise in the signal. The OPA354 series op amps offer 60ns of settling time to 0.01%, making them a good choice for driving high- and medium-speed sampling A/D converters and reference 604Ω +3V + V+ 10nF 604Ω 75Ω 1/2 OPA2354 R1 Red(1) 1µF Red 75Ω R2 V+ R1 Green(1) R2 604Ω 75Ω 1/2 OPA2354 Green 75Ω 604Ω NOTE: (1) Source video signal offset 300mV above ground to accomodate op amp swing−to−ground capability. 604Ω +3V + V+ 1µF 10nF 604Ω 75Ω Blue(1) R1 OPA354 Blue 75Ω R2 Figure 5. RGB Cable Driver 13 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 +5V 330pF 5kΩ 5kΩ VIN VREF V+ +In OPA354 +2.5V −In ADS7816, ADS7861, or ADS7864 12−Bit A/D Converter GND VIN = 0V to −5V for 0V to 5V output. NOTE: A/D Converter Input = 0V to VREF Figure 6. The OPA354 in Inverting Configuration Driving the ADS7816 CAPACITIVE LOAD AND STABILITY The OPA354 series op amps can drive a wide range of capacitive loads. However, all op amps under certain conditions may become unstable. Op amp configuration, gain, and load value are just a few of the factors to consider when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of capacitive loading. The capacitive load reacts with the op amp’s output resistance, along with any additional load resistance, to create a pole in the small-signal response that degrades the phase margin. Refer to the typical characteristic curve Frequency Response for Various CL for details. The OPA354’s topology enhances its ability to drive capacitive loads. In unity gain, these op amps perform well with large capacitive loads. Refer to the typical characteristic curve Recommended RS vs Capacitive Load and Frequency Response vs Capacitive Load for details. One method of improving capacitive load drive in the unity-gain configuration is to insert a 10Ω to 20Ω resistor in series with the output, as shown in Figure 7. This significantly reduces ringing with large capacitive loadssee the typical characteristic curve Frequency Response vs Capacitive Load. However, if there is a resistive load in parallel with the capacitive load, RS creates a voltage divider. This introduces a DC error at the output and slightly reduces output swing. This error may be insignificant. For instance, with RL = 10kΩ and RS = 20Ω, there is only about a 0.2% error at the output. 14 V+ RS VOUT OPA354 VIN RL CL Figure 7. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive WIDEBAND TRANSIMPEDANCE AMPLIFIER Wide bandwidth, low input bias current, and low input voltage and current noise make the OPA354 an ideal wideband photodiode transimpedance amplifier for low-voltage single-supply applications. Low-voltage noise is important because photodiode capacitance causes the effective noise gain of the circuit to increase at high frequency. "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 The key elements to a transimpedance design, as shown in Figure 8, are the expected diode capacitance (including the parasitic input common-mode and differential-mode input capacitance (2 + 2)pF for the OPA354), the desired transimpedance gain (RF), and the Gain Bandwidth Product (GBP) for the OPA354 (100MHz). With these 3 variables set, the feedback capacitor value (CF) may be set to control the frequency response. A 10nF ceramic bypass capacitor is the minimum recommended value; adding a 1µF or larger tantalum capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass capacitance is essential to achieving very low harmonic and intermodulation distortion. POWER DISSIPATION Power dissipation depends on power-supply voltage, signal and load conditions. With DC signals, power dissipation is equal to the product of output current times the voltage across the conducting output transistor, VS − VO. Power dissipation can be minimized by using the lowest possible power-supply voltage necessary to assure the required output voltage swing. CF < 1pF (prevents gain peaking) RF 10MΩ +V For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply voltage. Dissipation with AC signals is lower. Application Bulletin AB-039 (SBOA022), Power Amplifier Stress and Power Handling Limitations, explains how to calculate or measure power dissipation with unusual signals and loads, and can be found at www.ti.com. λ CD OPA354 VOUT Figure 8. Transimpedance Amplifier To achieve a maximally flat 2nd-order Butterworth frequency response, the feedback pole should be set to: 1 + 2pR FCF GBP Ǹ4pR C F D (1) Typical surface-mount resistors have a parasitic capacitance of around 0.2pF that must be deducted from the calculated feedback capacitance value. Bandwidth is calculated by: f *3dB + GBP Hz Ǹ2pR C F D Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 150°C, maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered at 160°C. The thermal protection should trigger more than 35°C above the maximum expected ambient condition of your application. PowerPAD THERMALLY ENHANCED PACKAGE (2) For even higher transimpedance bandwidth, the high-speed CMOS OPA355 (200MHz GBW) or the OPA655 (400MHz GBW) may be used. PCB LAYOUT Good high-frequency printed circuit board (PCB) layout techniques should be employed for the OPA354. Generous use of ground planes, short and direct signal traces, and a suitable bypass capacitor located at the V+ pin will assure clean, stable operation. Large areas of copper also provides a means of dissipating heat that is generated in normal operation. Sockets are definitely not recommended for use with any high-speed amplifier. Besides the regular SOT23-5 and MSOP-8, the single and dual versions of the OPA354 also come in SO-8 PowerPAD. The SO-8 PowerPAD is a standard-size SO-8 package where the exposed leadframe on the bottom of the package can be soldered directly to the PCB to create an extremely low thermal resistance. This will enhance the OPA354’s power dissipation capability significantly and eliminates the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard PCB assembly techniques. NOTE: Since the SO-8 PowerPAD is pin-compatible with standard SO-8 packages, the OPA354 and OPA2354 can directly replace operational amplifiers in existing sockets. Soldering the PowerPAD to the PCB is always required, even with applications that have low power dissipation. This provides the necessary thermal and mechanical connection between the leadframe die pad and the PCB. 15 "#$ %"#$ $"#$ www.ti.com SBOS233C − MARCH 2002− REVISED APRIL 2004 The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the IC, as shown in Figure 9. This provides an extremely low thermal resistance (qJC) path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB as a heatsink. In addition, plated-through holes (vias) provide a low thermal resistance heat flow path to the back side of the PCB. Leadframe (Copper Alloy) IC (Silicon) Mold Compound (Plastic) Die Attach (Epoxy) Leadframe Die Pad Exposed at Base of the Package (Copper Alloy) Figure 9. Section View of a PowerPAD Package 4. It is recommended, but not required, to place a small number of additional holes under the package and outside the thermal pad area. These holes provide additional heat paths between the copper thermal land and the ground plane. They may be larger because they are not in the area to be soldered, so wicking is not a problem. This is illustrated in Figure 10. 5. Connect all holes, including those within the thermal pad area and outside the pad area, to the internal ground plane or other internal copper plane for single-supply applications, and to V− for split-supply applications. 6. When laying out these holes, do not use the typical web or spoke via connection methodology, as shown in Figure 11. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes soldering the vias that have ground plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. PowerPAD ASSEMBLY PROCESS 1. The PowerPAD must be connected to the device’s most negative supply voltage, which will be ground in single-supply applications, and V− in split-supply applications. 2. Prepare the PCB with a top-side etch pattern, as shown in Figure 10. The exact land design may vary based on the specific assembly process requirements. There should be etch for the leads as well as etch for the thermal land. Solid Via RECOMMENDED Web or Spoke Via NOT RECOMMENDED (due to poor heat conduction) Figure 11. Via Connection Thermal Land (Copper) Minimum Size 4.8mm x 3.8mm (189 mils x 150 mils) OPTIONAL: Additional 4 vias outside of thermal pad area but under the package. REQUIRED: Thermal pad area 2.286mm x 2.286mm (90 mils x 90 mils) with 5 vias (via diameter = 13 mils) Figure 10. 8-Pin PowerPAD PCB Etch and Via Pattern 3. Place the recommended number of plated-through holes (or thermal vias) in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept small so that solder wicking through the holes is not a problem during reflow. The minimum recommended number of holes for the SO-8 PowerPAD package is 5, as shown in Figure 10. 16 7. The top-side solder mask should leave the pad connections and the thermal pad area exposed. The thermal pad area should leave the 13 mil holes exposed. The larger holes outside the thermal pad area may be covered with solder mask. 8. Apply solder paste to the exposed thermal pad area and all of the package terminals. 9. With these preparatory steps in place, the PowerPAD IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For detailed information on the PowerPAD package including thermal modeling considerations and repair procedures, please see Technical Brief SLMA002, PowerPAD Thermally Enhanced Package, located at www.ti.com. PACKAGE OPTION ADDENDUM www.ti.com 21-May-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY OPA2354AIDDA ACTIVE HSOP DDA 8 100 OPA2354AIDDAR ACTIVE HSOP DDA 8 2500 OPA2354AIDGKR ACTIVE VSSOP DGK 8 2500 OPA2354AIDGKT ACTIVE VSSOP DGK 8 250 OPA354AIDBVR ACTIVE SOP DBV 5 3000 OPA354AIDBVT ACTIVE SOP DBV 5 250 OPA354AIDDA ACTIVE HSOP DDA 8 100 OPA354AIDDAR ACTIVE HSOP DDA 8 2500 OPA4354AID ACTIVE SOIC D 14 58 OPA4354AIDR ACTIVE SOIC D 14 2500 OPA4354AIPWR ACTIVE TSSOP PW 14 2500 OPA4354AIPWT ACTIVE TSSOP PW 14 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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