TI THS3120ID

THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
LOW-NOISE, HIGH-OUTPUT DRIVE, CURRENT-FEEDBACK,
OPERATIONAL AMPLIFIERS
FEATURES
•
•
•
•
•
•
DESCRIPTION
Low Noise
– 1 pA/√Hz Noninverting Current Noise
– 10 pA/√Hz Inverting Current Noise
– 2.5 nV/√Hz Voltage Noise
High Output Current Drive: 475 mA
High Slew Rate: 1700 V/µs (RL = 50 Ω,
VO = 8 VPP)
Wide Bandwidth: 120 MHz (G = 2, RL = 50 Ω)
Wide Supply Range: ±5 V to ±15 V
Power-Down Feature: (THS3120 Only)
The THS3120 and THS3121 are low-noise,
high-voltage, high output current drive, currentfeedback amplifiers designed to operate over a wide
supply range of ±5 V to ±15 V for today's high
performance applications.
The THS3120 offers a power saving mode by providing a power-down pin for reducing the 7-mA quiescent current of the device, when the device is not
active.
These
amplifiers
provide
well-regulated
ac
performance characteristics. Most notably, the 0.1-dB
flat bandwidth is exceedingly high, reaching beyond
90 MHz. The unity gain bandwidth of 130 MHz allows
for good distortion characteristics at 10 MHz. Coupled
with high 1700-V/µs slew rate, the THS3120 and
THS3121 amplifiers allow for high output voltage
swings at high frequencies.
APPLICATIONS
•
•
•
•
Video Distribution
Power FET Driver
Pin Driver
Capacitive Load Driver
The THS3120 and THS3121 are offered in a 8-pin
SOIC (D), and the 8-pin MSOP (DGN) packages with
PowerPAD™.
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.07
0.05
0.04
Differential Phase − deg
0.06
Differential Gain − %
0.14
Gain = 2,
RF = 649 Ω,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
PAL
0.03
NTSC
0.02
0.01
VIDEO DISTRIBUTION AMPLIFIER APPLICATION
Gain = 2,
RF = 649 Ω,
0.12 VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
0.1
0.08
649 Ω
649 Ω
15 V
PAL
−
+
VI
NTSC
0.06
75-Ω Transmission Line
75 Ω
−15 V
75 Ω
0.04
VO(1)
n Lines
75 Ω
VO(n)
75 Ω
0.02
0
0
1
2
3
4
5
6
7
8
0
0
Number of 150 Ω Loads
1
2
3
4
5
6
Number of 150 Ω Loads
7
8
75 Ω
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling procedures and installation procedures can cause damage.
TOP VIEW
D, DGN
TOP VIEW
THS3120
REF
VIN−
VIN+
VS−
1
8
2
7
3
6
4
5
D, DGN
THS3121
PD
VS+
VOUT
NC
NC
VIN −
VIN +
VS−
NC = No Internal Connection
1
8
2
7
3
6
4
5
NC
VS+
VOUT
NC
NC = No Internal Connection
Note: The device with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin
functional range is from VS− to (VS+ − 4 V).
AVAILABLE OPTIONS
TA
PACKAGED DEVICE
PLASTIC SMALL OUTLINE SOIC (D)
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
(1)
(2)
PLASTIC MSOP (DGN) (1) (2)
THS3120CD
THS3120CDGN
THS3120CDR
THS3120CDGNR
THS3120ID
THS3120IDGN
THS3120IDR
THS3120IDGNR
THS3121CD
THS3121CDGN
THS3121CDR
THS3121CDGNR
THS3121ID
THS3121IDGN
THS3121IDR
THS3121IDGNR
SYMBOL
AQA
APN
AQO
APO
Available in tape and reel. The R suffix standard quantity is 2500 (e.g. THS3120CDGNR).
The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATING TABLE
PACKAGE
(1)
(2)
2
ΘJC (°C/W)
D-8 (1)
38.3
DGN-8 (2)
4.7
POWER RATING
TJ = 125°C
ΘJA (°C/W)
TA = 25°C
TA = 85°C
95
1.05 W
421 mW
58.4
1.71 W
685 W
This data was taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the ΘJA is 95°C/W with
power rating at TA = 25°C of 1.05 W.
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 inch x 3 inch PCB. For further information, refer to
the Application Information section of this data sheet.
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage
NOM
MAX
Dual supply
±5
±15
Single supply
10
30
V
0
70
Industrial
-40
85
Operating junction temperature, continuous operating, TJ
-40
125
°C
Normal storage temperature, Tstg
-40
85
°C
Operating free-air temperature, TA
Commercial
UNIT
°C
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
UNIT
Supply voltage, VS- to VS+
33 V
Input voltage, VI
± VS
Differential input voltage, VID
±4V
Output current, IO (2)
550 mA
Continuous power dissipation
See Dissipation Ratings Table
Maximum junction temperature, TJ (3)
150°C
Maximum junction temperature, continuous operation, long term reliability, TJ
Operating free-air temperature, TA
Storage temperature, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(4)
Commercial
Industrial
125°C
0°C to 70°C
-40°C to 85°C
-65°C to 125°C
300°C
ESD ratings:
(1)
(2)
(3)
(4)
HBM
1000
CDM
1500
MM
200
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The THS3120 and THS3121 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
3
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 649 Ω,RL = 50 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
-40°C to
85°C
UNIT
MIN/TYP/
MAX
MHz
TYP
V/µs
TYP
AC PERFORMANCE
G = 1, RF = 806 Ω, VO = 200 mVPP
130
G = 2, RF = 649 Ω, VO = 200 mVPP
120
G = 5, RF = 499 Ω, VO = 200 mVPP
105
G = 10, RF = 301 Ω, VO = 200 mVPP
66
0.1 dB bandwidth flatness
G = 2, RF = 649 Ω, VO = 200 mVPP
90
Large-signal bandwidth
G = 5, RF = 499 Ω , VO = 2 VPP
Small-signal bandwidth, -3 dB
80
G = 1, VO = 4-V step, RF = 806 Ω
1500
G = 2, VO = 8-V step, RF = 649 Ω
1700
Slew rate
Recommended maximum SR for
repetitive signals (1)
900
V/µs
MAX
Rise and fall time
G = -5, VO = 10-V step, RF = 499Ω
10
ns
TYP
Settling time to 0.1%
G = -2, VO = 2 VPP step
11
Settling time to 0.01%
G = -2, VO = 2 VPP step
52
ns
TYP
dBc
TYP
Slew rate (25% to 75% level)
Harmonic distortion
2nd Harmonic distortion
RL = 50 Ω
51
RL = 499 Ω
53
RL = 50 Ω
50
3rd Harmonic distortion
G = 2,
RF = 649 Ω,
VO = 2 VPP,
f = 10 MHz
Input voltage noise
f > 20 kHz
2.5
nV / √Hz
TYP
Noninverting input current noise
f > 20 kHz
1
pA / √Hz
TYP
Inverting input current noise
f > 20 kHz
10
pA / √Hz
TYP
Differential gain
Differential phase
G = 2,
RL = 150 Ω,
RF = 649 Ω
RL = 499 Ω
65
NTSC
0.007%
PAL
0.007%
NTSC
0.018°
PAL
0.022°
TYP
DC PERFORMANCE
Transimpedance
Input offset voltage
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
Average offset current drift
VO = ±3.75 V, Gain = 1
VCM = 0 V
VCM = 0 V
VCM = 0 V
VCM = 0 V
1.9
1.3
1
1
MΩ
MIN
2
6
8
8
mV
MAX
±10
±10
µV/°C
TYP
MAX
1
4
3
15
4
15
6
6
µA
±10
±10
nA/°C
TYP
20
20
µA
MAX
±10
±10
nA/°C
TYP
20
20
µA
MAX
±30
±30
nA/°C
TYP
MIN
INPUT CHARACTERISTICS
Input common-mode voltage range
Common-mode rejection ratio
VCM = ±12.5 V
±13.3
±13
±12.8
±12.8
V
70
63
60
60
dB
MIN
Noninverting input resistance
41
MΩ
TYP
Noninverting input capacitance
0.4
pF
TYP
V
MIN
MIN
OUTPUT CHARACTERISTICS
RL = 1 kΩ
±14
±13.5
±13
±13
RL = 50 Ω
±13.5
±12.5
±12
±12
Output current (sourcing)
RL = 25 Ω
475
425
400
400
mA
Output current (sinking)
RL = 25 Ω
490
425
400
400
mA
MIN
Output impedance
f = 1 MHz, Closed loop
0.04
Ω
TYP
Output voltage swing
(1)
4
For more information, see the Application Information section of this data sheet.
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
VS = ±15 V, RF = 649 Ω,RL = 50 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
Specified operating voltage
±15
±16
±16
Maximum quiescent current
7
8.5
11
Minimum quiescent current
7
5.5
-40°C to
85°C
UNIT
MIN/TYP/
MAX
±16
V
MAX
11
mA
MAX
4
4
mA
MIN
POWER SUPPLY
Power supply rejection (+PSRR)
VS+ = 15.5 V to 14.5 V, VS- = 15 V
83
75
70
70
dB
MIN
Power supply rejection (-PSRR)
VS+ = 15 V, VS- = -15.5 V to -14.5 V
78
70
65
65
dB
MIN
V
MAX
µA
MAX
µA
TYP
µs
TYP
kΩ || pF
TYP
POWER-DOWN CHARACTERISTICS
Power-down voltage level
Enable, REF = 0 V
≤ 0.8
Power-down , REF = 0 V
≥2
PD = 0V
300
VPD = 0 V, REF = 0 V,
11
VPD = 3.3 V, REF = 0 V
11
Turnon time delay
90% of final value
4
Turnoff time delay
10% of final value
6
Power-down quiescent current
VPD quiescent current
Input impedance
3.4 || 1.7
450
500
500
5
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
VS = ±5 V, RF = 750 Ω, RL = 50 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
-40°C to
85°C
UNIT
MIN/TYP/
MAX
MHz
TYP
V/µs
TYP
AC PERFORMANCE
G = 1, RF = 909 Ω, VO = 200 mVPP
105
G = 2, RF = 750 Ω, VO = 200 mVPP
100
G = 5, RF = 499 Ω, VO = 200 mVPP
95
G = 10, RF = 301 Ω, VO = 200 mVPP
70
0.1 dB bandwidth flatness
G = 2, RF = 750 Ω, VO = 200 mVPP
70
Large-signal bandwidth
G = 2, RF = 750 Ω , VO = 2 VPP
85
G = 1, VO= 2-V step, RF = 909 Ω
560
G = 2, VO= 2-V step, RF = 750 Ω
620
Slew rate
Recommended maximum SR for
repetitive signals (1)
900
V/µs
MAX
Rise and fall time
G = -5, VO = 5-V step, RF = 499Ω
10
ns
TYP
Settling time to 0.1%
G = -2, VO = 2 VPP step
7
Settling time to 0.01%
G = -2, VO = 2 VPP step
42
ns
TYP
dBc
TYP
Small-signal bandwidth, -3 dB
Slew rate (25% to 75% level)
Harmonic distortion
2nd Harmonic distortion
RL = 50Ω
51
RL = 499 Ω
53
RL = 50Ω
48
3rd Harmonic distortion
G = 2,
RF = 649 Ω,
VO = 2 VPP,
f = 10 MHz
Input voltage noise
f > 20 kHz
2.5
nV / √Hz
TYP
Noninverting input current noise
f > 20 kHz
1
pA / √Hz
TYP
Inverting input current noise
f > 20 kHz
10
pA / √Hz
TYP
Differential gain
Differential phase
G = 2,
RL = 150 Ω,
RF = 806 Ω
RL = 499 Ω
60
NTSC
0.008%
PAL
0.008%
NTSC
0.014°
PAL
0.018°
TYP
DC PERFORMANCE
Transimpedance
Input offset voltage
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
Average offset current drift
VO = ±1.25 V, Gain = 1
VCM = 0 V
VCM = 0 V
VCM = 0 V
VCM = 0 V
1.2
0.9
0.7
0.7
MΩ
MIN
3
6
8
8
mV
MAX
±10
±10
µV/°C
TYP
MAX
1
4
2
15
2
15
6
6
µA
±10
±10
nA/°C
TYP
20
20
µA
MAX
±10
±10
nA/°C
TYP
20
20
µA
MAX
±30
±30
nA/°C
TYP
MIN
INPUT CHARACTERISTICS
Input common-mode voltage range
Common-mode rejection ratio
VCM = ±2.5 V
±3.2
±2.9
±2.8
±2.8
V
66
62
58
58
dB
MIN
Noninverting input resistance
35
MΩ
TYP
Noninverting input capacitance
0.5
pF
TYP
V
MIN
MIN
OUTPUT CHARACTERISTICS
RL = 1 kΩ
±4
±3.8
±3.7
±3.7
RL = 50 Ω
±3.9
±3.7
±3.6
±3.6
Output current (sourcing)
RL = 10 Ω
310
250
200
200
mA
Output current (sinking)
RL = 10 Ω
325
250
200
200
mA
MIN
Output impedance
f = 1 MHz
0.05
Ω
TYP
Output voltage swing
(1)
6
For more information, see the Application Information section of this data sheet.
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V, RF = 750 Ω, RL = 50 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
-40°C to
85°C
Specified operating voltage
±5
±4.5
±4.5
±4.5
V
MIN
Maximum quiescent current
6.5
8
10
10
mA
MAX
UNIT
MIN/TYP/
MAX
POWER SUPPLY
Minimum quiescent current
6.5
4
3.5
3.5
mA
MIN
Power supply rejection (+PSRR)
VS+ = 5.5 V to 4.5 V,
VS- = 5 V
80
72
67
67
dB
MIN
Power supply rejection (-PSRR)
VS+ = 5 V,
VS- = -5.5 V to -4.5 V
75
67
62
62
dB
MIN
V
MAX
µA
MAX
µA
TYP
µs
TYP
kΩ || pF
TYP
POWER-DOWN CHARACTERISTICS
Enable, REF = 0 V
≤ 0.8
Power-down , REF = 0 V
≥ 0.2
PD = 0 V
200
VPD = 0 V, REF = 0 V,
11
VPD = 3.3 V, REF = 0 V
11
Turnon time delay
90% of final value
4
Turnoff time delay
10% of final value
6
Power-down voltage level
Power-down quiescent current
VPD quiescent current
Input impedance
3.4 || 1.7
450
500
500
7
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
±15-V graphs
Noninverting small signal gain frequency response
1, 2
Inverting small signal gain frequency response
3
0.1 dB flatness
4
Noninverting large signal gain frequency response
5
Inverting large signal gain frequency response
6
Frequency response capacitive load
7
Recommended RISO
vs Capacitive load
8
2nd Harmonic distortion
vs Frequency
9
3rd Harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage swing
11, 12
Slew rate
vs Output voltage step
13, 14
Noise
vs Frequency
Settling time
10
15
16, 17
Quiescent current
vs Supply voltage
18
Output voltage
vs Load resistance
19
Input bias and offset current
vs Case temperature
20
Input offset voltage
vs Case temperature
21
Transimpedance
vs Frequency
22
Rejection ratio
vs Frequency
23
Noninverting small signal transient response
24
Inverting large signal transient response
25
Overdrive recovery time
26
Differential gain
vs Number of loads
27
Differential phase
vs Number of loads
28
Closed loop output impedance
vs Frequency
29
Power-down quiescent current
vs Supply voltage
30
Turnon and turnoff time delay
31
±5-V graphs
Noninverting small signal gain frequency response
32
Inverting small signal gain frequency response
33
0.1 dB flatness
34
Slew rate
vs Output voltage step
2nd Harmonic distortion
vs Frequency
3rd Harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage swing
Noninverting small signal transient response
43
44
Settling time
8
38
39, 40
42
vs Case temperature
Overdrive recovery time
Rejection ratio
37
41
Inverting small signal transient response
Input bias and offset current
35, 36
45
vs Frequency
46
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V)
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
9
RF = 475 Ω
RF = 649 Ω
7
Noninverting Gain − dB
6
5
RF = 750 Ω
4
3
Gain = 2,
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
1
18
16
14
12
G = 5, RF = 499 Ω
10 M
100 M
G = 2, RF = 649 Ω
8
6
4
2
1G
100 k
16
G = 5, RF = 499 Ω
14
1M
10 M
10
8
G = 2, RF = 681 Ω
6
4
RL = 50 Ω,
VO = 2 VPP,
VS = ±15 V
1M
10
8
G =-1, RF = 681 Ω
6
4
2
RL = 50 Ω,
VO = 2 VPP,
VS = ±15 V
0
-2
10 M
100 M
-4
1G
1M
10 M
100 M
1G
f - Frequency - Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
FREQUENCY RESPONSE
CAPACITIVE LOAD
RECOMMENDED RISO
vs
CAPACITIVE LOAD
2nd HARMONIC DISTORTION
vs
FREQUENCY
12
R(ISO) = 40.2 Ω
CL = 22 pF
R(ISO) = 30 Ω
CL = 47 pF
R(ISO) = 20 Ω
CL = 100 pF
Gain = 5,
RL = 50 Ω
VS = ±15 V
f - Frequency - Hz
60
Recommended R ISO Resistance − Ω
R(ISO) = 49.9 Ω CL = 10 pF
4
1G
G = -5, RF = 499 Ω
14
12
0
100 k
100 M
14
6
100 M
12
5.7
8
10 M
f - Frequency - Hz
INVERTING LARGE SIGNAL
FREQUENCY RESPONSE
2
10
1M
NONINVERTING LARGE SIGNAL
FREQUENCY RESPONSE
5.9
16
100 k
0.1 dB FLATNESS
6
100 k
G = -1, RF = 681 Ω
Figure 3.
Noninverting Gain − dB
Noninverting Gain - dB
1G
G = -2, RF = 681 Ω
Figure 2.
5.8
Signal Gain - dB
100 M
0
-2
-4
16
6.1
8
6
4
2
Figure 1.
Gain = 2,
RF = 562 Ω,
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
6.2
-2
10 M
G = -5, RF = 499 Ω
10
f − Frequency − Hz
6.3
0
1M
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
G = -10, RF = 365 Ω
18
16
14
12
G = 1, RF = 806 Ω
f − Frequency − Hz
2
24
22
20
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
10
0
−2
−4
0
1M
G = 10, RF = 301 Ω
Inverting Gain - dB
2
24
22
20
-30
Gain = 5,
RL = 50 Ω,
VS = ±15 V
50
2 nd Harmonic Distortion - dBc
Noninverting Gain − dB
8
INVERTING SMALL SIGNAL
FREQUENCY RESPONSE
Inverting Gain - dB
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
40
30
20
10
0
10 M
100 M
Capacitive Load - Hz
Figure 7.
10
100
CL − Capacitive Load − pF
Figure 8.
-40
VO = 2 VPP,
RL = 50 Ω,
VS = ±15 V
G = 5,
RF = 499 Ω
-50
G = 2,
RF = 649 Ω
-60
-70
-80
G = 2, RF = 649 Ω,
RL = 499 Ω
-90
-100
100 k
1M
10 M
100 M
f - Frequency - Hz
Figure 9.
9
THS3120, THS3121
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SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V) (continued)
3rd HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
-50
-60
G = 2,
RF = 649 Ω
-70
-80
G = 2,
RF = 649 Ω,
RL = 499 Ω
-90
HD3, RL = 50Ω
-80
10 M
1M
f - Frequency - Hz
HD2, RL = 499Ω
-90
-95
100 M
1
2
3
4
5
6
7
8
9
0
10
1
2
3
4
5
6
7
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
NOISE
vs
FREQUENCY
600
1400
1000
600
400
200
0
0
3.5 4
1
2
3
Figure 13.
SETTLING TIME
Rising Edge
1
VO − Output Voltage − V
0.75
0.5
Gain = −2
RL = 50 Ω
RF = 499 Ω
VS = ±15 V
0.25
0
−0.25
−0.5
−0.75
Falling Edge
−1
−1.25
2
4
6
8
10
t − Time − ns
Figure 16.
12
Vn
4
5
6
7
8
9
10
0.1
VO − Output Voltage −VPP
VO − Output Voltage −VPP
1.25
10
In+
0
4.5 5
14
16
10
In-
1
0.01
1
Figure 14.
Figure 15.
SETTLING TIME
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
−4.5
10
Gain = −2
RL = 50 Ω
RF = 499 Ω
VS = ±15 V
Falling Edge
4
6
8
10
12
14 16
TA = 25 °C
8
7
TA = -40 °C
6
5
4
3
2
1
0
2
100
TA = 85 °C
9
Rising Edge
0
10
f - Frequency - kHz
I Q - Quiescent Current - mA
2.5 3
Fall
800
200
1.5 2
Rise
1200
400
0.5 1
Hz
1600
V n - Voltage Noise - nV/
Fall
800
9
100
Gain = 2
RL = 50 Ω
RF = 649 Ω
VS = ±15 V
1800
1000
8
VO - Output Voltage Swing - VPP
Figure 12.
Rise
0
Gain = 2,
RF = 649 Ω,
f = 8 MHz
VS = ±15 V
-80
Figure 11.
1200
0
HD2, RL = 499Ω
Figure 10.
SR − Slew Rate − V/ µ s
1400
HD3, RL = 50 Ω
-70
-90
2000
1600
-60
VO - Output Voltage Swing - VPP
Gain = 1
RL = 50 Ω
RF = 806 Ω
VS = ±15 V
1800
HD2, RL = 50 Ω
-50
HD3, RL = 499Ω
HD3, RL = 499Ω
0
2000
VO − Output Voltage − V
Gain = 2,
RF = 649 Ω,
f= 1 MHz
VS = ±15 V
-85
-100
100 k
Harmonic Distortion - dBc
-75
G = 5,
RF = 499 Ω
I n - Current Noise - pA/ Hz
-40
HD2, RL = 50Ω
Harmonic Distortion - dBc
3rd Harmonic Distortion - dBc
VO = 2 VPP,
RL = 50 Ω,
VS = ±15 V
-100
SR − Slew Rate − V/ µ s
-40
-70
-30
10
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
2
3
4
5 6
7
8
9
10 11 12 13 14 15
t − Time − ns
VS - Supply Voltage - ±V
Figure 17.
#IMPLIED #IMPLIED.
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V) (continued)
INPUT BIAS AND
OFFSET CURRENT
vs
CASE TEMPERATURE
16
14
12
10
8
6
4
2
0
−2
−4
−6
−8
−10
−12
−14
−16
VOS − Input Offset Voltage − mV
IIB−
3
2.5
VS = ±15 V
TA = −40 to 85°C
2
IOS
1.5
1
IIB+
0.5
100
Figure 19.
Figure 20.
TRANSIMPEDANCE
vs
FREQUENCY
REJECTION RATIO
vs
FREQUENCY
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
0.3
VS = ±15 V
CMRR
0.25
60
40
30
VO - Output Voltage - V
VS = ±5 V
PSRR−
40
30
20
PSRR+
20
0
0
1M
10 M
100 M
1G
0.1
Input
0.05
0
-0.05
-0.1
Gain = 2,
RL = 50 Ω,
RF = 649 Ω,
VS = ±15 V
-0.15
100 k
1M
10 M
-0.25
-0.3
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
100 M
t - Time - µs
f - Frequency - Hz
f − Frequency − Hz
Figure 21.
Figure 22.
Figure 23.
OVERDRIVE RECOVERY TIME
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
20
Output
10
Output Voltage - V
3
2
1
Input
-1
-2
Gain = -5,
RL = 50 Ω,
RF = 499 Ω,
VS = ±15 V
-5
-6
0.04 0.05 0.06 0.07 0.08 0.09 0.1
t - Time - µs
Figure 24.
3
0.05
Gain = 2,
RF = 649 Ω,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
0.04
PAL
0.06
2
5
1
0
0
0.03
-5
-1
-10
-2
-15
-3
0.01
-4
1
0
-20
0.11 0.12
0.07
4
Gain = 2,
RF = 648 Ω,
VS = ±15 V
15
Differential Gain − %
5
VI - Input Voltage - V
6
-4
0.15
-0.2
10
10
Output
0.2
50
Rejection Ratio − dB
VS = ±15 V
50
-3
1
Figure 18.
70
0
2
TC − Case Temperature − °C
80
4
VS = ±5 V
3
TC − Case Temperature − °C
70
100 k
VS = ±15 V
4
RL − Load Resistance − Ω
90
60
5
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1000
100
Transimpedance Gain - dB ohms
6
VS = ±15 V
10
VO - Output Voltage - V
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
4
3.5
I IB − Input Bias Current − µ A
I OS − Input Offset Current − µ A
VO − Output Voltage − V
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
0
0.2
0.4
0.6
0.8
t - Time - µs
Figure 25.
NTSC
0.02
0
1
2
3
4
5
6
7
8
Number of 150 Ω Loads
Figure 26.
11
THS3120, THS3121
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SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V) (continued)
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
Gain = 2,
RF = 649 Ω,
0.12 VS = ±15 V,
40 IRE - NTSC and PAL,
Worst Case ±100 IRE Ramp
0.1
0.08
PAL
NTSC
0.06
0.04
0.02
0
0
1
2
3
4
5
6
7
400
100
Gain = 2,
RF = 649 Ω,
VS = ±15 V
Powerdown Quiescent Current − µ A
ZO − Closed-Loop Output Impedance − Ω
Differential Phase - °
0.14
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
10
1
0.1
1M
10 M
Number of 150 Ω Loads
100 M
1G
#IMPLIED #IMPLIED.
TA = −40°C
200
TA = 25°C
150
100
50
1.5
1
0
−0.5
Powerdown Pulse
6
5
4
3
Gain = 5,
VI = 0.1 Vdc
RL = 50 Ω
VS = ±15 V and ±5 V
0
0.1 0.2
0.3
2
1
0
−1
0.4 0.5 0.6 0.7
t − Time − ms
Figure 29.
PowerDown Pulse − V
Output Voltage
0.5
3
5
7
9
11
Figure 28.
TURNON AND TURNOFF
TIME DELAY
VO − Output Voltage Level − V
TA = 85°C
250
VS − Supply Voltage − ±V
f − Frequency − Hz
Figure 27.
12
300
0
0.01
8
350
13
15
THS3120, THS3121
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SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±5 V)
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
G = 5, RF = 499 Ω
14
12
10
G = 2, RF = 750 Ω
8
6
4
G = 1, RF = 909 Ω
2
0
−2
−4
10 M
100 M
G = -2, RF = 681 Ω
6
4
2
G = -1, RF = 750 Ω
1M
6.1
6
5.9
5.8
10 M
100 M
5.7
1G
1M
10 M
100 M
f − Frequency − Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 30.
Figure 31.
Figure 32.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
2nd HARMONIC DISTORTION
vs
FREQUENCY
700
Gain = 1
RL = 50 Ω
RF = 909 Ω
VS = ±5 V
-30
Rise
Rise
500
Fall
400
300
200
500
Fall
400
300
200
Gain = 2
RL = 50 Ω
RF = 750 Ω
VS = ±5 V
100
100
0
0
0
1
2
3
4
2nd Harmonic Destortion - dBc
600
SR − Slew Rate − V/µ s
-40
G = -5, RF = 499 Ω
-50
-60
G = -2, RF = 649 Ω
-70
-80
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
-90
-100
0
5
1
2
3
4
5
6
7
100 k
1M
10 M
100 M
VO − Output Voltage −VPP
VO − Output Voltage −VPP
Figure 33.
Figure 34.
Figure 35.
3rd HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
-70
-30
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
f - Frequency - Hz
-40
HD3, RL = 50Ω
HD3, RL = 50Ω
HD3, RL = 50Ω
Harmonic Distortion - dBc
-75
-50
G = -5, RF = 499 Ω
-60
-70
-80
G = -2, RF = 649 Ω
-80
HD2, RL = 499Ω
-85
HD3, RL = 499Ω
-90
Gain = 2,
RF = 649 Ω
f= 1 MHz
VS = ±5 V
-95
-90
Harmonic Distortion - dBc
600
SR − Slew Rate − V/ µ s
G = -5, RF = 499 Ω
10
8
Gain = 2,
RF = 750 Ω,
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±5 V
6.2
14
12
1G
700
3rd Harmonic Distortion - dBc
0.1 dB FLATNESS
6.3
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±5 V
G = -10, RF = 365 Ω
0
-2
-4
1M
-40
24
22
20
18
16
Noninverting Gain - dB
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±5 V
G = 10, RF = 301 Ω
22
20
18
16
Inverting Gain - dB
Noninverting Gain − dB
24
INVERTING SMALL SIGNAL
FREQUENCY RESPONSE
100 k
1M
10 M
100 M
-50
-60
-70
HD2, RL = 499Ω
Gain = 2,
RF = 649 Ω
f= 8 MHz
VS = ±5 V
-80
HD3, RL = 499Ω
-100
-100
HD3, RL = 50Ω
-90
0
0.5
1
1.5
2
2.5
3
3.5
4 4.5
5
0
0.5 1
1.5 2
2.5
3
3.5 4
4.5
f - Frequency - Hz
VO - Output Voltage Swing - VPP
VO - Output Voltage Swing - VPP
Figure 36.
Figure 37.
Figure 38.
5
13
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SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±5 V) (continued)
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
Output
VO - Output Voltage - V
Input
0.05
0
-0.05
-0.1
Gain = 2
RL = 50 Ω
RF = 750 Ω
VS = ±5 V
-0.15
-0.2
-0.25
10
20
30
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
Input
Gain = -5,
RL = 50 Ω,
RF = 499 Ω,
VS = ±5 V
-2.5
-3
-3.5
-0.3
0
VS = ±5 V
Output
40
50
60
70
0
OVERDRIVE RECOVERY TIME
1
VO - Output Voltage - V
1
0.6
0.75
2
0.4
1
0.2
0
0
-1
-0.2
-2
-0.4
-3
-0.6
-4
-0.8
-5
-1
0.4
0.6
t - Time - µs
Figure 42.
14
0.8
1
IIB+
0.75
0.5
IOS
30
40
50
60
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
70
TC − Case Temperature − °C
0.8
1
Figure 40.
Figure 41.
SETTLING TIME
REJECTION RATIO
vs
FREQUENCY
70
VS = ±5 V
60
VO − Output Voltage − V
Gain = 2,
RF = 750 Ω,
VS = ±5 V
0.2
10 20
1.25
VI - Input Voltage - V
5
0
IIB−
1.25
t - Time - µs
Figure 39.
3
1.5
0
t - Time - ns
4
1.75
0.25
Rising Edge
0.5
0.25
Gain = −2
RL = 50 Ω
RF = 681 Ω
VS = ±5 V
0
−0.25
−0.5
Rejection Ratio − dB
VO - Output Voltage - V
0.15
0.1
2
3.5
3
2.5
I IB − Input Bias Current − µ A
I OS − Input Offset Current − µ A
0.3
0.25
0.2
INPUT BIAS AND
OFFSET CURRENT
vs
CASE TEMPERATURE
50
40
PSRR−
30
CMRR
20
−0.75
Falling Edge
−1
−1.25
0
2
4
6 8 10 12 14 16 18 20 22 24 26
PSRR+
10
0
100 k
1M
10 M
t − Time − ns
f − Frequency − Hz
Figure 43.
Figure 44.
100 M
THS3120, THS3121
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SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
APPLICATION INFORMATION
Maximum Slew Rate for Repetitive Signals
The THS3120 and THS3121 are recommended for
high slew rate pulsed applications where the internal
nodes of the amplifier have time to stabilize between
pulses. It is recommended to have at least 20-ns
delay between pulses.
The THS3120 and THS3121 are not recommended
for applications with repetitive signals (sine, square,
sawtooth, or other) that exceed 900 V/µs. Using the
part in these applications results in excessive current
draw from the power supply and possible device
damage.
For applications with high slew rate, repetitive signals,
the THS3091 and THS3095 (single), or THS3092 and
THS3096 (dual) are recommended.
WIDEBAND, NONINVERTING OPERATION
The THS3120 and THS3121 are unity gain stable
130-MHz current-feedback operational amplifiers, designed to operate from a ±5-V to ±15-V power supply.
Figure 45 shows the THS3121 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment presenting a 50-Ω load impedance.
15 V
+VS
+
0.1 µF
50 Ω Source
+
VI
Table 1. Recommended Resistor Values for
Optimum Frequency Response
THS3120 and THS3121 RF and RG values for minimal peaking
with RL = 50 Ω
GAIN (V/V)
1
2
SUPPLY VOLTAGE
(V)
RG (Ω)
RF (Ω)
±15
--
806
±5
--
909
±15
649
649
±5
750
750
±15
124
499
±5
124
499
±15
33.2
301
±5
33.2
301
±15
681
681
±5
750
750
-2
±15 and ±5
340
681
-5
±15 and ±5
100
499
-10
±15 and ±5
36.5
365
5
10
-1
49.9 Ω
THS3120
49.9 Ω
_
50 Ω LOAD
RF
649 Ω
6.8 µF
Current-feedback amplifiers are highly dependent on
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain setting
resistors RF and RG at different gains to give maximum bandwidth with minimal peaking in the frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
649 Ω
RG
0.1 µF
6.8 µF
+
-VS
-15 V
Figure 45. Wideband, Noninverting Gain
Configuration
15
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SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
WIDEBAND, INVERTING OPERATION
+VS
Figure 46 shows the THS3121 in a typical inverting
gain configuration where the input and output impedances and signal gain from Figure 45 are retained
in an inverting circuit configuration.
50 Ω Source
+
VI
15 V +VS
+
THS3120
50 Ω Source
VI
50 Ω LOAD
649 Ω
RG
649 Ω
+VS
2
RF
50 Ω LOAD
RG
RF
340 Ω
RM
59 Ω
681 Ω
VS
50 Ω Source
0.1 µF
6.8 µF
340 Ω
RT
59 Ω
681 Ω
_
49.9 Ω
THS3120
+
50 Ω LOAD
+VS
2
+VS
2
-VS
Figure 46. Wideband, Inverting Gain
Configuration
RG
VI
+
-15 V
_
RF
6.8 µF
49.9 Ω
_
49.9 Ω
+VS
2
+
0.1 µF
49.9 Ω
RT
THS3120
Figure 47. DC-Coupled, Single-Supply Operation
Video Distribution
SINGLE SUPPLY OPERATION
The THS3120 and THS3121 have the capability to
operate from a single supply voltage ranging from
10 V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits shown in Figure 47 shows inverting and
noninverting amplifiers configured for single supply
operations.
The wide bandwidth, high slew rate, and high output
drive current of the THS3120 and THS3121 matches
the demands for video distribution for delivering video
signals down multiple cables. To ensure high signal
quality with minimal degradation of performance, a
0.1-dB gain flatness should be at least 7x the
passband frequency to minimize group delay variations from the amplifier. A high slew rate minimizes
distortion of the video signal, and supports
component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality.
649 Ω
649 Ω
15 V
+
VI
75 Ω
75-Ω Transmission Line
-15 V
75 Ω
n Lines
VO(1)
75 Ω
VO(n)
75 Ω
75 Ω
Figure 48. Video Distribution Amplifier
Application
16
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SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
Driving Capacitive Loads
Applications, such as FET drivers and line drivers can
be highly capacitive and cause stability problems for
high-speed amplifiers.
Figure 49 through Figure 55 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier’s feedback path. See Figure 49 for
recommended resistor values versus capacitive load.
Recommended R ISO Resistance − Ω
60
Gain = 5,
RL = 50 Ω,
VS = ±15 V
50
40
30
20
10
0
10
100
CL − Capacitive Load − pF
Figure 49. Recommended RISO vs Capacitive Load
499 Ω
Using a ferrite chip in place of RISO, as shown in
Figure 51, is another approach of isolating the output
of the amplifier. The ferrite's impedance characteristic
versus frequency is useful to maintain the low frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to RISO, 20 Ω - 50 Ω, at 100 MHz and low impedance
at dc.
Figure 52 shows another method used to maintain
the low frequency load independence of the amplifier
while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback
is mainly from the load side of RISO. At high frequency, the feedback is mainly via the 27-pF capacitor. The resistor RIN in series with the negative input
is used to stabilize the amplifier and should be equal
to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 53 gives similar
results with reduced dc offset and low frequency
noise. (See the ADDITIONAL REFERENCE MATERIAL section for expanding the usability of current-feedback amplifiers.)
RF
VS
124 Ω
_
5.11 Ω
+
RISO
100 Ω LOAD
27 pF
499 Ω
RIN
1 µF
-VS
VS
Placing a small series resistor, RISO, between the
amplifier’s output and the capacitive load, as shown
in Figure 50, is an easy way of isolating the load
capacitance.
RG
49.9 Ω
124 Ω
750 Ω
VS
_
+
-VS
Figure 50.
VS
100 Ω LOAD
5.11 Ω
1 µF
49.9 Ω
499 Ω
124 Ω
Figure 52.
VS
Ferrite Bead
_
+
-VS
VS
1 µF
100 Ω LOAD
49.9 Ω
Figure 51.
17
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
RF
27 pF
VS
VS
499 Ω
5.11 Ω
+
_
FIN
RG
FB
124 Ω
-VS
VS
_
5.11 Ω
+
301 Ω
66.5 Ω
1 µF
-VS
VS
100 Ω LOAD
301 Ω
49.9 Ω
VS
_
Figure 53.
+
Figure 54 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load
faster as when driving large FET transistors.
499 Ω
VS
124 Ω
24.9 Ω
+
-VS
499 Ω
VS
VS
124 Ω
_
24.9 Ω
-VS
-VS
Figure 55. PowerFET Drive Circuit
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
The THS3120 features a power-down pin (PD) which
lowers the quiescent current from 7 mA down to 300
µA, ideal for reducing system power.
5.11 Ω
_
5.11 Ω
1 nF
5.11 Ω
+
-VS
Figure 54.
Figure 55 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
The power-down pin of the amplifier defaults to the
negative supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and are given in the specification tables. Below
the Enable Threshold Voltage, the device is on.
Above the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 56 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 1298 Ω. Figure 45 shows this circuit
configuration for reference.
18
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Powerdown Output Impedance − Ω
1400
Gain = 2
RF = 649 Ω
VS = ±15 V and ±5 V
1200
Achieving optimum performance with high frequency
amplifiers, like the THS3120 and THS3121, requires
careful attention to board layout parasitic and external
component types.
1000
800
600
400
200
0
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 56. Power-down Output Impedance vs
Frequency
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V-) of the amplifier. If this difference exceeds
±0.7 V, the output of the amplifier creates an output
voltage
equal
to
approximately
[(V+ - V-) -0.7 V]×Gain. This also implies that if a
voltage is applied to the output while in power-down
mode, the V- node voltage is equal to
VO(applied)× RG/(RF + RG). For low gain configurations
and a large applied voltage at the output, the amplifier may actually turn ON due to the aforementioned
behavior.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3120 also
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage level thresholds that apply to the power-down
pin. The usable range at the REF pin is from VS- to
(VS+ - 4 V).
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF and 100-pF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
• Careful selection and placement of external
components preserve the high frequency performance of the THS3120 and THS3121. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a
tighter overall layout. Again, keep their leads and
PC board trace length as short as possible.
Never use wirebound type resistors in a high
frequency application. Since the output pin and
inverting input pins are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed
close to the gain-setting resistors. Even with a
low parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values >
2.0 kΩ, this parasitic capacitance can add a pole
and/or a zero that can effect circuit operation.
Keep resistor values as low as possible, consistent with load driving considerations.
19
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
•
•
20
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS since the THS3120 and THS3121 are
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB
signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is not necessary
onboard, and in fact, a higher impedance environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance based on board material
and trace dimensions, a matching series resistor
into the trace from the output of the THS3120 /
THS3121 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high speed part like the THS3120
and THS3121 is not recommended. The additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely
troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the THS3120 / THS3121 parts directly
onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS3120 and THS3121 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 57(a) and Figure 57(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see Figure 57(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal performance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS312x have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 57. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 58. DGN PowerPAD PCB Etch and Via
Pattern
PowerPAD™ LAYOUT CONSIDERATIONS
1. PCB with a top side etch pattern as shown in
Figure 58. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3120 / THS3121 IC. These additional
vias may be larger than the 10-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered so that wicking is not a
problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as VS-,
is acceptable as there is no electrical connection
to the silicon.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. Therefore, the holes under the THS3120 / THS3121
PowerPAD package should make their connection to the internal ground plane with a complete
connection around the entire circumference of the
plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area
with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that
is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS3120 and THS3121 incorporates automatic
thermal shutoff protection. This protection circuitry
shuts down the amplifier if the junction temperature
exceeds approximately 160°C. When the junction
temperature reduces to approximately 140°C, the
amplifier turns on again. But, for maximum performance and reliability, the designer must take care to
ensure that the design does not exeed a junction
temperature of 125°C. Between 125°C and 150°C,
damage does not occur, but the performance of the
amplifier begins to degrade and long term reliability
suffers. The thermal characteristics of the device are
dictated by the package and the PC board. Maximum
power dissipation for a given package can be calculated using the following formula.
21
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
P Dmax T max T A
JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power dissipation,
but
also
dynamic
power
dissipation. Often times, this is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
θJC is the thermal coeffiecient from the silicon junctions to
the case (°C/W).
DESIGN TOOLS
θCA is the thermal coeffiecient from the case to ambient
air (°C/W).
Evaluation
Fixtures,
Application Support
For systems where heat dissipation is more critical,
the THS3120 and THS3121 are offered in an 8-pin
MSOP with PowerPAD package offering even better
thermal performance. The thermal coefficient for the
PowerPAD packages are substantially improved over
the traditional SOIC. Maximum power dissipation
levels are depicted in the graph for the available
packages. The data for the PowerPAD packages
assume a board layout that follows the PowerPAD
layout guidelines referenced above and detailed in
the PowerPAD application note (literature number
SLMA002). The following graph also illustrates the
effect of not soldering the PowerPAD to a PCB. The
thermal impedance increases substantially which may
cause serious heat and performance issues. Be sure
to always solder the PowerPAD to the PCB for
optimum performance.
PD − Maximum Power Dissipation − W
4
ΤJ = 125°C
3.5
3
θJA = 58.4°C/W
2.5
θJA = 95°C/W
2
1.5
1
0.5
θJA = 158°C/W
0
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x 3”
θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
θJA = 95°C/W for 8-Pin SOIC High−K Test PCB (D)
θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
Figure 59. Maximum Power Distribution vs
Ambient Temperature
22
Spice
Models,
and
Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal an evaluation board has
been developed for the THS3120 and THS3121
operational amplifier. The board is easy to use,
allowing for straightforward evaluation of the device.
The evaluation board can be ordered through the
Texas Instruments web site, www.ti.com, or through
your local Texas Instruments sales representative.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS3121 is available through the Texas
Instruments web site (www.ti.com). The PIC is also
available for design assistance and detailed product
information. These models do a good job of predicting small-signal ac and transient performance
under a wide variety of operating conditions. They are
not intended to model the distortion characteristics of
the amplifier, nor do they attempt to distinguish
between the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
J2
GND
J1
VS+
J7
VS−
FB2
FB1
VS+
+
C3
C5
NOTE: The Edge number for the THS3121 is
6445589.
TP2
C4
C2
C1
VS−
C6
+
PD
J7
R5
Z1
R6
0
R4
TP1
Vs+
R3
J5
Vin −
R8B
7
2 _
8
R1
R8A
6
3 +
1
4
R7A
R7B
Z2
J6
Vout
Vs −
J4
Vin+
R2
REF
J8
1
Figure 60. THS3120 EVM Circuit Configuration
Figure 62. THS3120 EVM Board Layout
(Bottom Layer)
THS3120DGN EVM
6445588
Figure 61. THS3120 EVM Board Layout
(Top Layer)
23
THS3120, THS3121
www.ti.com
SLOS420A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
Table 2. Bill of Materials
THS3120DGN and THS3121DGN EVM
(1)
(2)
ITEM
DESCRIPTION
SMD SIZE
REFERENCE
DESIGNATOR
PCB
QUANTITY
MANUFACTURER'S
PART NUMBER (1)
1
BeadD, Ferrite, 3 A, 80 Ω
1206
FB1, FB2
2
(Steward) HI1206N800R-00
2
Cap. 6.8 µF, Tanatalum, 35 V, 10%
D
C1, C2
2
(AVX) TAJD685K035R
3
Open
0805
R5, Z1
2
4
Cap. 0.1 µF, Ceramic, X7R, 50 V
0805
C3, C4
2
5
Cap. 100 pF, Ceramic, NPO, 100 V
0805
C5, C6
2
(AVX) 08051A101JAT2A
6
Resistor, 0 Ω, 1/8 W, 1%
0805
R6 (2)
1
(Phycomp) 9C08052A0R00JLHFT
7
Resistor, 124 Ω, 1/8 W, 1%
0805
R3
1
(Phycomp) 9C08052A1240FKHFT
8
Resistor, 499 Ω, 1/8 W, 1%
0806
R4
1
(Phycomp) 9C08052A4990FKHFT
9
Open
1206
R7A, Z2
2
10
Resistor, 49.9 Ω, 1/4 W, 1%
1206
R2, R8A
2
(Phycomp) 9C12063A49R9FKRFT
11
Resistor, 0 Ω, 1/4 W, 1%
1206
R1
1
(Phycomp) 9C12063A53R6FKRFT
12
Open
2512
R7B, R8B
2
13
Header, 0.1" CTRS, 0.025" SQ pins
3 Pos.
JP1 (2)
1
(Sullins) PZC36SAAN
14
Shunts
JP1 (2)
1
(Sullins) SSC02SYAN
15
Jack, banana receptance, 0.25" dia.
hole
J1, J2, J3
3
(SPC) 813
16
Test point, red
J7 (2), J8 (2), TP1
3
(Keystone) 5000
17
Test point, black
TP2
1
(Keystone) 5001
18
Connector, SMA PCB jack
J4, J5, J6
3
(Amphenol) 901-144-8RFX
19
Standoff, 4-40 hex, 0.625" length
4
(Keystone) 1808
20
Screw, Phillips, 4-40, 0.250"
4
SHR-0440-016-SN
21
IC, THS3120
U1 (2)
1
(TI) THS3120DGN
22
Board, printed-circuit (THS3120)
(2)
1
(TI) EDGE # 6445588
23
IC, THS3121
U1
1
(TI) THS3121DGN
24
Board, printed-circuit (THS3121)
1
(TI) EDGE # 6445589
(AVX) 08055C104KAT2A
The manufacturer's part numbers were used for test purposes only.
Applies to the THS3120DGN EVM only.
ADDITIONAL REFERENCE MATERIAL
•
•
•
•
•
•
•
24
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
Current Feedback Analysis and Compensation (SLOA021)
Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications
Journal www.ti.com/sc/analogapps).
THERMAL PAD MECHANICAL DATA
www.ti.com
DGN (S-PDSO-G8)
THERMAL INFORMATION
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy , Texas Instruments Literature No. SLMA004. Both documents are
available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
5
Exposed Thermal Pad
1,73
MAX
1
4
1,78
MAX
Top View
NOTE: All linear dimensions are in millimeters
PPTD041
Exposed Thermal Pad Dimensions
PowerPAD is a trademark of Texas Instruments
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