TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 D D D D D D 3.3-V Supply Operation 10-Bit-Resolution Analog-to-Digital Converter (ADC) Inherent Sample and Hold Function Total Unadjusted Error . . . ± 1 LSB Max On-Chip System Clock Terminal Compatible With TLC1549 and TLC1549x Application Report Available† CMOS Technology D, JG, OR P PACKAGE (TOP VIEW) REF + ANALOG IN REF – GND 1 8 2 7 3 6 4 5 VCC I/O CLOCK DATA OUT CS FK PACKAGE (TOP VIEW) NC REF+ NC VCC NC D D description NC ANALOG IN NC REF– NC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC I/O CLOCK NC DATA OUT NC NC GND NC CS NC The TLV1549C, TLV1549I, and TLV1549M are 10-bit, switched-capacitor, successiveapproximation, analog-to-digital converters. The devices have two digital inputs and a 3-state output [chip select (CS), input-output clock (I/O CLOCK), and data output (DATA OUT)] that provide a three-wire interface to the serial port of a host processor. The sample-and-hold function is automatic. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows lowerror conversion over the full operating free-air temperature range. NC – No internal connection The TLV1549C is characterized for operation from 0°C to 70°C. The TLV1549I is characterized for operation from – 40°C to 85°C. The TLV1549M is characterized for operation over the full military temperature range of – 55°C to 125°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) 0°C to 70°C TLV1549CD – 40°C to 85°C TLV1549ID – 55°C to 125°C — CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) — TLV1549CP — TLV1549IP TLV1549MJG — — — TLV1549MFK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Interfacing the TLV1549 10-Bit Serial-Out ADC to Popular 3.3-V Microcontrollers (SLAA005) Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 typical equivalent inputs INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE 1 kΩ TYP ANALOG IN ANALOG IN Ci = 60 pF TYP (equivalent input capacitance) 5 MΩ TYP functional block diagram REF + 1 REF – 3 10-Bit Analog-to-Digital Converter (switched capacitors) 10 2 ANALOG IN Sample and Hold Output Data Register 10 10-to-1 Data Selector and Driver 4 System Clock, Control Logic, and I/O Counters 7 I/O CLOCK CS 5 Terminal numbers shown are for the D, JG, and P packages only. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 DATA OUT TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 Terminal Functions TERMINAL I/O DESCRIPTION 2 I Analog input. The driving source impedance should be ≤ 1 kΩ. The external driving source to ANALOG IN should have a current capability ≥ 10 mA. CS 5 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high transition disables I/O CLOCK within a setup time plus two falling edges of the internal system clock. DATA OUT 6 O This 3-state serial output for the A/D conversion result is in the high-impedance state when CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next most significant bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused LSBs. GND 4 I The ground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I/O CLOCK 7 I The input /output clock receives the serial I/O CLOCK input and performs the following three functions: 1) On the third falling edge of I/O CLOCK, the analog input voltage begins charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK. 2) It shifts the nine remaining bits of the previous conversion data out on DATA OUT. 3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock. REF + 1 I The upper reference voltage value (nominally VCC) is applied to REF +. The maximum input voltage range is determined by the difference between the voltage applied to REF + and the voltage applied to REF –. REF – 3 I The lower reference voltage value (nominally ground) is applied to this REF –. VCC 8 I Positive supply voltage NAME NO. ANALOG IN detailed description With chip select (CS) inactive (high), the I/O CLOCK input is initially disabled and DATA OUT is in the highimpedance state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then provides the I/O CLOCK sequence to I/O CLOCK and receives the previous conversion result from DATA OUT. I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first ten I/O clocks provide the control timing for sampling the analog input. There are six basic serial interface timing modes that can be used with the TLV1549. These modes are determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are: (1) a fast mode with a 10-clock transfer and CS inactive (high) between transfers, (2) a fast mode with a 10-clock transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between transfers, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with an 11- to 16-clock transfer and CS inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer and CS active (low) continuously. The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and mode 5, within 21 µs from the falling edge of the tenth I/O CLOCK in mode 2 and mode 4, and following the 16th clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of the I/O CLOCK. Ten bits of data are transmitted to the host serial interface through DATA OUT. The number of serial clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long. Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that can be used, and the timing on which the MSB of the previous conversion appears at the output. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 Table 1. Mode Operation MODES Fast Modes Slow Modes NO. OF I/O CLOCKS CS MSB AT DATA OUT† TIMING DIAGRAM Mode 1 High between conversion cycles 10 CS falling edge Figure 6 Mode 2 Low continuously 10 Within 21 µs Figure 7 CS falling edge Figure 8 Mode 3 High between conversion cycles Mode 4 Low continuously Mode 5 High between conversion cycles Mode 6 Low continuously † This timing also initiates serial-interface communication. ‡ No more than 16 clocks should be used. 11 to 16‡ 16‡ 11 to 16‡ 16‡ Within 21 µs Figure 9 CS falling edge Figure 10 16th clock falling edge Figure 11 All the modes require a minimum period of 21 µs after the falling edge of the tenth I/O CLOCK before a new transfer sequence can begin. During a serial I/O CLOCK data transfer, CS must be active (low) so that the I/O CLOCK input is enabled. When CS is toggled between data transfers (modes 1, 3, and 5), the transitions at CS are recognized as valid only if the level is maintained for a minimum period of 1.425 µs after the transition. If the transfer is more than ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur within 9.5 µs after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with the host serial interface and CS has to be toggled to restore proper operation. fast modes The device is in a fast mode when the serial I/O CLOCK data transfer is completed within 21 µs from the falling edge of the tenth I/O CLOCK. With a 10-clock serial transfer, the device can only run in a fast mode. mode 1: fast mode, CS inactive (high) between transfers, 10-clock transfer In this mode, CS is inactive (high) between serial I/O-CLOCK transfers and each transfer is ten clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the internal system clock. mode 2: fast mode, CS active (low) continuously, 10-clock transfer In this mode, CS is active (low) between serial I/O-CLOCK transfers and each transfer is ten clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 µs after the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT. mode 3: fast mode, CS inactive (high) between transfers, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O-CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the internal system clock. mode 4: fast mode, CS active (low) continuously, 16-clock transfer In this mode, CS is active (low) between serial I/O-CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 µs after the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT. slow modes In a slow mode, the serial I/O CLOCK data transfer is completed after 21 µs from the falling edge of the tenth I/O CLOCK. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 mode 5: slow mode, CS inactive (high) between transfers, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O-CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the internal system clock. mode 6: slow mode, CS active (low) continuously, 16-clock transfer In this mode, CS is active (low) between serial I/O-CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next 16-clock transfer initiated by the serial interface. analog input sampling Sampling of the analog input starts on the falling edge of the third I/O CLOCK, and sampling continues for seven I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. converter and analog input The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –) voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF –. If the voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half VCC ), a bit 0 is placed in the output register and the 512-weight capacitor is switched to REF –. If the voltage at the summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains connected to REF + through the remainder of the successive-approximation process. The process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 SC Threshold Detector 512 NODE 512 REF – 256 128 16 REF+ REF+ REF+ REF – ST REF – ST REF – ST 8 4 REF+ REF – ST REF+ REF – ST 2 1 REF+ REF+ REF – ST REF – ST To Output Latches 1 REF – ST ST VI Figure 1. Simplified Model of the Successive-Approximation System chip-select operation The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode. A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device returns to the initial state (the contents of the output data register remain at the previous conversion result). Exercise care to prevent CS from being taken low close to completion of conversion because the output data may be corrupted. reference voltage inputs There are two reference inputs used with the TLV1549: REF + and REF –. These voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero reading, respectively. The values of REF+, REF –, and the analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF + and at zero when the input signal is equal to or lower than REF –. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1): TLV1549C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V TLV1549I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V TLV1549M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V Negative reference voltage, Vref – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.1 V Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA Operating free-air temperature range, TA: TLV1549C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV1549I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C TLV1549M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to ground with REF – and GND wired together (unless otherwise noted). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 recommended operating conditions Supply voltage, VCC MIN NOM MAX 3 3.3 3.6 Positive reference voltage, Vref + (see Note 2) VCC 0 Negative reference voltage, Vref – (see Note 2) Differential reference voltage, Vref + – Vref – (see Note 2) 2.5 Analog input voltage (see Note 2) 0 High-level control input voltage, VIH VCC = 3 V to 3.6 V VCC = 3 V to 3.6 V Low-level control input voltage, VIL Clock frequency at I/O CLOCK (see Note 3) VCC V V V VCC + 0.2 VCC 2 0 UNIT V V V 0.6 V 2.1 MHz 1.425 µs 0 ns Pulse duration, I/O CLOCK high, twH(I/O) 190 ns Pulse duration, I/O CLOCK low, twL(I/O) 190 Setup time, CS low before first I/O CLOCK↑, tsu(CS) (see Note 4) Hold time, CS low after last I/O CLOCK↓, th(CS) Transition time, I/O CLOCK, tt(I/O) (see Note 5 and Figure 5) µs 10 µs 0 70 °C TLV1549I – 40 85 °C TLV1549M – 55 125 °C Transition time, CS, tt(CS) TLV1549C Operating free-air temperature, TA ns 1 NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied to REF – convert as all zeros (0000000000). The TLV1549 is functional with reference voltages down to 1 V (Vref + – Vref –); however, the electrical specifications are no longer applicable. 3. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V), at least one I/O CLOCK rising edge (≥ 2 V) must occur within 9.5 µs. 4. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to the I/O CLOCK. Therefore, no attempt should be made to clock out the data until the minimum CS setup time has elapsed. 5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the device functions with input clock transition time as slow as 1 µs for remote data-acquisition applications where the sensor and the A / D converter are placed several feet away from the controlling microprocessor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX VOH High level output voltage High-level VCC = 3 V, VCC = 3 V to 3.6 V, IOH = – 1.6 mA IOH = – 20 µA VOL Low level output voltage Low-level VCC = 3 V, VCC = 3 V to 3.6 V, IOL = 1.6 mA IOL = 20 µA IOZ Off state (high-impedance-state) Off-state (high impedance state) output current VO = VCC, VO = 0, CS at VCC 10 CS at VCC – 10 IIH IIL High-level input current VI = VCC VI = 0 0.005 2.5 µA Low-level input current – 0.005 – 2.5 µA ICC Operating supply current CS at 0 V 0.4 2.5 mA Analog input leakage current VI = VCC VI = 0 Maximum static analog reference current into REF+ Ci Input capacitance V VCC – 0.1 0.4 0.1 1 –1 TLV1549C, I (Analog) Vref+ = VCC, Vref – = GND During sample cycle 30 TLV1549M, (Analog) During sample cycle 30 TLV1549C, I (Control) POST OFFICE BOX 655303 10 5 TLV1549M, (Control) † All typical values are at VCC = 3.3 V, TA = 25°C. 8 2.4 UNIT 5 • DALLAS, TEXAS 75265 V µA µA µA 55 15 pF TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz PARAMETER TEST CONDITIONS MIN MAX UNIT ±1 LSB Zero error (see Note 7) See Note 2 ±1 LSB Full-scale error (see Note 7) See Note 2 ±1 LSB ±1 LSB 21 µs Linearity error (see Note 6) Total unadjusted error (see Note 8) tconv Conversion time See Figures 6 – 11 tc Total cycle time (access, sample, and conversion) See Figures 6 – 11 and Note 9 tv td(I/O-DATA) Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 5 Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 5 240 ns tPZH, tPZL tPHZ, tPLZ Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 180 ns tr(bus) tf(bus) Rise time, data bus See Figure 5 300 ns Fall time, data bus See Figure 5 300 ns 21 + 10 I/O CLOCK periods 10 µs ns td(I/O-CS) Delay time, 10th I/O CLOCK↓ to CS↓ to abort conversion (see Note 10) 9 µs NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied to REF – convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + – Vref –); however, the electrical specifications are no longer applicable. 6. Linearity error is the maximum deviation from the best straight line through the A / D transfer characteristics. 7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference between 1111111111 and the converted output for full-scale input voltage. 8. Total unadjusted error comprises linearity, zero, and full-scale errors. 9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven I/O CLOCK periods, and ends on the falling edge of the tenth I/O CLOCK (see Figure 5). 10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of the internal clock (1.425 µs) after the transition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 PARAMETER MEASUREMENT INFORMATION VCC Test Point RL = 2.18 kΩ DATA OUT 12 kΩ CL = 100 pF Figure 2. Load Circuit 2V CS 0.8 V tPZH, tPZL tPHZ, tPLZ 2.4 V 90% 0.4 V 10% DATA OUT Figure 3. DATA OUT to Hi-Z Voltage Waveforms 2V CS 0.8 V tsu(CS) th(CS) I/O CLOCK 0.8 V First Clock Last Clock 0.8 V Figure 4. CS to I/O CLOCK Voltage Waveforms tt(I/O) tt(I/O) I/O CLOCK 2V 2V 0.8 V 0.8 V 0.8 V I/O CLOCK Period td(I/O-DATA) tv DATA OUT 2.4 V 2.4 V 0.4 V 0.4 V tr(bus), tf(bus) Figure 5. I/O CLOCK and DATA OUT Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 PARAMETER MEASUREMENT INFORMATION CS (see Note A) I/O CLOCK 1 2 3 4 5 6 7 8 9 10 Sample Cycle B DATA OUT ÎÎÎÎÎÎ ÎÎÎÎÎÎ 1 Hi-Z State A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Previous Conversion Data MSB B9 A/D Conversion Interval (≤ 21 µs) Initialize LSB Initialize Figure 6. Timing for 10-Clock Transfer Using CS Must Be High on Power Up CS (see Note A) I/O CLOCK 1 2 3 4 5 6 7 8 9 10 1 Sample Cycle B DATA OUT A9 A8 A7 A6 A5 A4 A3 See Note B A2 A1 Previous Conversion Data MSB A0 Low Level B9 A/D Conversion Interval (≤ 21 µs) Initialize LSB Initialize Figure 7. Timing for 10-Clock Transfer Not Using CS ÏÏ ÏÏ ÏÏÎÎ ÎÎ ÎÎÎ ÎÎÎ See Note C CS (see Note A) I/O CLOCK 1 2 3 4 5 6 7 8 9 10 Sample Cycle B DATA OUT A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Previous Conversion Data MSB Initialize LSB 11 Low Level 16 Hi-Z 1 B9 A/D Conversion Interval (≤ 21 µs) Initialize Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 µs) NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup time has elapsed. B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. C. The first I/O CLOCK must occur after the end of the previous conversion. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 PARAMETER MEASUREMENT INFORMATION Must Be High on Power Up CS (see Note A) I/O CLOCK 1 2 3 4 5 6 7 8 9 10 14 15 1 16 Sample Cycle B DATA OUT A9 A8 A7 A6 A5 A4 A3 See Note C A2 A1 Previous Conversion Data MSB Low Level A0 B9 A/D Conversion Interval (≤ 21 µs) LSB Initialize Initialize Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed Within 21 µs) CS (see Note A) I/O CLOCK 1 2 3 4 5 6 7 8 9 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Previous Conversion Data MSB 16 11 1 See Note B Sample Cycle B DATA OUT ÏÏÏ ÏÏÏ ÎÎÎ ÌÌÌÌ ÎÎÎ ÌÌÌÌ ÎÎÎ ÎÎÎ A0 LSB Initialize Hi-Z State Low Level A/D Conversion Interval (≤ 21 µs) B9 Initialize Figure 10. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21 µs) Must Be High on Power Up CS (see Note A) I/O CLOCK 1 2 3 4 5 6 7 8 9 10 Sample Cycle B DATA OUT A9 MSB A8 A7 A6 A5 A4 A3 A2 14 15 See Note B A1 Previous Conversion Data A0 1 16 See Note C Low Level B9 LSB A/D Conversion Interval (≤ 21 µs) Initialize Figure 11. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed After 21 µs) NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system clock after CS↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup time has elapsed. B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. C. The first I/O CLOCK must occur after the end of the previous conversion. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 APPLICATION INFORMATION 1023 1111111111 See Notes A and B 1111111110 1022 1111111101 1021 VFT = VFS – 1/2 LSB 513 1000000001 512 1000000000 VZT = VZS + 1/2 LSB Step Digital Output Code VFS 511 0111111111 VZS 0000000001 1 0000000000 0 0.003 0.006 1.5315 1.5345 1.5375 3.066 3.0675 2 0.0015 0000000010 3.069 0 3.072 VI – Analog Input Voltage – V NOTES: A. This curve is based on the assumption that Vref + and Vref – have been adjusted so that the voltage at the transition from digital 0 to 1 (VZ T) is 0.0015 V and the transition to full scale (VF T) is 3.0675 V. 1 LSB = 3 mV. B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is the step whose nominal midstep value equals zero. Figure 12. Ideal Conversion Characteristics TLV1549 Analog Input 2 ANALOG IN CS I/O CLOCK 5 7 Processor DATA OUT 5-V DC Regulated Control Circuit 6 1 REF+ 3 REF – GND To Source Ground 4 Figure 13. Typical Serial Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV1549C, TLV1549I, TLV1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS071C – JANUARY 1993 – REVISED MARCH 1995 APPLICATION INFORMATION simplified analog input analysis Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: ǒ Ǔ The capacitance charging voltage is given by V C + VS 1– e– tcńRtCi where (1) Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS – (VS /2048) (2) ǒ Ǔ Equating equation 1 to equation 2 and solving for time tc gives V and S * ǒ V Ǔ ń2048 + VS 1– e– tcńRtCi S (3) tc (1/2 LSB) = Rt × Ci × ln(2048) (4) Therefore, with the values given the time for the analog input signal to settle is tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048) (5) This time must be less than the converter sample time shown in the timing diagrams. Driving Source† TLV1549 Rs VS VI ri VC 1 kΩ MAX Ci 50 pF MAX VI = Input Voltage at ANALOG IN VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Equivalent Input Capacitance † Driving source requirements: • Noise and distortion for the source must be equivalent to the resolution of the converter. • Rs must be real at the input frequency. Figure 14. Equivalent Input Circuit Including the Driving Source 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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