SM5846AP Multi-function Digital Filter OVERVIEW The SM5846AP is a multi-function digital filter that incorporates 4/8 times oversampling digital audio signal reproduction, digital deemphasis, digital attenuation and soft mute functions. The I/O interface allows serial data transmission of 16/20/24/32-bit input data and 20/24-bit output data. FEATURES Functions ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 8-times oversampling (interpolation) Switchable 8/4 times oversampling output Two master clock frequencies (refer to Clock Functions) • 384fs/512fs (normal-speed sampling) • 192fs/256fs (high-speed sampling) Digital deemphasis • Compatible with 32/44.1/48kHz (normalspeed) and 64/88.2/96kHz (high-speed) input sampling frequencies • ON/OFF control Digital attenuator • 128-step attenuation using linear 7-bit data setting Soft muting • 1016/fs (normal-speed sampling) • 2032/fs (high-speed sampling) Output data round-off operation (normal round-off or rectangular distribution dither round-off) Selectable LR clock polarity Microprocessor controllable Input data format • 2s complement, MSB first, alternating L/R serial • 16/20/24/32-bit data selectable Output data format • 2s complement, MSB first, simultaneous L/R serial • 20/24-bit data selectable. 24-bit internal data processing Jitter-free mode/synchronous mode selectable Crystal oscillator circuit built-in TTL-compatible outputs Molybdenum-gate CMOS Filter Construction ■ ■ ■ ■ Interpolation filter (linear 3-stage FIR filter) • Normal-speed sampling mode 1st stage (fs to 2fs) 121st order 2nd stage (2fs to 4fs) 21st order 3rd stage (4fs to 8fs) 13th order • High-speed sampling mode 1st stage (fs to 2fs) 177th order 2nd stage (2fs to 4fs) 29th order 3rd stage (4fs to 8fs) 17th order Deemphasis filter (IIR filter) Arithmetic units • 25× 24-bit parallel adder • 32-bit accumulator Overflow limiter built-in APPLICATIONS ■ Digital audio equipment ORDERING INFOMATION Device Package SM5846AP 28-pin DIP SEIKO NPC CORPORATION —1 SM5846AP PINOUT (Top view) DIN 1 28 LRCI BCKI 2 27 MDS VDD1 3 26 BCKO DITH 4 25 WCKO CKEN 5 24 DOL XTI 6 23 DOR XTO 7 22 VDD2 VSS1 8 21 VSS2 CKO 9 20 ASEL1 CKS 10 19 OBS ASEL2/MDCK 11 18 TEST2 HS/MDT 12 17 TEST1 SYNC/MDLE 13 16 DEEM RST 14 15 LRS PACKAGE DIMENSIONS 0 to 15° 15.2 13.8 0.2 (Unit: mm) 4.5 0.3 + 0.10 0.25 − 0.05 37.3 0.3 2.54 0.45 0.1 3.2 0.2 7.7 0.5 3.8 0.1 + 0.30 1.5 − 0.05 SEIKO NPC CORPORATION —2 SM5846AP FILTER CHARACTERISTICS Normal-speed Sampling Parameter Rating Passband bandwidth 0 to 0.4535fs Stopband bandwidth 0.5465 to 7.4535fs Passband ripple ±0.0004dB ≥ 75dB Stopband attenuation When CKS is HIGH: 63.89/fs (when SYNC is LOW) and 63.51/fs to 64.26/fs (when SYNC is HIGH) When CKS is LOW: 63.76/fs (when SYNC is LOW) and 63.59/fs to 64.14/fs (when SYNC is HIGH) Group delay time1 1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). Overall frequency characteristic 0 Attenuation [dB] 20 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency [fs] Passband frequency characteristic Attenuation [dB] −0.0005 −0.00025 0.00000 0.00025 0.0005 0.000 0.125 0.250 0.375 0.500 Frequency [fs] Transition band characteristic 0 Attenuation [dB] 20 40 60 80 100 120 140 0.00 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 Frequency [fs] SEIKO NPC CORPORATION —3 SM5846AP High-speed Sampling (8fs Output) Parameter Rating Passband bandwidth 0 to 0.4535fs Stopband bandwidth 0.5465 to 7.4535fs Passband ripple ±0.00001dB ≥ 105dB Stopband attenuation When CKS is HIGH: 51.91/fs (when SYNC is LOW) and 51.53/fs to 52.28/fs (when SYNC is HIGH) When CKS is LOW: 51.78/fs (when SYNC is LOW) and 51.40/fs to 52.15/fs (when SYNC is HIGH) Group delay time1 1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). Overall frequency characteristic 0 Attenuation [dB] 20 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency [fs] Passband frequency characteristic Attenuation [dB] −0.0001 −0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500 Frequency [fs] Transition band characteristic 0 Attenuation [dB] 20 40 60 80 100 120 140 0.00 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 Frequency [fs] SEIKO NPC CORPORATION —4 SM5846AP High-speed Sampling (4fs Output) Parameter Rating Passband bandwidth 0 to 0.4535fs Stopband bandwidth 0.5465 to 7.4535fs Passband ripple ±0.00001dB ≥ 104dB Stopband attenuation When CKS is HIGH: 50.78/fs (when SYNC is LOW) and 50.40/fs to 51.15/fs (when SYNC is HIGH) When CKS is LOW: 50.77/fs (when SYNC is LOW) and 50.40/fs to 51.15/fs (when SYNC is HIGH) Group delay time1 1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). Overall frequency characteristic 0 Attenuation [dB] 20 40 60 80 100 120 140 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Frequency [fs] Passband frequency characteristic Attenuation [dB] −0.0001 −0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500 Frequency [fs] Transition band characteristic 0 Attenuation [dB] 20 40 60 80 100 120 140 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 Frequency [fs] SEIKO NPC CORPORATION —5 SM5846AP Deemphasis Filter Characteristics (Normal-speed Sampling) Parameter Rating Sampling frequency (fs) Passband bandwidth 32kHz 44.1kHz 48kHz 0 to 14.5kHz 0 to 20.0kHz 0 to 21.7kHz Attenuation Deviation from ideal characteristics ±0.01dB Phase 0 to 6° Deemphasis passband characteristic (logarithmic scale) The phase traces are from top to bottom fs = 32/44.1/48kHz, respectively. Attenuation [dB] Phase 2 −20 4 −40 6 −60 8 Phase θ [ ° ] 0 0 Attenuation 10 10 20 50 100 200 500 1k 2k 5k 10k 20k Frequency [Hz] Deemphasis passband characteristic (linear scale) The phase traces are from top to bottom fs = 32/44.1/48kHz, respectively. 0 Phase 2 −20 4 −40 6 −60 8 Phase θ [ ° ] Attenuation [dB] 0 Attenuation 10 0 4k 8k 12k 16k 20k 22k 24k Frequency [Hz] SEIKO NPC CORPORATION —6 SM5846AP Deemphasis Filter Characteristics (High-speed Sampling) Parameter Rating Sampling frequency (fs) Passband bandwidth 64kHz 88.2kHz 96kHz 0 to 29.0kHz 0 to 40.0kHz 0 to 43.5kHz Attenuation Deviation from ideal characteristics ±0.001dB Phase 0 to 1° Deemphasis passband characteristic (logarithmic scale) The phase traces are from top to bottom fs = 64/88.2/96kHz, respectively. Attenuation [dB] Phase 2 −20 4 −40 6 −60 8 Phase θ [ ° ] 0 0 Attenuation 10 10 20 50 100 200 500 1k 2k 5k 10k 20k Frequency [Hz] Deemphasis passband characteristic (linear scale) The phase traces are from top to bottom fs = 64/88.2/96kHz, respectively. Phase Attenuation [dB] 2 −20 4 −40 6 −60 8 Phase θ [ ° ] 0 0 Attenuation 10 0 4k 8k 12k 16k 20k 22k 24k Frequency [Hz] SEIKO NPC CORPORATION —7 SM5846AP SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Symbol Rating Unit Supply voltage range VDD −0.3 to 7.0 V Input voltage range VIN − 0.3 to VDD + 0.3 V Storage temperature range Tstg −40 to 125 °C Power dissipation PD 750 mW Symbol Rating Unit Supply voltage range VDD 4.5 to 5.5 V Operating temperature range Topr −20 to 70 °C Recommended Operating Conditions VSS = 0V Parameter DC Electrical Characteristics VDD = 4.5 to 5.5V, VSS = 0V, Ta = −20 to 70°C Rating Parameter Symbol Condition Unit min typ max – 110 130 mA Supply current consumption1 IDD HIGH-level input voltage VIH All inputs 0.7VDD – – V LOW-level input voltage VIL All inputs – – 0.3VDD V 0.3VDD – – Vp-p VDD − 0.4 – – V XTI AC-coupled input voltage VINAC HIGH-level output voltage VOH All outputs, IOH = −1mA LOW-level output voltage VOL All outputs, IOL = 2mA – – 0.4 V XTI HIGH-level input current IIH VIN = VDD – 10 20 µA XTI LOW-level input current IIL VIN = VSS – 10 20 µA LOW-level input current IIL Inputs excluding XTI, VIN = VSS – 10 20 µA Input leakage current ILH Inputs excluding XTI, VIN = DVDD – – 1.0 µA 1. VDD = 5.0V, fsys = 18.432MHz, 384fs operation, no output load. SEIKO NPC CORPORATION —8 SM5846AP AC Characteristics XTI input timing VDD = 4.5 to 5.5V, VSS = 0V, Ta = −20 to 70°C Rating Parameter Symbol Condition Unit min typ max fOSC 10 – 18.5 MHz tXI 54 – – ns XTI HIGH-level clock pulsewidth tCWH 24 – – ns XTI LOW-level clock pulsewidth tCWL 24 – – ns Oscillator frequency XTI clock pulse cycle time XTI 0.5VDD tCHW tCHW tXI RST input timing VDD = 4.5 to 5.5V, VSS = 0V, Ta = −20 to 70°C Rating Parameter Reset pulsewidth Symbol Condition tRST Unit min typ max When power is applied 1 – – µs At all other times 50 – – ns 0.5VDD RST tRST SEIKO NPC CORPORATION —9 SM5846AP Serial data input timing (BCKI, DIN, LRCI) VDD = 4.5 to 5.5V, VSS = 0V, Ta = −20 to 70°C Rating Parameter Symbol Condition Unit min typ max tBCY 100 – – ns BCKI HIGH-level pulsewidth tBCWH 50 – – ns BCKI LOW-level pulsewidth tBCWL 50 – – ns DIN setup time tDS 20 – – ns DIN hold time tDH 20 – – ns BCKI rising edge to LRCI edge time tBL 50 – – ns LRCI edge to BCKI rising edge time tLB 50 – – ns BCKI pulse cycle time tBCY tBCWH tBCWL 0.5VDD BCKI tDS DIN tDH 0.5VDD VALID tBL LRCI tLB 0.5VDD SEIKO NPC CORPORATION —10 SM5846AP Microprocessor serial interface timing (MDCK, MDT, MDLE) VDD = 4.5 to 5.5V, VSS = 0V, Ta = −20 to 70°C Rating Parameter Symbol Condition Unit min typ max tMCY 100 – – ns MDCK HIGH-level pulsewidth tMCWH 50 – – ns MDCK LOW-level pulsewidth tMCWL 50 – – ns MDT setup time tMDS 20 – – ns MDT hold time tMDH 20 – – ns MDCK rising edge to MDLE edge time tMCL 50 – – ns MDLE edge to MDCK rising edge time tMLC 50 – – ns MDLE HIGH-level pulsewidth tMLWH 20 – – ns MDLE LOW-level pulsewidth tMLWL 20 – – ns MDCK pulse cycle time tMCY tMCWH tMCWL 0.5VDD MDCK tMDS tMDH MDT 0.5VDD tMCL tMCL 0.5VDD MDLE tMLWL tMLWH SEIKO NPC CORPORATION —11 SM5846AP Output signal timing (CKO, BCKO, DOR, DOL, WCKO) VDD = 4.5 to 5.5V, VSS = 0V, Ta = −20 to 70°C, CL = 15pF Parameter Symbol XTI to CKO propagation delay time min typ max tCKH – 17 35 tCKL – 17 35 – 20 60 – 20 60 – 20 60 tsbH tsbL XTI to BCKO propagation delay time tsbH tsbL BCKO to DOR propagation delay time BCKO to DOL propagation delay time BCKO to WCKO propagation delay time Rating Condition Normal and high-speed mode 4fs output High-speed mode 8fs output – 20 60 tbdH −5 – 15 tbdL −5 – 15 tbdH −5 – 15 tbdL −5 – 15 tbdH −5 – 15 tbdL −5 – 15 Unit ns ns ns ns ns CKO output XTI 0.5VDD tCKH tCKL CKO 1.5V BCKO output 0.5VDD XTI tsbH BCKO 1.5V *1 tsbL BCKO tsbH 1.5V *2 tsbL *1 : High speed mode 8fs output *2 : Normal and high-speed mode 8fs output DOR, DOL, WCKO output 1.5V BCKO tbdH DOR DOL WCKO tbdL 1.5V SEIKO NPC CORPORATION —12 SM5846AP PIN DESCRIPTION Number Name I/O1 1 DIN Ip Data input 2 BCKI Ip Bit clock input 3 VDD1 – 5V supply voltage 4 DITH Ip Dither ON/OFF control 5 CKEN Ip Crystal oscillator operation enable 6 XTI I Crystal oscillator input/external clock input 7 XTO O Crystal oscillator output 8 VSS1 – Ground 9 CKO O Master clock output 10 CKS Ip Master clock input frequency select 11 ASEL2/MDCK Ip Operating mode select/microprocessor interface clock input 12 HS/MDT Ip Operating mode select/microprocessor interface data input 13 SYNC/MDLE Ip Sync mode select/microprocessor interface latch enable input 14 RST Ip Reset input 15 LRS Ip LR clock polarity select 16 DEEM Ip Deemphasis ON/OFF select 17 TEST1 Ip Test pin 1. Tie HIGH or leave open for normal operation. 18 TEST2 Ip Test pin 2. Tie LOW for normal operation. 19 OBS Ip Output data length select 20 ASEL1 Ip Operating mode select 21 VSS2 – Ground 22 VDD2 – 5V supply voltage 23 DOR O Right-channel data output 24 DOL O Left-channel data output 25 WCKO O Word clock output 26 BCKO O Output data bit clock output 27 MDS Ip Mode set method select 28 LRCI Ip LR clock input Description 1. Ip = input pin with pull-up resistor, I = input, O = output SEIKO NPC CORPORATION —13 SM5846AP VSS1 VSS2 VDD1 VDD2 Reset Circuit Output data Interface (serial output) DIN BCKI Output data Interface (serial input) Arithmetic Block LRCI LRS Control Control DOR DOL BCKO WCKO OBS Control DITH Micro controller Interface (serial input) ASEL1 ASEL2/MDCK MDS SYNC/MDLE DEEM TEST2 TEST1 Operation Mode Control HS/MDT Clock Generator RST CKS CKEN CKO XTO XTI BLOCK DIAGRAM SEIKO NPC CORPORATION —14 SM5846AP SYSTEM CONFIGURATION Setting DIN BCKI TEST1 MDS HS/MDT ASEL1 ASEL2/MCK SYNC/MLE DEEN DITH LRS OBS TEST2 +5V DOR DOL DAC BCKO LRCI RST VDD2 VDD1 VSS2 VSS1 CKS XTO XTI CKO CKEN WCKO DSP Setting Reset Circuits +5V Oscilation Control DATA FLOW ATT1/ATT2 soft muting uses the D-ATT function to set the gain to −∞. Normal-speed Sampling (fs = 32/44.1/48kHz) DEMI FIRI IN (fs) 2fs LPF (×2) fs 2fs DLY 2fs 2fs ATT1 2fs 2fs FIR2 2fs 2fs (D-ATT / Soft Mute) SWa (121 order) FIR3 LPF (×2) 4fs 4fs (21 order) LPF (×2) 8fs OUT (8fs) 8fs (13 order) High-speed Sampling (fs = 64/88.2/96kHz) FIR5 FIR4 IN (fs) fs LPF (×2) 2fs 2fs SWb(177 order) LPF (×2) 4fs (29 order) DEM2 4fs 4fs 4fs 4fs SWd(ON / OFF) FIR6 ATT2 4fs (D-ATT / Soft Mute) LPF (×2) 8fs (17 order) 8fs 8fs/4fs SWg ( 8fs / 4fs ) OUT ( 8fs / 4fs ) 4fs SEIKO NPC CORPORATION —15 SM5846AP FUNCTIONAL DESCRIPTION Mode Switching and Function Switching The SM5846AP supports several operating modes and function switches. Internal control flags, set by the digital inputs or serial data input signal from a microprocessor, determine the status of those function switches. Mode switching/function switch controls Stage System Name MDS Operating mode switch Clock switch Filter switch Control request Input Yes HS Yes Yes Yes Yes ASEL1 Yes Yes CKS Yes CKEN Yes Yes Output interface switch Operating mode switching Input clock frequency switching Crystal oscillator operating control switching Yes FSEL2 Yes FSEL1 Yes MUTE Input interface switch IC control request switch (input pin/control flag) ASEL2 DEEM Function Control flag Deemphasis ON/OFF switching Deemphasis filter sampling frequency set Yes Mute ON/OFF control DITH Yes (pos. logic) Yes (neg. logic) Dither ON/OFF control SYNC Yes Yes LRS Yes LRCI (LR clock) input polarity switching IBS2 Yes IBS1 Yes OBS Yes Jitter-free/sync mode switching Yes Input data length set Output data length set Control request switching Input pin functions when MDS is LOW MDS input and device control All pins that are part of the microprocessor interface can be used whenever MDS is LOW. Mode switching/function switching is performed under input pin control when MDS is HIGH, and under internal flag control when MDS is LOW. MDS1 Control request HIGH Input pins LOW Control flags Pin name Function HS/MDT Serial data transfer data clock ASEL2/MDCK Serial data transfer clock input SYNC/MDLE Serial data transfer latch enable input 1. Switching MDS during device operation is prohibited. CKS CKS function switch input CKEN CKEN function switch input LRS LRS function switch input Notes Used for the microprocessor interface Input pin control only because there is no corresponding control flag. SEIKO NPC CORPORATION —16 SM5846AP Control flag functions when MSD is HIGH (default) Other requests are controlled by internal flag only because there is no corresponding input pin. These control flags are valid when MDS is HIGH. The default values are shown in the following table. Flag name Default value FSEL2 HIGH FSEL1 HIGH MUTE HIGH IBS2 LOW IBS1 HIGH Default setting 44.1kHz deemphasis filter sampling frequency Muting OFF 16-bit input data length Clock Functions Input clock frequency switching (CKS) This switch is used to select the input clock frequency—384fs or 512fs (normal-speed sampling), and 192fs or 256fs (high-speed sampling). System clock CKS Input sampling frequency fs [kHz] Notes Frequency [MHz] [× fs] 32 16.384 512fs Normal-speed sampling mode 64 16.384 256fs High-speed sampling mode 32 12.288 44.1 16.9344 384fs Normal-speed sampling mode 48 18.432 64 12.288 88.2 16.9344 192fs High-speed sampling mode 96 18.432 LOW HIGH Crystal oscillator control switch (CKEN) This switch is used to start/stop the crystal oscillator circuit. CKEN Crystal oscillator operation HIGH Oscillating LOW Stopped SEIKO NPC CORPORATION —17 SM5846AP Crystal oscillator circuit The built-in crystal oscillator circuit comprises a feedback resistor and several logic gates. The system clock can be generated using an external quartz crystal and 2 capacitors. System Clock Rf CKEN XTI XTO CKO X'tal C1 Oscilation/Stop Contorol C2 System Clock Output External clock When an external clock is used, XTO is left open-circuit and the clock signal is input on XTI. System Clock Rf CKEN XTI XTO CKO Open Oscilation/ Stop Contorol External Clock Input System Clock Output SEIKO NPC CORPORATION —18 SM5846AP Other control settings Filter Stage Input data length select Operating mode ISB1 and ISB2 flags are used to set the input data length. The SM5846A supports 3 different operating modes to control output data rate switching. The operating mode is selected by the state of HS, ASEL1 and ASEL2. IBS2 IBS1 Input data length HIGH HIGH 20 bits HIGH LOW 24 bits LOW HIGH 16 bits LOW LOW 32 bits Notes Operating mode1 The length is set to the default value of 16 bits (IBS2 = LOW and IBS1 = HIGH) after a reset. HS ASEL1 HIGH LOW LOW HIGH ASEL2 HIGH Speed Oversampling Normal-speed sampling 8-times HIGH LOW LRCI input polarity select Pin LRS is used to set the LRCI input polarity. 8-times High-speed sampling 4-times 1. Only the above 3 modes are valid. Operating speed and sampling frequency LRS LRCI Input channel HIGH HIGH Left HIGH LOW Right LOW HIGH Right LOW LOW Left Sync mode select The SYNC pin or flag setting can be used to select either jitter-free mode or sync mode to control synchronization between input data and internal arithmetic blocks. SYNC Mode HIGH Jitter-free mode LOW Sync mode The SM5846AP supports sampling frequencies of 32/44.1/48kHz (normal-speed sampling mode) and 64/88.2/96kHz (high-speed sampling mode). Operating speed Input sampling frequency Normal-speed sampling 32/44.1/48kHz High-speed sampling 64/88.2/96kHz Deemphasis filter The SM5846AP contains a digital deemphasis filter controlled by DEEM. Notes The SYNC flag is set HIGH (default) after a reset. DEEM Deemphasis HIGH ON LOW OFF The sampling frequency is selected by FSEL1 and FSEL2. Sampling frequency fs [kHz] FSEL2 FSEL1 Normal-speed sampling High-speed sampling HIGH HIGH 44.1 88.2 HIGH LOW 48 96 LOW HIGH 44.1 88.2 LOW LOW 32 64 Digital attenuator The digital attenuator is controlled by serial data from the microprocessor interface. This data can set attenuation and muting. Note that the digital attenuator is only enabled when MDS is LOW. ATT1 and ATT2 are used to set the attenuation in normal-speed sampling and high-speed sampling, respectively. SEIKO NPC CORPORATION —19 SM5846AP Attenuation setting Digital attenuator operation The data stored in the D-ATT attenuation register, accessed through the microprocessor interface, determines the attenuation setting of the digital attenuator. The D-ATT register data format is shown below. The attenuation register is reset to 0 (attenuation = 0 dB) after a system reset signal. bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 "0" a1 a2 a3 a4 a5 a6 a7 LSB MSB DATT attenation data (7bit) Register information The attenuation setting is given by the following equations. When data is written to the attenuation register, through the microprocessor interface, the attenuation changes from the current value to the new value at the speed shown in the following table. Operating speed Speed of attenuation change Time from min. to max. attenuation Normal-speed sampling 8/fs per step change 1016/fs (23.0ms at 44.1kHz) High-speed sampling 16/fs per step change 2032/fs (23.0ms at 88.2kHz) Soft muting operation Soft muting ON/OFF is controlled by the MUTE flag, accessed through the microprocessor interface. Attenuation = 0 [dB] (DATT = 0) Attenuation = 20log10 Attenuation = −∞ 127 − DATT [dB] (0 < DATT < 127) 128 (DATT = 127) The attenuation for a selection of values is given in the following table. DATT register value Microprocess or command [hex] Attenuation [dB] 0 00H 0 1 01H −0.137 × 0.984375 2 02H −0.206 × 0.9765625 ↓ ↓ ↓ 63 3FH −6.021 × 0.5 64 40H −6.157 × 0.4921875 ↓ ↓ ↓ 125 7DH −36.12 × 0.015625 126 7EH −42.14 × 0.0078125 127 7FH −∞ Relative gain × 1.0 ↓ MUTE Muting HIGH OFF LOW ON Notes The MUTE flag is set HIGH (default) after a system reset. When muting is ON, the attenuation ramps down to −∞ at the speed shown in the table. Similarly when muting is OFF, the attenuation level returns to the original value at the same speed. If the contents of the DATT attenuation register are changed while muting is ON (attenuation = −∞), only the register contents are replaced. If muting is subsequently turned OFF, the attenuation value changes to the new value at the same speed as shown in the table. ↓ ×0 SEIKO NPC CORPORATION —20 SM5846AP Output data round-off Dither round-off Output data round-off processing is required because the internal data length of the digital filter is different from the output data length (internal data processing width > output data width). Dither round-off is carried out by adding a pseudorandom number between 0 and 1 LSB, derived from a rectangular distribution, to the filter output data to form 20/24-bit output data, depending on the selected output data length. The random number rectangular distribution is shown below (average = 1/2 LSB). The SM5846AP can select either normal round-off or dither round-off on the output data. Round-off processing can be selected either by input pin or control flag settings. MDS DITH pin DITH flag HIGH × HIGH LOW LOW Output data round-off Dither round-off Normal round-off HIGH Normal round-off LOW Dither round-off × Probavility Notes The DITH flag is set HIGH (default) after a system reset. Normal round-off Normal round-off is carried out by adding 1/2 LSB to the filter output data to form 20/24-bit output data, depending on the selected output data length. ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; 0 1/2 1 (LSB) Overflow limiter If an overflow or underflow condition occurs after round-off or filter arithmetic processing, the output data will be fixed at positive or negative maximum value. SEIKO NPC CORPORATION —21 SM5846AP Audio Data Input Interface Audio data input interface pins Serial data transmission is used for the digital audio data input. Audio data is input using pins LRCI, BCKI, and DIN. The LRCI input polarity is determined by pin LRS. The data has the following format: ■ ■ ■ ■ ■ 16/20/24/32-bit data length Alternating left/right-channel serial data transmission MSB first Rear packed 2s complement for negative values Pin name Function LRCI Left/right-channel latch clock input BCKI Bit transfer clock input DIN Serial data input LRS LRCI input polarity switch Serial data on DIN is input to the serial-to-parallel shift register on the falling edge of the bit transfer clock BCKI. The parallel data is then stored in the left/right-channel input buffers on the HIGH/LOWlevel pulse of the LRCI latch clock signal, depending on the selected polarity of the LRCI clock. Audio data input interface schematic 32bit SIPO Shiftregister DIN BCKI D C Q 32bit Register 32bit Register D Left channel C Input Data Buffer Q D Right channel C Input Data Buffer Left channel Input Data Right channel Input Data Q LRCI LRS SEIKO NPC CORPORATION —22 SM5846AP Input data interface example (LRS = HIGH) 32-bit input data length fs Right channel Input Data Left channel Input Data (MSB) DIN 31 30 (LSB) (MSB) 29 28 2 1 0 31 30 (LSB) 29 28 2 1 0 BCKI (64fs) LRCI 24-bit input data length fs Right channel Input Data Left channel Input Data (MSB) DIN 23 (LSB) 22 2 1 0 (LSB) (MSB) 23 22 2 1 0 BCKI (64fs) LRCI 20-bit input data length fs Left channel Input Data Right channel Input Data (MSB) DIN 19 (LSB) 18 2 1 0 (MSB) 19 (LSB) 18 2 1 0 BCKI (64fs) LRCI 16-bit input data length fs Right channel Input Data Left channel Input Data (MSB) DIN 15 (LSB) 14 1 0 (MSB) 15 14 (LSB) 1 0 BCKI (64fs) LRCI SEIKO NPC CORPORATION —23 SM5846AP Input data validity 32-bit input data length 31 30 Polarity Mark 28 26 8 24 6 4 2 0 ;;; ;;; ;;; ;;; ;;; ;;; ;;;;;; ;;; ;;;;;; ;;; ;;;;;; ;;; ;;;;; ;; ;;; ;;;;;; ;;;;;; ;;;;;; ;;;;; Decimal point Effective Number of Bits (24bits) Low order 8 bits cut it off (No round-offattention) Input Data (32bits) 24-bit input data length 23 22 Polarity Mark 20 18 16 6 4 2 0 Decimal point Effective Number of bits (24bits) Input Data (24bits) 20-bit input data length 19 18 16 14 4 2 0 0 Polarity Mark 0 0 0 Decimal point Effective Number of bits (24bits) Input Data (20bits) Input to "0"(4 bits) 16-bit input data length 15 14 12 2 0 0 0 0 0 0 0 0 0 Polarity Mark Decimal point Effective Number of Bits (24bits) Input Data (16bits) Input to "0"(8 bits) SEIKO NPC CORPORATION —24 SM5846AP Audio Data Output Interface Serial data transmission is used for the digital audio data output. The data has the following format: ■ ■ ■ ■ ■ 20/24-bit data length Simultaneous left/right-channel serial data transmission MSB first Bit transfer clock burst (NPC format) 2s complement for negative values Audio data output interface pins Audio data is output using pins WCKO, BCKO, DOL and DIN. Pin name Serial data is output on DOL and DOR on the falling edge of the bit transfer clock BCKO. Generally, external circuits, such as a serial D/A converter, sample the serial data output on DOL and DOR on the rising edge of the bit transfer clock signal, and then shift the data into a register. At the completion of one data cycle (20/24-bit selectable) transfer, the word clock WCKO goes LOW with a 50% duty ratio. Then the external circuit writes parallel data to a buffer register on the falling edge of word clock WCKO. Output data length select The output data length is set by either the OBS pin or flag. Function WCKO Word clock output BCKO Bit transfer clock output DOL Left-channel serial data output DOR Right-channel serial data output OBS Output data length HIGH 24 bits LOW 20 bits Notes The OBS flag is set LOW (default) after a system reset. SEIKO NPC CORPORATION —25 SM5846AP Audio data output interface L-ch Serial DAC DOL D C Following Block VO VOUT(L-ch) VO VOUT(R-ch) STB R-ch Serial DAC D DOR D C BCKO C WCKO STB D 20/24bit SIPO Shiftregister 20/24bit SIPO Shiftregister IN DAC output data format 24-bit output data length 23 22 Polarity Mark 20 18 16 6 4 2 0 Decimal point Output Data (24bits) 20-bit output data length 19 18 Polarity Mark 16 14 4 2 0 Decimal point Output Data (20bits) SEIKO NPC CORPORATION —26 SM5846AP Audio data output timing Normal-speed sampling: 384fs clock, 24-bit data output, 8fs output data rate 1 frame (1/8fs) 1 fCK/2 (192fs) 10 12 20 24 WCKO BCKO DOL 23 22 21 3 20 2 1 0 DOR MSB LSB 24bits Normal-speed sampling: 384fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK/2 (192fs) 1 2 10 12 20 21 24 WCKO BCKO DOL 19 18 1 17 0 DOR MSB LSB 20bits SEIKO NPC CORPORATION —27 SM5846AP Normal-speed sampling: 512fs clock, 24-bit data output, 8fs output data rate 1 frame (1/8fs) 1 2 13 14 15 16 17 18 25 30 32 30 32 fCK/2 (256fs) WCKO BCKO DOL 23 22 21 0 DOR LSB MSB 24bits Normal-speed sampling: 512fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK/2 (256fs) 1 2 13 14 15 16 17 18 19 20 21 WCKO BCKO DOL 19 18 17 0 DOR MSB LSB 20bits SEIKO NPC CORPORATION —28 SM5846AP High-speed sampling: 192fs clock, 24-bit data output, 8fs output data rate 1 frame (1/8fs) 1 fCK (192fs) 2 10 12 20 21 24 WCKO BCKO DOL 23 22 21 20 3 2 1 0 DOR MSB LSB 24bits High-speed sampling: 192fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK (192fs) 1 2 10 12 20 21 1 0 24 WCKO BCKO DOL 19 18 17 DOR MSB LSB 20bits SEIKO NPC CORPORATION —29 SM5846AP High-speed sampling: 256fs clock, 24-bit data output, 8fs output data rate 1 frame (1/8fs) 1 fCK (256fs) 2 13 14 15 16 17 18 25 30 32 WCKO BCKO DOL 23 22 21 0 DOR LSB MSB 24bits High-speed sampling: 256fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK (256fs) 1 2 13 14 15 16 17 18 19 20 21 30 32 WCKO BCKO DOL 19 18 17 0 DOR LSB MSB 20bits SEIKO NPC CORPORATION —30 SM5846AP High-speed sampling: 192fs clock, 24-bit data output, 4fs output data rate 1 frame (1/4fs) fCK/2 (96fs) 1 10 12 20 24 WCKO BCKO DOL 23 22 21 20 3 2 1 0 DOR MSB LSB 24bits High-speed sampling: 192fs clock, 20-bit data output, 4fs output data rate 1 frame (1/4fs) 1 10 12 20 21 24 fCK/2 (96fs) WCKO BCKO DOL 19 18 1 17 0 DOR MSB LSB 20bits SEIKO NPC CORPORATION —31 SM5846AP High-speed sampling: 256fs clock, 24-bit data output, 4fs output data rate 1 frame (1/4fs) 1 13 2 14 15 16 17 18 25 30 32 30 32 fCK/2 (128fs) WCKO BCKO DOL 23 22 0 21 DOR MSB LSB 24bits High-speed sampling: 256fs clock, 20-bit data output, 4fs output data rate 1 frame (1/4fs) 1 2 13 14 15 16 17 18 19 20 21 fCK/2 (128fs) WCKO BCKO DOL 19 18 0 17 DOR MSB LSB 20bits SEIKO NPC CORPORATION —32 SM5846AP Microprocessor Interface Microprocessor interface pins When MDS is LOW, the SM5846AP is controlled by internal flags set by serial data transferred over the microprocessor interface comprising MDLE, MDCK and MDT. Pin name Function MDLE Microprocessor data latch enable input MDCK Microprocessor data transfer clock input MDT Serial data input Internal control flag serial data on MDT is input into an internal shift register on the rising edge of MDCK. After 8-bit data has been input, the data in the shift register is stored in one of four internal flag registers on the rising edge of MDLE latch enable. The address of the flag register is derived by decoding bits 1 to 3 of the 8-bit data. Microprocessor interface 8bit SIPO Shift Register MDT D MDCK C Q 8bit Register 8bit Register D C 8bit Register D C Q 8bit Register D C Q D C Q Q Decoder MDLE D-ATT Attenation Mode flag 1 Mode flag 2 Mode flag 3 Microprocessor interface data input timing MDCK and MDLE can also follow the dotted lines above MDLE MDCK MDT bit1 MSB bit2 bit3 bit4 bit5 bit6 bit7 bit8 LSB SEIKO NPC CORPORATION —33 SM5846AP Serial data format Register Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 D-ATT attenuation 0 a1 a2 a3 a4 a5 a6 a7 Mode flag 1 1 0 SYNC TEST1 = 0 HS FSEL1 FSEL2 DEEM Mode flag 2 1 1 MUTE DITH OBS IBS1 IBS2 1 Mode flag 3 1 1 ASEL1 ASEL2 1 TEST2 = 0 1 0 Address information is displayed in double-line cells of the table. Test bits (mode flag 1 bit 4 and mode flag 3 bit 6) should be set to 0. System Reset When a reset is necessary The device must be reset under the following conditions. ■ When power is first applied When the LRCI clock or system clock stop A 0.01µF external capacitor is recommended. However, the time constant can be lengthened if longer time is required for the XTI and LRCI clocks to stabilize after power-ON. At power-ON reset, RST must go LOW and then go HIGH after the XTI and LRCI clocks stabilize (reset release). The external capacitor discharges through the internal pull-up resistor at power-OFF as this is the only possible discharge path. This could cause reset failure if power is reapplied while the external capacitor is discharging. Therefore, a diode should be connected between RST and VDD to quickly discharge the capacitor and ensure correct power-ON reset operation. Reset timing External power-ON reset circuit ■ Reset input conditions The RST input is active LOW. The internal arithmetic registers and output sequence are initialized on the rising edge of the LRCI clock after reset release. The internal control flags and DATT attenuation register are initialized after RST goes LOW. Outputs DOL and DOR are tied LOW while RST is LOW. ‘ Discharge for Diode Internal Pull-up Register RST Schmitt Buffer Power-ON reset using a capacitor The RST input configuration is a Schmitt-trigger input with a pull-up resistor, which means that a simple power-ON reset circuit can be made by connecting a capacitor between RST and VSS as shown below. External Capacitor C ‘ Internal Pull-up Register RST Schmitt Buffer External Capacitor C SEIKO NPC CORPORATION —34 SM5846AP Internal control flag/D-ATT attenuator register initial values Register Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 D-ATT attenuation 0 a1 = 0 a2 = 0 a3 = 0 a4 = 0 a5 = 0 a6 = 0 a7 = 0 Mode flag 1 1 0 SYNC = 1 TEST1 = 0 HS = 1 FSEL1 = 1 FSEL2 = 1 DEEM = 0 Mode flag 2 1 1 MUTE = 1 DITH = 1 OBS = 0 IBS1 = 1 IBS2 = 0 1 Mode flag 3 1 1 ASEL1 = 1 ASEL2 = 1 1 TEST2 = 1 1 0 When external muting is required Test Precautions The SM5846AP has a relatively long group delay time because multi-stage filters are employed to achieve the desired filter characteristics. Under the following conditions, undesirable noise output can occur during the group delay time period. In this case, it may be necessary to use external muting. The following conditions should be maintained for normal operation. ■ ■ ■ ■ ■ ■ When power is first applied. The state of internal registers may be undefined during power-ON. When switching the operating mode. When switching the operating mode using HS, ASEL1 and ASEL2, the internal register assignments may be changed. If the LRCI and/or XTI clock stop. If a disturbance occurs during an input data cycle, normal filter output may not be achieved. When switching deemphasis ON/OFF. Switching the deemphasis filter parameters may cause switching noise output. When switching the sampling frequency (clock frequency). When switching between input/output data formats (including LRCI clock polarity switching). ■ ■ ■ ■ MDS and DITH inputs should not be simultaneously LOW. TEST1 (bit 4 of mode flag 1 register) should not be set to 1. TEST2 (bit 4 of mode flag 3 register) should be set to 0 after system reset (including power-ON). Mode flag 3 register bit 5 and/or bit 7 should not be set to 0. Note that switching MDS is inhibited during system operation. SEIKO NPC CORPORATION —35 SM5846AP Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: [email protected] NC9616CE 2006.04 SEIKO NPC CORPORATION —36