Ordering number ENA1997 Ordering Orderingnumber number:: :ENA1928B ENA1997 LV4924VH Bi-CMOS IC http://onsemi.com Class-D Audio power Amplifier Power cell BTL 10W×2ch Overview The LV4924VH is a 2-channel full-bridge driver for digital power amplifiers. It requires a PWM modulator IC in the previous stage. This IC is a power cell that takes in PWM signals as an input and is used to form a digital amplifier system for TVs, amusement equipment, and other such systems. Features • BTL output, class D amplifier system • High-efficiency class D amplifier • Muting function reduces impulse noise at power on / off • Protection circuits incorporated for over-current, thermal, supply voltage drop, output offset detector • Built-in bootstrap diodes Specification • • • • Output 15W (VD=16V, RL=8Ω, fIN=1kHz, AES17, THD+N=10%) Output 10W (VD=13V, RL=8Ω, fIN=1kHz, AES17, THD+N=10%) Efficiency : 89% (VD=13V, RL=8Ω, fIN=1kHz, PO=10W) THD+N : 0.1% (VD=13V, RL=8Ω, fIN=1kHz, PO=1W, Filter: AES17) Maximum Ratings / Absolute Maximum Ratings /Ta=25°C Parameter Symbol Conditions Maximum supply voltage VD Externally applied voltage Maximum PWM pin voltage VIN PWM_A1,PWM_A2,PWM_B1,PWM_B2 Maximum pull-up pin voltage Vpup max NPN Open collector pin Allowable power dissipation Pd max Exposed Die-pad Soldered *1 Maximum junction temperature Tj max Operating temperature Storage temperature Ratings Unit 22 V 6 V 20 V 4.6 W 150 °C Topr -25 to 75 °C Tstg -50 to 150 °C *1 Customer bread board rev.1.0: 90.0mm × 70.0 mm × 1.6 mm (two-layer) Material: glass epoxy Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 May, 2013 N1611 SY 20111031-S00002 No.A1997-1/15 LV4924VH Recommended Operating Range at Ta = 25°C Parameter Symbol Recommended supply voltage Ratings Conditions min typ Unit max VD Externally applied voltage 9 13 20 V Recommended PWM pin voltage VIN PWM_A1,PWM_A2,PWM_B1,PWM_B2 0 Recommended pull-up supply Vpup NPN Open collector pin - 3.3 5 V - 18 V RL Speaker load 4 8 - Ω range voltage Recommended load resistance Electrical Characteristics Ta=25°C, VD=13V, RL=8Ω, L=22μH (TOKO: A7040HN-220M), C=0.33μF (Matsuo: 553M6302-334K) Parameter Symbol Ratings Conditions min Quiescent current ICCO STBY=H, MUTE=H, fIN=384kHz, Duty=50% Current at MUTE Imute STBY=H, MUTE=L, VIN=GND Standby current Ist STBY=L, MUTE=L, VIN=GND H input voltage VIH PWM_A, PWM_B, STBY, MUTE L input voltage VI L PWM_A, PWM_B, STBY, MUTE H input current I IH VIN=5V L input current IIL Output pin leakage current IOFF VIN=GND NPN Open collector output Output pin current IOL Power Tr ON resistance *1 Rds ON typ 30 38 45 mA 2 4 6 mA - 10 μA 2.3 - 5.5 V 0 - 1.0 V 60 μA -20 - - - - - OFF-stage 5.0V pull-up Unit max - μA - NPN Open collector output 0.5 ON-stage, VOL=0.4V 1 - Id=1A - 220 μA - mA - mΩ Turn ON delay time td ON fIN=384kHz, Duty=50% - 30 50 Turn OFF delay time td OFF fIN=384kHz, Duty=50% - 30 50 ns Rise-up time tr fIN=384kHz, Duty=50% - 5 20 ns - 5 20 ns Fall time tf fIN=384kHz, Duty=50% *1 : The maximum power transistor ON resistance(RDSON) is 270mΩ(design guarantee value). ns Note : The value of these characteristics were measured in Our test environment. The actual value in an end system will vary depending on the printed circuit board pattern, the components used, and other factors. Electrical Characteristics (Reference value: The table below shows the reference value when FPGA equivalent to the Our reference model is used.) Parameter Symbol Conditions Ratings min typ max Unit Output 1 PO1 THD+N=10%, fIN=1kHz, AES17 - 10 - W Output 2 PO2 VD=16V, THD+N=10%, fIN=1kHz, AES17 - 15 - W Total harmonic distortion THD+N PO=1W, fIN =1kHz, AES17 0.1 % Note : The value of these characteristics were measured in Our test environment. The actual value in an end system will vary depending on the printed circuit board pattern, the components used, and other factors. Audio data IIS PWM BD-mode MCLK MCLK BCLK BCLK LRCLK SDATA FPGA LRCLK LV4924VH SDATA No.A1997-2/15 LV4924VH Package Dimensions unit : mm (typ) 3417 BOTTOM VIEW TOP VIEW 15.0 36 0.5 (3.5) 5.6 7.6 (4.7) 12 1.625 0.22 0.2 0.65 (1.5) SIDE VIEW 0.05 2.17 1.7 MAX (0.68) SANYO : HSSOP36(275mil) OUT_CH2_P OUT_CH2_P PVD2 PVD2 27 26 25 24 23 19 20 21 22 10 11 12 13 14 15 16 17 18 NC8 NC9 NC10 NC11 GND BOOT_CH2_P 28 NC7 OUT_CH1_N 29 VDDA2 OUT_CH1_N 30 NC6 BOOT_CH1_N 31 BOOT_CH2_N VDDA1 32 NC5 BOOT_CH1_P 33 OUT_CH2_N OUT_CH1_P 34 PWM_A2 OUT_CH1_P 35 OUT_CH2_N PVD1 36 PWM_B2 PVD1 Pin Assignment 1 2 3 4 5 6 7 8 9 STBY MUTE SOS NC1 NC2 NC3 NC4 PWM_A1 PWM_B1 LV4924VH GND Top view No.A1997-3/15 LV4924VH Reference data for thermal design Overall view of substrate Mounted on a specified board (Customer bread board rev.1.0): 90.0mm × 70.0 mm × 1.6 mm (two-layer) Material: glass epoxy Pd max-Ta Allowable power dissipation, Pd max -- W 6 5 Pd max -- Ta Specified board : 90.0 × 70.0 × 1.6mm3 glass epoxy Exposed Die-Pad Soldered 4.6 4 3.2 3 Exposed Die-Pad Not Soldered 2.7 2 1.9 1 0 --25 0 25 50 75 100 Ambient temperature, Ta -- C 1. Data of the Exposed Die-Pad (heat spreader) substrate as mounted represents the value in the state where the exposed Die-Pad surface is wet for 90% or more. 2. For the set design, derating design should be made while ensuring allowance. Stresses to become an object of derating are the voltage, current, junction temperature, power loss and mechanical stresses including vibration, impact and tension. Accordingly, these stresses must be as low or small as possible in the design. Approximate targets for general derating are as follows: (1) Maximum value 80% or less for the voltage rating. (2) Maximum value 80% or less for the current rating. (3) Maximum value 80% or less for the temperature rating. 3. After set design, be sure to verify the design with the product. Also check the soldered state of the Exposed Die-Pad, etc. and verify the reliability of the soldered joint. If any void or deterioration is observed in these sections, thermal conduction to the substrate is deteriorated, resulting in thermal damage of IC. No.A1997-4/15 LV4924VH GND GND Block Diagram Pin Equivalent Circuit Pin No. 1 Pin name STBY I/O I Description Equivalent Circuit Standby mode control PVD 1 GND 2 MUTE I Muting control PVD VDDA 2 GND Continued on next page. No.A1997-5/15 LV4924VH Continued from preceding page. Pin No. 3 Pin name SOS I/O Description I Internal protection circuit detection output (OR output of the Equivalent Circuit PVD thermal detection, over-current, voltage drop protection, offset detection circuit) of an NPN open collector output type 3 GND 4 NC1 - Non connection 5 NC2 - Non connection 6 NC3 - Non connection 7 NC4 - Non connection 8 PWM_A1 I PWM input (plus input) of OUT_CH1_P 9 PWM_B1 I PWM input (negative input) of OUT_CH1_N 10 PWM_B2 I PWM input (negative input) of OUT_CH2_N 11 PWM_A2 I PWM input (plus input) of OUT_CH2_P VDDA PVD GND FIN GND - ground 12 NC5 - Non connection 13 NC6 - Non connection 14 NC7 - Non connection 15 NC8 - Non connection 16 NC9 - Non connection 17 NC10 - Non connection 18 NC11 - Non connection 19, 20 PVD2 - Power pin 21, 22 OUT_CH2_P O Output pin, Channel 2 plus 26, 27 OUT_CH2_N O Output pin, Channel 2 minus 28, 29 OUT_CH1_N O Output pin, Channel 1 minus 33, 34 OUT_CH1_P O Output pin, Channel 1 plus PVD GND 23 BOOT_CH2_P I/O Bootstrap I / O pin, channel 2 plus 24 VDDA2 O Internal power supply decoupling capacitor connection 25 BOOT_CH2_N I/O Bootstrap I / O pin, channel 2 minus 30 BOOT_CH1_N I/O Bootstrap I / O pin, channel 1 minus 31 VDDA1 O Internal power supply decoupling capacitor connection BOOT_CH1_P I/O 32 35, 36 PVD1 - Bootstrap I / O pin, channel 1 plus Power pin No.A1997-6/15 LV4924VH Description of functions System Standby The built-in 5V regulator is turned ON / OFF by changing over "H" and "L" of "STBY". The regulator is turned OFF with "STBY" at "L" and ON with "STBY" at "H". This signal also causes initialization of the internal logic initialization with "L" and the normal mode with "H". MUTE Function The MUTE function is mainly for muting of the output and for reduction of pop noise at power ON. Muting the output The output PWM can be turned ON / OFF by changing over "H" and "L" of "MUTE". The PWM output is stopped (putting all of PWM outputs at high impedance) with "MUTE" at "L" and enters the normal operation mode with "MUTE" at "H". Sequence at power ON To reduce the pop noise, turn ON power supply while controlling in the following timing (PWM=BD mode). In particular, all of inputs of PWM must be held at "L" at canceling of MUTE function. * Please observe the following items for the destruction prevention of the output transistor. (1) Under all conditions must control the period at the "H" level about the PWM input so as not to become more than 200μs when period of the "H" level MUTE and STBY signals both. No.A1997-7/15 LV4924VH Sequence at power OFF To reduce the pop noise, turn OFF power supply while controlling in the following timing (PWM=BD mode). Protection Circuit LV4924VH incorporates the over-current protection circuit, thermal protection circuit, supply voltage drop protection circuit and output offset detection protection circuit. Activation of any one of these circuits causes the SOS output pin to become active and thus "L". Over-current protection circuit This circuit is a protection circuit* to protect the output transistor from the over-current and compatible with any mode of lightning, ground fault, and load short-circuit. Protection is done when the detection current value (about 6A) set inside IC is reached, forcing the output transistor to remain OFF for about 20μs. After forced OFF, the transistor returns automatically to the normal operation and performs protection again if the over-current continues to flow. Output Current Control Operation Self-recovery & Normal Operation Internal Control Signal * The over-current protection circuit functions only to avoid the abnormal state, such as output short-circuit, etc., temporarily, and does not guarantee to offer the protection to prevent damage to IC. No.A1997-8/15 LV4924VH Thermal protection circuit This circuit detects the temperature (150°C or more) inside LSI for protection. While this protection circuit is active, the output Tr is turned OFF on both high- and low-sides, putting the output in the high-impedance state. This operation is also provided with the hysteresis. Supply voltage drop protection circuit To avoid unstable operation at low voltages, this circuit monitors the PVD pin voltage and turns ON the amplifier when this voltage exceeds the Attack voltage (VD = 7V typ.). In addition, to avoid unstable operation when the PVD pin voltage has dropped because of certain reasons, the Recover voltage (VD = 6V typ.) is set. Both Attack and Recover voltages have the hysteresis (about 1V) to prevent continuous ON / OFF operation of the supply voltage drop protection circuit. PVD Pin Voltage Recovery Voltage Internal Control Signal Output offset detection protection circuit This circuit is a protection circuit intended to alleviate burn of the loudspeakers when DC outputs to the BTL output for a certain period or more. The circuit detects the case in which each BTL input of each channel continues to disagree (for about 300ms), turns OFF the output Tr on both high- and low-sides, and puts the output in the high-impedance state. No.A1997-9/15 LV4924VH GND GND Application Circuit * SOS of pin 3 is the open collector output. Therefore, to monitor this output with CPU, it is necessary to pull up (resistor: R1) at power supply of CPU, etc. When the output is not to be used (not to be monitored), it is not necessary to pull-up the resistor. No.A1997-10/15 LV4924VH Characteristics Data: L=22μH (TOKO: A7040HN-220M), C=0.33μF (Matsuo: 553M6302-334K) Ist -- VD 0.3 Ipd -- Ta 0.3 Standby current, Ist - A Standby current, Ist - A V D =13V, RL=8 IN=Low, STBYB=Low MUTEB=Low 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 22 0.2 0.1 0 -40 24 -20 Supply voltage, VD - V IMUTE -- VD 8 Muting current, Imute - mA Muting current, Imute - mA 40 60 80 100 120 100 120 100 120 100 120 V D =13V, RL=8 IN=0, STBYB=High MUTEB=Low 7 6 5 4 3 2 6 5 4 3 2 1 1 0 4 6 8 10 12 14 16 18 20 0 -40 22 -20 Supply voltage, VD - V Quiescent current, Icco - mA 60 50 40 30 20 10 0 4 6 8 10 12 14 16 40 60 80 18 20 VD=13V, RL=8 IN=Duty50%[0 to 3.3V] STBYB=High, MUTEB=High 50 40 30 20 10 0 -40 22 -20 Supply voltage, VD - V 0 20 40 60 80 Ambient temperature, Ta - C VDD1,2 -- VD 6 20 Icco -- Ta 70 RL=8 IN=Duty50%[0 to 3.3V] STBYB=High, MUTEB=High 60 0 Ambient temperature, Ta - C Icco -- VD 70 Quiescent current, Icco - mA 20 IMUTE -- Ta 8 RL=8 , IN=Low STBYB=High, MUTEB=Low 7 0 Ambient temperature, Ta - C VDD1,2 -- Ta 6 5 5 4 4 VDDA1,2[V] VDDA1,2[V] RL=8 3 3 2 2 1 1 0 4 6 8 10 12 14 16 Supply voltage, VD - V 18 20 22 0 -40 VD=13V RL=8 -20 0 20 40 60 80 Ambient temperature, Ta - C No.A1997-11/15 LV4924VH td ON -- VD 50 50 40 30 20 10 10 12 14 16 18 20 22 VD=13V RL=8 40 30 20 10 0 -40 0 8 td ON -- Ta 60 Turn ON delay time, td ON - nsec Turn ON delay time, td ON - nsec 60 -20 Supply voltage, VD - V td OFF -- VD 50 40 30 20 10 0 8 10 12 14 16 18 40 60 80 100 120 20 50 80 100 120 100 120 100 120 40 30 20 10 0 -40 22 VD=13V RL=8 -20 Supply voltage, VD - V 0 20 40 60 Ambient temperature, Ta - C tr -- VD 30 20 td OFF -- Ta 60 Turn OFF delay time, td OFF - nsec Turn OFF delay time, td OFF - nsec 60 0 Ambient temperature, Ta - C tr -- Ta 30 Rise-up time, tr - nsec Rise-up time, tr - nsec VD=13V RL=8 20 10 10 12 14 16 18 20 10 0 -40 0 8 20 22 -20 Supply voltage, VD - V tf -- VD 30 0 20 40 60 80 Ambient temperature, Ta - C CH sep. -- Ta 30 20 Full time, tr - nsec Full time, tr - nsec VD=13V RL=8 10 0 8 10 12 14 16 18 Supply voltage, VD - V 20 22 20 10 0 -40 -20 0 20 40 60 80 Ambient temperature, Ta - C No.A1997-12/15 LV4924VH Pd - Power Efficiency -- Power 100 4 80 60 Pd - W Efficiency - % 3 2 40 1 20 0 0 0 2 4 6 8 10 0 2 4 60 3 Pd - W Efficiency - % 80 40 12 15 2 1 0 0 0 3 6 9 12 15 0 3 Power - W/ch Power@THD+N+1% -- Ta Power@THD+N+1% -- VD fIN=1kHz THD+N=1% 2CH-Drive AES17 28 32 28 RL=6 Power@THD+N=1% - W 32 24 RL=4 20 9 6 Power - W/ch Power@THD+N=1% - W 10 Pd - Power 5 20 16 RL=8 12 8 4 24 VD=13V fIN=1kHz THD+N=1% 2CH-Drive AES17 20 16 RL=4 12 RL=6 8 RL=8 4 0 8 10 12 14 18 16 20 0 -40 22 -20 Supply voltage, VD - V fIN=1kHz THD+N=10% 2CH-Drive AES17 36 40 36 RL=6 32 28 RL=4 24 20 RL=8 16 12 32 0 16 Supply voltage, VD - V 100 120 18 20 22 100 120 VD=13V fIN=1kHz THD+N=10% 2CH-Drive AES17 RL=4 16 RL=6 12 4 14 80 20 4 12 60 24 8 10 40 28 8 8 20 Power@THD+N+10% -- Ta 44 Power@THD+N=10% - W 40 0 Ambient temperature, Ta - C Power@THD+N+10% -- VD 44 Power@THD+N=10% - W 8 Power - W/ch Efficiency -- Power 100 6 4 Power - W/ch 0 -40 RL=8 -20 0 20 40 60 80 Ambient temperature, Ta - C No.A1997-13/15 LV4924VH THD+N -- Frequency 10 VD=13V RL=8 PO=1W 2CH-Drive AES17 1 CH1 0.1 CH2 0.01 10 100 1000 THD+N -- Ta 100 Total harmonic distortion, THD+N -- % Total harmonic distortion, THD+N -- % 100 100000 10000 10 VD=13V RL=8 fIN=1kHz PO=1W 2CH-Drive AES17 1 CH1 0.1 CH2 0.01 -40 -20 THD+N -- Frequency 10 VD=16V RL=8 PO=1W 2CH-Drive AES17 1 CH1 0.1 CH2 0.01 10 100 1000 10 Total harmonic distortion, THD+N -- % Total harmonic distortion, THD+N -- % 1 fIN=100Hz fIN=1kHz 0.1 fIN=6.67kHz 0.1 Power - W 120 100 120 CH1 CH2 0.1 -20 0 20 40 80 60 1 THD+N -- Power 100 10 0.01 100 Ambient temperature, Ta - C VD=13V RL=8 2CH-Drive AES17 0.001 80 60 1 0.01 -40 100000 10000 THD+N -- Power 0.01 0.0001 40 VD=16V RL=8 fIN=1kHz PO=1W 2CH-Drive AES17 Frequency - Hz 100 20 THD+N -- Ta 100 Total harmonic distortion, THD+N -- % Total harmonic distortion, THD+N -- % 100 0 Ambient temperature, Ta - C Frequency - Hz 10 100 VD=16V RL=8 2CH-Drive AES17 10 1 fIN=100Hz fIN=1kHz 0.1 fIN=6.67kHz 0.01 0.0001 0.001 0.01 0.1 1 10 100 Power - W No.A1997-14/15 LV4924VH ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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