TI SN65LV1021DB

SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
D
D
D
D
100-Mbps to 400-Mbps Serial LVDS Data
Payload Bandwidth at 10-MHz to 40-MHz
System Clock
Pin-Compatible Superset of NSM
DS92LV1021/DS92LV1212
Chipset (Serializer/Deserializer) Power
Consumption <350 mW (Typ) at 40 MHz
Synchronization Mode for Faster Lock
D
D
D
D
D
D
Lock Indicator
No External Components Required for PLL
Low-Cost 28-Pin SSOP Package
Industrial Temperature Qualified,
TA = – 40°C to 85°C
Programmable Edge Trigger on Clock
(Rising or Falling Edge)
Flow-Through Pinout for Easy PCB Layout
SN65LV1021
Serializer
SYNC1
SYNC2
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
TCLK_R/F
TCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SN65LV1212
Deserializer
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVCC
DVCC
AVCC
AGND
PWRDN
AGND
D O+
D O–
AGND
DEN
AGND
AVCC
DGND
DGND
AGND
RCLK_R/F
REFCLK
AVCC
RI+
RI–
PWRDN
REN
RCLK
LOCK
AVCC
AGND
AGND
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
DVCC
DGND
DVCC
DGND
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
description
The SN65LV1021 serializer and SN65LV1212 deserializer comprise a 10-bit serdes chipset designed to
transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz
to 40 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 480-Mbps
payload-encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC
patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,
the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is
available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1021 and SN65LV1212 are characterized for operation over ambient air temperature of – 40°C to
85°C.
ORDERING INFORMATION
DEVICE
PART NUMBER
Serializer
SN65LV1021DB
Deserializer
SN65LV1212DB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
block diagrams
SN65LVDS1021
SN65LVDS1212
TCLK
(10 MHz
to
40 MHz)
PLL
Timing /
Control
Y+
A–
Y–
PLL
DEN
Clock
Recovery
SYNC1
SYNC2
10
Output Latch
TCLK_R/F
A+
Serial-to-Parallel
Input Latch
DIN
Parallel-to-Serial
LVDS
10
Timing /
Control
DOUT
REFCLK
REN
LOCK
RCLK_R/F
RCLK
(10 MHz to
40 MHz)
functional description
The SN65LV1021 and SN65LV1212 are a 10-bit serializer/deserializer chipset designed to transmit data over
differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 40 MHz. The chipset
has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down
mode, and high-impedance mode. The following sections describe each state of operation.
initialization mode
Initialization of both devices must occur before data transmission can commence. Initialization refers to
synchronization of the serializer and deserializer PLLs to local clocks.
When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state,
while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device
begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an
external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs
remain in the high-impedance state, while the PLL locks to the TCLK.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
functional description (continued)
synchronization mode
The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be
accomplished in one of two ways:
D
Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six
ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the
deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC
patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid a SYNC1 or
SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.
When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock
information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC
patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low.
When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the
deserializer LOCK output directly to SYNC1 or SYNC2.
D
Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the
serializer to send special SYNC patterns. This allows the SN65LV1212 to operate in open-loop applications.
Equally important is the deserializer’s ability to support hot insertion into a running backplane. In the
open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because
lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary
constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK
when the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer
could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive
multitransition (RMT); see Figure 1 for RMT examples. RMT occurs when more than one low-high transition
takes place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the
data pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock
exists. Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock
pattern changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer
is in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary happens
each cycle. The deserializer does not go into lock unitil it finds a unique four consecutive cycles of data boundary
(stop/start bits) at the same position.
The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive
cycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event
of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a
high-impedance state. The user’s system should monitor the LOCK pin in order to detect a loss of
synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if
reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as
previously noted.
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3
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
synchronization mode (continued)
DIN0 Held Low and DIN1 Held High
Stop
Bit
Start
Bit
DIN0
Stop
Bit
Start
Bit
Stop
Bit
Start
Bit
Stop
Bit
Start
Bit
DIN1
DIN4 Held Low and DIN5 Held High
Stop
Bit
Start
Bit
DIN4
DIN5
DIN8 Held Low and DIN9 Held High
Stop
Bit
Start
Bit
DIN8
DIN9
Figure 1. RMT Pattern Examples
data transmission mode
After initialization and synchronization, the serializer accepts parallel data from inputs DIN0 – DIN9. The serializer
uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to
strobe incoming data. If either of the SYNC inputs is high for 6 TCLK cycles, the data at DIN0 – DIN9 is ignored
regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent.
After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the
register. The start bit is always high and the stop bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO±)
at 12 times the TCLK frequency. For example, if TCLK is 10 MHz, the serial rate is 10 × 12 = 120 Mbps. Because
only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 12 MHz,
the useful data rate is 10 × 12 = 120 Mbps. The data source, which provides TCLK, must be in the range of
10 MHz to 40 MHz.
4
POST OFFICE BOX 655303
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SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
functional description (continued)
The serializer outputs (DO±) can drive point-to-point connections or limited multipoint or multidrop backplanes.
The outputs transmit data when the enable pin (DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the serializer output pins enter the high-impedance state.
Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks
to the embedded clock and uses it to recover the serialized data. ROUTx data is valid when LOCK is low,
otherwise ROUT0 – ROUT9 is invalid. The ROUT0–ROUT9 data is strobed out by RCLK. The specific RCLK edge
polarity to be used is selected by the RCLK_R/F input. The ROUT0 – ROUT9, LOCK and RCLK outputs can drive
a maximum of three CMOS input gates (15-pF load, total for all three) with a 40-MHz clock.
power down
When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the
power-down mode, a low-power sleep mode, to reduce power consumption. The deserializer enters power
down when you drive PWRDN and REN low. The serializer enters power down when the PWRDN is driven low.
In power down, the PLL stops and the outputs enter a high-impedance state, which disables load current and
reduces supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high.
Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and
resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer
initializes and drives LOCK high until lock to the LVDS clock occurs.
high-impedance mode
The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output
pins (DO+ and DO–) into a high-impedance state. When you drive DEN high, the serializer returns to its previous
state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin
is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins
(ROUT0 – ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active,
reflecting the state of the PLL.
Deserializer Truth Table
INPUTS
OUTPUTS
PWRDN
REN
ROUT[0:9]
LOCK
H
H
RCLK
H
Z
H
Z
H
Active
L
Active
L
X
Z
Z
Z
H
L
Z
Active
Z
NOTES: 1. LOCK output reflects the state of the deserializer with regard
to the selected data stream.
2. RCLK active indicates the RCLK is running if the deserializer
is locked. The timing of RCLK with respect to ROUT is
determined by RCLK_R/F.
3. ROUT and RCLK are 3-stated when LOCK is asserted high.
POST OFFICE BOX 655303
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5
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
Terminal Functions
serializer
PIN
NAME
DESCRIPTION
1, 2
SYNC1, SYNC2
LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted high
for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If after completion
of transmission of 1026 patterns SYNC continues to be asserted, then the transmission continues until SYNC
is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC pattern transmission initiates.
3 – 12
DIN0–DIN9
Parallel LVTTL data inputs
13
TCLK_R/F
LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data strobe.
14
TCLK
LVTTL-level reference clock input. The SN65LV1021 accepts a 10-MHz to 40-MHz clock. TCLK strobes
parallel data into the input latch and provides a reference frequency to the PLL.
15, 16
DGND
Digital circuit ground
18, 20, 23,
25
AGND
Analog circuit ground (PLL and analog circuits)
17, 26
AVCC
DEN
Analog circuit power supply (PLL and analog circuits)
19
21
DO –
DO +
22
27, 28
DVCC
PWRDN
24
LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial data
output.
Inverting LVDS differential output
Noninverting LVDS differential output
Digital circuit power supply
LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedance
state, putting the device into a low-power mode.
deserializer
PIN
NAME
3
REFCLK
15 – 19,
24 – 28
ROUT0–ROUT9
2
RCLK_R/F
9
RCLK
LVTTL-level output recovered clock. Use RCLK to strobe ROUTx.
14, 20, 22
DGND
Digital circuit ground
1, 12, 13
AGND
Analog circuit ground (PLL and analog circuits)
4, 11
AVCC
REN
Analog circuit power supply (PLL and analog circuits)
8
5
RI+
Serial data input. Noninverting LVDS differential input
6
RI–
LOCK
10
21, 23
7
6
DVCC
PWRDN
DESCRIPTION
LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency.
Parallel LVTTL data outputs
LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data
strobe.
LVTTL logic input. Low places ROUT0–ROUT9, LOCK, and RCLK in the high-impedance state.
Serial data input. Inverting LVDS differential input
LVTTL-level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge.
Digital circuit power supply
LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state,
putting the device into a low-power mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
absolute maximum ratings (unless otherwise noted)†
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4 V
LVTTL input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to (VCC + 0.3 V)
LVTTL output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to (VCC + 0.3 V)
LVDS receiver input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 3.9 V
LVDS driver output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 3.9 V
LVDS output short circuit duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Electrostatic discharge: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 6 kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 200 V
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature (soldering, 4 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Maximum package power dissipation, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.27 W
Package derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 mW/°C above 25°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC}
3
3.3
3.6
V
Receiver input voltage range
0
2.4
V
V
ID
2
Receiver input common mode range, VCM
Supply noise voltage
V
2.4 –ǒ IDǓ
2
100
UNIT
V
mVP–P
Operating free-air temperature, TA
–40
25
85
°C
‡ By design, DVCC and AVCC are separated internally and does not matter what the difference is for DVCC–AVCC, as long as both are within
3 V to 3.6 V.
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7
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
electrical characteristics over recommended operating supply and temperature ranges (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note 4)
VIH
VIL
High-level input voltage
2
Low-level input voltage
GND
VCL
IIN
Input clamp voltage
ICL = –18 mA
VIN = 0 V or 3.6 V
Input current (see Note 5)
VCC
0.8
V
–1.5
V
200
µA
VCC
0.8
V
– 0.62
–1.5
V
200
µA
2.2
3
V
GND
0.25
VCC
0.5
–15
–47
–85
mA
–10
±1
10
µA
350
400
–200
± 100
V
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note 6)
VIH
VIL
High-level input voltage
2
Low-level input voltage
GND
VCL
IIN
Input clamp voltage
VOH
VOL
High-level output voltage
IOS
IOZ
Output short-circuit current
ICL = –18 mA
VIN = 0 V or 3.6 V
Input current
–200
IOH = – 5 mA
IOL = 5 mA
Low-level output voltage
VOUT = 0 V
PWRDN or REN = 0.8 V, VOUT = 0 V or VCC
High-impedance output current
V
V
SERIALIZER LVDS DC SPECIFICATIONS (apply to pins DO+ and DO –)
VOD
∆VOD
Output differential voltage (DO+)–(DO–)
VOS
∆VOS
Offset voltage
IOS
IOZ
Output short circuit current
D0 = 0 V, DINx = high, PWRDN and DEN = 2.4 V
High-impedance output current
PWRDN or DEN = 0.8 V, DO = 0 V or VCC
Output differential voltage unbalance
RL = 27
2 Ω,, See Figure 18
1.1
1.2
IOX
Power-off output current
VCC = 0 V, DO = 0 V or VCC
DESERIALIZER LVDS DC SPECIFICATIONS (apply to pins RI+ and RI–)
Differential threshold high voltage
V
35
mV
–10
– 90
mA
–10
±1
10
µA
–20
±1
20
µA
50
mV
IIN
Input current
VCM = 1.1 V
Differential threshold low voltage
– 50
mV
–10
±1
15
–10
± 0.05
10
f = 40 MHz
40
50
f = 10 MHz
20
25
200
500
f = 40 MHz
63
75
f = 10 MHz
15
35
0.36
1
VIN = 2.4 V, VCC = 3.6 V or 0 V
VIN = 0 V, VCC = 3.6 V or 0 V
mV
1.3
Offset voltage unbalance
VTH
VTL
mV
35
µA
SERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
ICCD
RL = 27 Ω, See Figure 2
Serializer supply current, worst case
ICCXD Serializer supply current, power down
PWRDN = 0.8 V
DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
ICCR
Deserializer supply current, worst case
CL = 15 pF, See Figure 3
ICCXR Deserializer supply current, power down
PWRDN = 0.8 V, REN = 0.8 V
NOTES: 4. Apply to DIN0 – DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN
5. High IIN values are due to pull-up and pull-down resistors on the inputs.
6. Apply to input pins PWRDN, RCLK_R/F, REN, REFCLK; apply to output pins ROUTx, RCLK, LOCK
8
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• DALLAS, TEXAS 75265
mA
µA
mA
mA
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
serializer timing requirements for TCLK over recommended operating supply and temperature
ranges (unless otherwise specified)
PARAMETER
MIN
TYP
MAX
UNIT
25
T
100
ns
Transmit clock high time
0.4T
0.5T
0.6T
ns
Transmit clock low time
0.4T
0.5T
0.6T
ns
3
6
ns
tTCP
tTCIH
Transmit clock period
tTCIL
tt(CLK)
tJIT
TCLK input jitter
TEST CONDITIONS
TCLK input transition time
See Figure 6
150
ps (RMS)
serializer switching characteristics over recommended operating supply and temperature ranges
(unless otherwise specified)
PARAMETER
TEST CONDITIONS
tTLH(L)
tTHL(L)
LVDS low-to-high transition time
tsu(DI)
th(D)
DIN0–DIN9 setup to TCLK
td(HZ)
td(LZ)
DO± high-to-high impedance state delay
td(ZH)
td(ZL)
DO± high-impedance state-to-high delay
tw(SP)
tPLD
SYNC pulse duration
MIN
RL = 27 Ω,, CL = 10 pF to GND,
See Figure 4
LVDS high-to-low transition time
RL = 27 Ω,, CL = 10 pF to GND,
See Figure 7
DIN0–DIN9 hold from TCLK
DO± low-to-high impedance state delay
MAX
0.2
1
ns
0.25
1
ns
1
0
6.5
4.5
RL = 27 Ω,, CL = 10 pF to GND,
See Figure 8
RL = 27 Ω,, See Figure 9 and
Figure 10
td(S)
Serializer delay
RL = 27 Ω, See Figure 11
t(BIT)
Bus LVDS bit width
RL = 27 Ω, CL = 10 pF to GND
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
2.5
DO± high-impedance state-to-low delay
Serializer PLL lock time
TYP
5
ns
2.5
5
ns
2.5
10
ns
2.7
10
ns
6×tTCP
1026×tTCP
ns
ns
t
tCLK/12
TCP
2
)3
ns
ns
9
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
deserializer timing requirements for REFCLK over recommended operating supply and
temperature ranges (unless otherwise specified)
PARAMETER
tRFCP
tRFDC
REFCLK period
tt(RF)
REFCLK transition time
TEST CONDITIONS
REFCLK duty cycle
MIN
TYP
MAX
UNIT
25
T
100
ns
40%
50%
60%
3
6
ns
deserializer switching characteristics over recommended operating supply and temperature
ranges (unless otherwise specified)
PARAMETER
tRCP
Receiver out clock period
tTLH(C)
CMOS/TTL low-to-high transition
time
tTHL(C)
CMOS/TTL high-to-low transition
time
td(D)
Deserializer delay,
See Figure 12
tsu(ROS)
ROUT0–ROUT9 setup data to
RCLK
t(ROH)
ROUT0–ROUT9 hold data to
RCLK
t(RDC)
RCLK duty cycle
td(HZ)
High-to-high impedance state
delay
td(LZ)
Low-to-high impedance state
delay
td(ZH)
High-impedance state-to-high
delay
td(ZL)
High-impedance state-to-low
delay
t(DSR1)
Deserializer PLL lock time from
PWRDN
(with SYNCPAT)
t(DSR2)
Deserializer PLL lock time from
SYNCPAT
td(ZHL)
High-impedance state-to-high
delay (power up)
t(RNM)
Deserializer noise margin
TEST
CONDITIONS
PIN/FREQ
t(RCP) = t(TCP)
See Figure 11
RCLK
CL =15 pF,
See Figure 5
ROUT0–
ROUT 9,
LOCK,
RCLK
Room
temperature,
3.3 V
See Figure 13
See Figure 14
See Figure 15,
Figure 16, and
Note 7
MIN
TYP
MAX
UNIT
100
ns
0.7
2.5
ns
1.1
2.5
ns
25
10 MHz
2×tRCP + 9
2.833×tRCP + 14
40 MHz
2×tRCP + 6
2.833×tRCP + 10
RCLK
0.4×tRCP
0.5×tRCP
– 0.4×tRCP
– 0.5×tRCP
40%
50%
60%
6.7
8
ns
4.6
8
ns
5.5
8
4.8
8
ns
ROUT0–
ROUT 9,
LOCK
10 MHz
(1024+26)tRFCP
40 MHz
(1024+26)tRFCP
10 MHz
0.7
40 MHz
0.2
LOCK
See Figure 17
and Note 8
ns
3
10 MHz
3680
40 MHz
1100
ns
ns
µss
ns
ps
NOTES: 7. t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon power up or when leaving the
power-down mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled
deserializer when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In
order to specify deserializer PLL performance tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions
of SYNCPATs.
8. tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
timing diagrams and test circuits
TCLK
ODD DIN
EVEN DIN
Figure 2. Worst-Case Serializer ICC Test Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 3. Worst-Case Deserializer ICC Test Pattern
10 pF
tTLH(L)
DO +
RL
Vdiff
tTHL(L)
80%
20%
80%
20%
DO –
10 pF
Vdiff = (DO+) – (DO–)
Figure 4. Serializer LVDS Output Load and Transition Times
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
timing diagrams and test circuits (continued)
Deserializer
CMOS/TTL Output
tTLH(C)
tTHL(L)
80%
15 pF
80%
20%
20%
Figure 5. Deserializer CMOS/TTL Output Load and Transition Times
tt(CLK)
TCLK
tt(CLK)
90%
3V
90%
10%
10%
0V
Figure 6. Serializer Input Clock Transition Time
tTCP
1.5 V
TCLK
1.5 V
For TCLK_R/F = Low
1.5 V
th(DI)
tsu(DI)
DIN [9:0]
1.5 V
Setup
Hold
1.5 V
Figure 7. Serializer Setup/Hold Times
Parasitic Package and
Trace Capacitance
3V
DEN
1.5 V
1.5 V
0V
td(HZ)
DO +
13.5 Ω
td(ZH)
VOH
50%
50%
1.1 V
1.1 V
DO –
DEN
13.5 Ω
DO ±
td(LZ)
1.1 V
50%
VOL
Figure 8. Serializer High-Impedance-State Test Circuit and Timing
12
td(ZL)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
50%
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
timing diagrams and test circuits (continued)
PWRDN
2V
0.8 V
td(HZ) or td(LZ)
1026 Cycles
TCLK
td(ZH) or td(ZL)
t(PLD)
DO ±
1026 Cycles
3-State
Output Active
3-State
SYNC Pattern
DEN = High
tw(SP)
SYNC
1.5 V
1.5 V
Figure 9. Serializer PLL Lock Time and PWRDN High-Impedance-State Delays
REN
PWRDN
TCLK
tw(SP)
SYNC1
or
SYNC2
DO ±
DATA
SYNC Pattern
TCLK
SYNC1
or
SYNC2
tw(SP) Min. Timing Met
DO ±
DATA
SYNC Pattern
Figure 10. SYNC Timing Delays
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
timing diagrams and test circuits (continued)
DIN
DIN0 – DIN9 SYMBOL N
DIN0 – DIN9 SYMBOL N+1
td(S)
TCLK
Timing for TCLK_R/F = High
Start
Stop
Bit
D00 – D09 SYMBOL N–1 Bit
Start
Bit
D00 – D09 SYMBOL N
Stop
Bit
DO
Figure 11. Serializer Delay
Start
Bit
D00 – D09 SYMBOL N
Stop
Bit
Start
Bit
D00 – D09 SYMBOL N+1
Stop
Bit
Start
Bit
D00 – D09 SYMBOL N+2
RI
Stop
Bit
1.2 V
1V
tDD
RCLK
Timing for RCLK_R/F = High
ROUT
ROUT0 – ROUT9 SYMBOL N–1
ROUT0 – ROUT9 SYMBOL N
Figure 12. Deserializer Delay
tLow
tHigh
RCLK
RCLK_R/F = Low
tHigh
tLow
RCLK
RCLK_R/F = High
tROH
tROS
ROUT [9:0]
1.5 V
Data Valid
Before RCLK
Data Valid
After RCLK
1.5 V
Figure 13. Deserializer Setup and Hold Times
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ROUT0 – ROUT9 SYMBOL N+1
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
timing diagrams and test circuits (continued)
7 V(LZ/ZL), Open (HZ/ZH)
VOH
500 Ω
450 Ω
REN
Scope
1.5 V
1.5 V
VOL
td(ZL)
td(LZ)
50 Ω
VOL + 0.5 V
VOL + 0.5 V
VOL
ROUT[9:0]
td(ZH)
td(HZ)
VOH
VOH – 0.5 V
VOH – 0.5 V
Figure 14. Deserializer High-Impedance-State Test Circuit and Timing
PWRDN
2V
0.8 V
REFCLK
1.5 V
tDSR1
DATA
RI±
Not Important
td(ZHL)
LOCK
SYNC Patterns
3-State
3-State
td(ZH) or td(ZL)
ROUT[9:0]
td(HZ) or td(LZ)
3-State
3-State
SYNC Symbol or DIN[9:0]
RCLK
3-State
3-State
RCLK_R/F = Low
REN
Figure 15. Receiver LVDS Input Skew Margin
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
timing diagrams and test circuits (continued)
3.6 V
3V
VCC
0V
PWRDN
0.8 V
REFCLK
tDSR2
DATA
1.2 V
RI±
Not Important
1V
SYNC Patterns
LOCK
3-State
td(ZH) or td(ZL)
ROUT[9:0]
td(HZ) or td(LZ)
3-State
3-State
SYNC Symbol or DIN[9:0]
RCLK
3-State
3-State
REN
Figure 16. Deserilaizer PLL Lock Time From SyncPAT
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
timing diagrams and test circuits (continued)
1.2 V
VTH
VTL
RI±
1V
tDJIT
tDJIT
tRNM
tRNM
tSW
Ideal Sampling Position
tSW: Setup and Hold Time (Internal Data Sampling Window)
tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK
tRNM: Receiver Noise Margin Time
Figure 17. Receiver LVDS Input Skew Margin
DO +
RL
10
DIN
Parallel-to-Serial
DO –
> TCLK
VOD = (DO+) – (DO–)
Differential Output Signal Is Shown as (DO+) – (DO–)
Figure 18. VOD Diagram
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SN65LV1021/SN65LV1212
10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°– 8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
18
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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