TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 D D D D D D D D D 8-Bit Resolution A/D Converter Microprocessor Peripheral or Stand-Alone Operation On-Chip 12-Channel Analog Multiplexer Built-in Self-Test Mode Software-Controllable Sample and Hold Total Unadjusted Error . . . ± 0.5 LSB Max Direct Replacement for Motorola MC145041 On-Board System Clock End-of-Conversion (EOC) Output Pinout and Control Signals Compatible With the TLC1542/3 10-Bit A/D Converters CMOS Technology PARAMETER VALUE Channel Acquisition/Sample Time 16 µs DW OR N PACKAGE (TOP VIEW) INPUT A0 INPUT A1 INPUT A2 INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8 GND 25 × 103 Samples per Second (Max) Power Dissipation (Max) 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC EOC I/O CLOCK ADDRESS INPUT DATA OUT CS REF+ REF– INPUT A10 INPUT A9 FN PACKAGE (TOP VIEW) 20 µs Conversion TIme (Max) 1 INPUT A2 INPUT A1 INPUT A0 VCC EOC D D 10 mW INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 description 4 3 2 1 20 19 18 5 17 6 16 I/O CLOCK ADDRESS INPU DATA OUT CS REF+ INPUT A8 GND INPUT A9 INPUT A10 REF– The TLC542 is a CMOS converter built around an 15 7 8-bit switched-capacitor successive-approximation 14 8 9 10 11 12 13 analog-to-digital converter. The device is designed for serial interface to a microprocessor or peripheral via a 3-state output with three inputs [including I/O CLOCK, CS (chip select), and ADDRESS INPUT]. The TLC542 allows high-speed data transfers and sample rates of up to 40,000 samples per second. In addition to the high-speed converter and versatile control logic, an on-chip 12-channel analog multiplexer can sample any one of 11 inputs or an internal “self-test” voltage, and the sample and hold is started under microprocessor control. At the end of conversion, the end-of-conversion (EOC) output pin goes high to indicate that conversion is complete. Detailed information on interfacing to most popular microprocessors is readily available from the factory. AVAILABLE OPTIONS PACKAGE TA CHIP CARRIER (FN) PLASTIC DIP (N) SMALL OUTLINE (DW) 0°C to 70°C — TLC542CN TLC542CDW – 40°C to 85°C TLC542IFN TLC542IN TLC542IDW Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 description (continued) The converter incorporated in the TLC542 features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noises. A switchedcapacitor design allows low-error (± 0.5 LSB) conversion in 20 µs over the full operating temperature range. The TLC542C is characterized for operation from 0°C to 70°C and the TLC542I is characterized for operation from – 40°C to 85°C. functional block diagram REF+ 8-Bit Analog-to-Digital Converter (Switched-Capacitors) Sample and Hold 8 12-Channel Analog Multiplexer Analog Inputs REF– 4 Output Data Register Input Address Register 8 8-to-1 Data Selector and Driver DATA OUT 4 Self-Test Reference 4 Input Multiplexer ADDRESS INPUT Control Logic and I/O Counters 2 I/O CLOCK CS EOC typical equivalent inputs INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE 1 kΩ TYP INPUT A0 – A10 2 INPUT A0 – A10 Ci = 60 pF TYP (equivalent input capacitance) POST OFFICE BOX 655303 5 MΩ TYP • DALLAS, TEXAS 75265 TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 operating sequence 1 2 3 4 5 6 7 8 I/O CLOCK 1 2 3 4 5 6 7 8 Don’t Care Access Cycle B (see Note A) tsu(A) tacq Access Cycle C tconv tacq 12 Internal System Clocks ≤ 12 µs tsu(CS) CS MSB ADDRESS INPUT B3 LSB B2 B1 MSB Don’t Care B0 C3 LSB C2 C1 Don’t Care C0 Hi-Z State Hi-Z State DATA OUT A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 See Note B Previous Conversion Data A MSB LSB (see Note B) td(I/O–EOC) Conversion Data B td(EOC–DATA) MSB LSB EOC tcycle NOTES: A. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of the internal system clock after CS↓ before responding to control input signals. The CS setup time is given by the tsu(CS) specifications. Therefore, no attempt should be made to clock-in an address until the minimum chip select setup time has elapsed. B. The output is 3-stated on CS going high or on the negative edge of the eighth I/O clock. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Peak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA Operating free-air temperature range: TLC542C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC542l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 recommended operating conditions, VCC = 4.75 to 5.5 V MIN NOM MAX 4.75 5 5.5 V Vref– – 0.1 VCC 0 VCC + 0.1 Vref+ V Differential reference voltage, Vref+ – Vref– (see Note 2) 1 VCC Analog input voltage (see Note 3) 0 High-level control input voltage, VIH 2 Supply voltage, VCC Positive reference voltage, Vref + (see Note 2) Negative reference voltage, Vref – (see Note 2) UNIT VCC + 0.2 VCC V V V Low-level control input voltage, VIL 0.8 Setup time, address bits at data input before I/O CLOCK↑, tsu(A) V V 400 ns Hold time, address bits after I/O CLOCK↑, th(A) 0 ns Hold time, CS low after 8th I/O CLOCK↑, th(CS) 0 ns 3.8 µs Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 4) Input/output clock frequency, fclock(I/O) 0 Input/output clock high, twH(I/O) Input/output clock low, twL(I/O) I/O CLOCK transition time, time tt (see Note 3) Operating free-air free air temperature, temperature TA 1.1 MHz 404 ns 404 ns fclock(I/O) ≤ 525 kHz fclock(I/O) > 525 kHz 100 ns 40 TLC542C TLC542I 0 70 – 40 85 °C NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (11111111), while input voltages less than that applied to REF – convert as all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF –. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 3. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor. 4. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of the internal system clock after CS ↓ before responding to control input signals. The CS setup time is given by the tsu(CS) specifications. Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed. electrical characteristics over recommended operating temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 1.1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX Low-level output voltage VCC = 4.75 V, VCC = 4.75 V, IOH = – 360 µA IOL = 1.6 mA Off-state ((high-impedance g state)) output current VO = VCC, VO = 0, CS at VCC 10 CS at VCC –10 IIH IIL High-level input current Low-level input current VI = VCC VI = 0 ICC Operating supply current CS at 0 V VOH VOL High-level output voltage (DATA OUT) V 0.4 Selected at VCC, Unselected channel at 0 V Iref Maximum static analog reference current into REF+ Vref+ = VCC, Ci Input capacitance 2 µA – 2.5 µA 2 mA 0.4 – 40°C to 85°C – 0.4 Vref – = GND 10 Analog inputs 7 55 Control inputs 5 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 µA 0.005 0°C to 70 °C † All typical values are at TA = 25°C. V – 0.005 1.2 Selected channel leakage current 4 2.4 UNIT µA µA pF TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 operating characteristics over recommended operating free-air temperature range, VCC = Vref + = 4.75 to 5.5 V, fclock(I/O) = 1 MHZ PARAMETER EL EZS Linearity error (see Note 5) Zero-scale error (see Note 6) EFS Full-scale error (see Note 6) TEST CONDITIONS MIN TYP† MAX UNIT ±0.5 LSB See Note 2 ±0.5 LSB See Note 2 ±0.5 LSB ±0.5 LSB Total unadjusted error (see Note 7) Self-test output code Input A11 address = 1011, See Note 8 01111101 (126) tconv tcycle Conversion time See operating sequence 20 µs Total access and conversion cycle time See operating sequence 40 µs tacq tv Channel acquisition time (sample cycle) See operating sequence 16 µs Time ouput data remains valid after I/O CLK↓ See Figure 5 td(IO-DATA) td(IO-EOC) Delay time, I/O CLK↓ to data output valid See Figure 5 400 ns Delay time, 8th I/O CLK↓ to EOC↓ See Figure 6 500 ns td(EOC-DATA) tPZH, tPZL Delay time, EOC↑ to data out (MSB) See Figure 7 400 ns Delay time, CS↓ to data out (MSB) See Figure 2 3.4 µs tPHZ, tPLZ tr(EOC) Delay time, CS↑ to data out (MSB) See Figure 2 150 ns Rise time See Figure 7 100 ns tf(EOC) tr(bus) Fall time See Figure 6 100 ns Data bus rise time See Figure 5 300 ns 128 10000011 (130) 10 ns tf(bus) Data bus fall time See Figure 5 300 ns † All typical values are at TA = 25°C NOTES: 2. Analog input voltages greater than that applied to REF + convert to all ones (11111111), while input voltages less than that applied to REF – convert to all zeros (00000000). For proper operation, REF + must be at least 1 V higher than REF –. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Zero-scale Error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between 11111111 and the converted output for full-scale input voltage. 7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. The A11 analog input signal is internally generated and is used for test purposes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 PARAMETER MEASUREMENT INFORMATION 1.4 V VCC 3 kΩ 3 kΩ Test Point Output Under Test Test Point Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR td, tr, AND tf Output Under Test Test Point CL (see Note A) 3 kΩ LOAD CIRCUIT FOR tPZH AND tPHZ LOAD CIRCUIT FOR tPZL AND tPLZ NOTE A: CL = 50 pF Figure 1. Load Circuits Address Valid 2V CS 0.8 V 2V 0.8 V An tPZH, tPZL tPHZ, tPLZ 2.4 V 90% 0.4 V 10% DATA OUT tsu(A) 2V I/O CLOCK Figure 3. Address Timing Figure 2. CS to Data Output Timing 2V CS 0.8 V tsu(CS) I/O CLOCK th(CS) 2V 8th Clock 0.8 V Figure 4. Figure 4. CS to I/O CLOCK Timing 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 th(A) TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 PARAMETER MEASUREMENT INFORMATION tr(I/O) tf(I/O) 2V 2V I/O CLOCK 0.8 V 0.8 V 0.8 V fclock(I/O) td(I/O-DATA) tv DATA OUT 2.4 V 2.4 V 0.4 V 0.4 V tr(bus), tf(bus) Figure 5. Data Output Timing I/O CLOCK 8th Clock 0.8 V td(I/O-EOC) 2.4 V EOC 0.4 V tf(EOC) Figure 6. EOC Timing tr(EOC) EOC 2.4 V 0.4 V td(EOC-DATA) 2.4 V DATA OUT 0.4 V Valid MSB Figure 7. Data Output to EOC Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 APPLICATION INFORMATION simplified analog input analysis Using the equivalent circuit in Figure 8, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by ( VC = VS 1– e – tc/RtCi ) (1) where Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS – (VS /512) (2) Equating equation 1 to equation 2 and solving for time tc gives ( VS – (VS/512) = VS 1– e – tc/RtCi ) (3) and tc (1/2 LSB) = Rt × Ci × ln(512) (4) Therefore, with the values given the time for the analog input signal to settle is tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(512) (5) This time must be less than the converter sample time shown in the timing diagrams. Driving Source† TLC542 Rs VS VI ri VC 1 kΩ MAX Ci 50 pF MAX VI = Input Voltage at INPUT A0 – A10 VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Input Capacitance † Driving source requirements: • Noise and distortion for the source must be equivalent to the resolution of the converter. • Rs must be real at the input frequency. Figure 8. Equivalent Input Circuit Including the Driving Source 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 PRINCIPLES OF OPERATION The TLC542 is a complete data acquisition system on a single chip. The device includes such functions as analog multiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic. Three control inputs (I/O CLOCK, CS (chip select), and ADDRESS INPUT) are included for flexibility and access speed. These control inputs and a TTL-compatible 3-state output are intended for serial communications with a microprocessor or microcomputer. With judicious interface timing, the TLC542 can complete a conversion in 20 µs, while complete input-conversion-output cycles can be repeated every 40 µs. Furthermore, this fast conversion can be executed on any of 11 inputs or its built-in self-test and in any order desired by the controlling processor. When CS is high, the DATA OUT terminal is in a 3-state condition, and the ADDRESS INPUT and I/O CLOCK terminals are disabled. When additional TLC542 devices are used, this feature allows each of these terminals, with the exception of the CS terminal, to share a control logic point with their counterpart terminals on additional A/D devices. Thus, this feature minimizes the control logic terminals required when using multiple A/D devices. The control sequence is designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is as follows: 1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and then a falling edge of the internal system clock before recognizing the low CS transition. The MSB of the result of the previous conversion automatically appears on the DATA OUT terminal. 2. On the first four rising edges of the I/O CLOCK, a new positive-logic multiplexer address is shifted in, with the MSB of this address shifted first. The negative edges of these four I/O CLOCK pulses shift out the second, third, fourth, and fifth most significant bits of the result of the previous conversion. The on-chip sample and hold begins sampling the newly addressed analog input after the fourth falling edge of the I/O CLOCK. The sampling operation basically involves charging the internal capacitors to the level of the analog input voltage. 3. Three clock cycles are applied to the I/O CLOCK terminal and the sixth, seventh, and eighth conversion bits are shifted out on the negative edges of these clock cycles. 4. The final eighth clock cycle is applied to the I/O CLOCK terminal. The falling edge of this clock cycle initiates a 12-system clock (≈ 12 µs) additional sampling period while the output is in the high-impedance state. Conversion is then performed during the next 20 µs. After this final I/O CLOCK cycle, CS must go high or the I/O CLOCK must remain low for at least 20 µs to allow for the conversion function. CS can be kept low during periods of multiple conversion. If CS is taken high, it must remain high until the end of conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion process. A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 20-µs conversion time has elapsed. Such action yields the conversion result of the previous conversion and not the ongoing conversion. The end-of-conversion (EOC) output goes low on the negative edge of the eighth I/O CLOCK. The subsequent low-to-high transition of EOC indicates the A/D conversion is complete and the conversion is ready for transfer. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075A – FEBRUARY 1989 – REVISED MARCH 1995 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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