TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 D D D D D D D Power Dissipation . . . 40 mW Max Advanced LinEPIC Single-Poly Process Provides Close Capacitor Matching for Better Accuracy Fast Parallel Processing for DSP and µP Interface Either External or Internal Clock Can Be Used Conversion Time . . . 6 µs Total Unadjusted Error . . . ±1 LSB Max CMOS Technology J† OR NW PACKAGE (TOP VIEW) REF+ REF – ANLG GND AIN ANLG VDD DGTL GND1 DGTL GND2 DGTL VDD1 DGTL VDD2 EOC D0 D1 description The TLC1550x and TLC1551 are data acquisition analog-to-digital converters (ADCs) using a 10-bit, switched-capacitor, successive-approximation network. A high-speed, 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor (µP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). Separate power terminals for the analog and digital portions minimize noise pickup in the supply leads. Additionally, the digital power is divided into two parts to separate the lower current logic from the higher current bus drivers. An external clock can be applied to CLKIN to override the internal system clock if desired. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 RD WR CLKIN CS D9 D8 D7 D6 D5 D4 D3 D2 † Refer to the mechanical data for the JW package. ANLG GND REF– REF+ NC RD WR CLKIN FK OR FN PACKAGE (TOP VIEW) AIN ANLG VDD DGTL GND1 NC DGTL GND2 DGTL VDD1 DGTL VDD2 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 CS D9 D8 NC D7 D6 D5 EOC D0 D1 NC D2 D3 D4 The TLC1550I and TLC1551I are characterized for operation from – 40°C to 85°C. The TLC1550M is characterized over the full military range of – 55°C to 125°C. 4 5 NC – No internal connection AVAILABLE OPTIONS PACKAGE TA CERAMIC CHIP CARRIER (FK) PLASTIC CHIP CARRIER (FN) CERAMIC DIP (J) PLASTIC DIP (NW) – 40°C to 85°C – TLC1550IFN TLC1551IFN – TLC1550INW – – 55°C to 125°C TLC1550MFK – TLC1550MJ – This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinEPIC is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 functional block diagram EOC CS SuccessiveApproximation Register Control Logic WR RD 10 D0 – D9 10 Frequency Divided by 2 DGTL VDD1 Internal Clock Comp 10-Bit Capacitor DAC and S/H 100 kΩ NOM Clock Detector CLKIN REF + REF – AIN typical equivalent inputs INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE 1 kΩ TYP AIN AIN Ci = 60 pF TYP (equivalent input capacitance) 2–2 POST OFFICE BOX 655303 5 MΩ TYP • DALLAS, TEXAS 75265 TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 Terminal Functions TERMINAL NO.† NAME DESCRIPTION NO.‡ ANLG GND 4 3 Analog ground. The reference point for the voltage applied on terminals ANLG VDD, AIN, REF+, and REF–. AIN 5 4 Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output. ANLG VDD 6 5 Analog positive power supply voltage. The voltage applied to this terminal is designated VDD3. CLKIN 26 22 Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high or left unconnected. CS 25 21 Chip-select. CS must be low for RD or WR to be recognized by the A/D converter. D0 13 11 Data bus output. D0 is bit 1 (LSB). D1 14 12 Data bus output. D1 is bit 2. D2 16 13 Data bus output. D2 is bit 3. D3 17 14 Data bus output. D3 is bit 4. D4 18 15 Data bus output. D4 is bit 5. D5 19 16 Data bus output. D5 is bit 6. D6 20 17 Data bus output. D6 is bit 7. D7 21 18 Data bus output. D7 is bit 8. D8 23 19 Data bus output. D8 is bit 9. D9 24 20 Data bus output. D9 is bit 10 (MSB). 7 6 Digital ground 1. The ground for power supply DGTL VDD1 and is the substrate connection. DGTL GND2 9 7 Digital ground 2. The ground for power supply DGTL VDD2. DGTL VDD1 10 8 Digital positive power-supply voltage 1. DGTL VDD1 supplies the logic. The voltage applied to DGTL VDD1 is designated VDD1. DGTL VDD2 11 9 Digital positive power-supply voltage 2. DGTL VDD2 supplies only the higher-current output buffers. The voltage applied to DGTL VDD2 is designated VDD2. EOC 12 10 End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred to the output latch. EOC can be connected to the µP- or DSP-interrupt terminal or can be continuously polled. RD 28 24 Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD resets EOC to a high within the td(EOC) specifications. REF+ 2 1 Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts to 1111111111. Analog input voltages between REF + and REF – convert to the appropriate result in a ratiometric manner. REF – 3 2 Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF – converts to 0000000000. 27 23 Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds the analog input until conversion is completed. Before and after the conversion period, which is given by t conv, the ADC remains in the sampling mode. DGTL GND1 WR † Terminal numbers for FK and FN packages. ‡ Terminal numbers for J and NW packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD1, VDD2, and VDD3 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Peak input current (any digital input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA Operating free-air temperature range, TA: TLC1550I, TLC1551I . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C TLC1550M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds: FK or FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: J or NW package . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: VDD1 is the voltage measured at DGTL VDD1 with respect to DGND1. VDD2 is the voltage measured at DGTL VDD2 with respect to the DGND2. VDD3 is the voltage measured at ANLG VDD with respect to AGND. For these specifications, all ground terminals are tied together (and represent 0 V). When VDD1, VDD2, and VDD3 are equal, they are referred to simply as VDD. recommended operating conditions Supply voltage, VDD1, VDD2, VDD3 MIN NOM MAX 4.75 5 5.5 Positive reference voltage, Vref+ (see Note 2) VDD3 0 Negative reference voltage, Vref– (see Note 2) Differential reference voltage, Vref+ – Vref – (see Note 2) 0.3 Analog input voltage range 0 High-level control input voltage, VIH 2 Low-level control input voltage, VIL Input clock frequency, f(CLKIN) 0.5 Setup time, CS low before WR or RD goes low, tsu(CS) Hold time, CS low after WR or RD goes high, th(CS) WR or RD pulse duration, tw(WR) Operating free-air free air temperature, temperature TA V V V 0.3 VDD3 V V V 0.8 V 7.8 MHz 0 ns 0 ns 50 ns 40% of period 80% of period TLC155xI – 40 85 TLC1550M – 55 125 Input clock low pulse duration, twL(CLKIN) UNIT °C NOTE 2: Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied to REF – convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V. 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 electrical characteristics over recommended operating free-air temperature range, VDD = Vref+ = 4.75 to 5.5 V and Vref – = 0 (unless otherwise noted) PARAMETER VOH TEST CONDITIONS High-level output voltage VDD = 4.75 V, IOH = – 360 µA TA = 25°C VOL Low level output voltage Low-level VDD = 4.75 V,, IOL = 2.4 mA IOZ Off state (high-impedance-state) (high impedance state) output current Off-state VO = VDD, VO = 0, IIH IIL High-level input current IIL Low-level input current (CLKIN) IOS Short circuit output current Short-circuit VO = 5 V, VO = 0, IDD Operating supply current CS low and RD high Ci Input capacitance Analog inputs Digital inputs TYP† 0.5 10 – 10 0.005 See typical equivalent inputs TLC1550/1I UNIT V 0.4 CS and RD at VDD TA = 25°C TA = 25°C MAX 2.4 TA = – 55°C to 125°C CS and RD at VDD VI = VDD VI = 0 Low-level input current (except CLKIN) MIN 2.5 V µA µA – 2.5 – 0.005 µA – 150 – 50 µA 7 14 – 12 –6 2 8 60 90* 5 15* mA mA pF * On products compliant to MIL-STD-883, Class B, this parameter is not production tested. † All typical values are at VDD = 5 V, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 operating characteristics over recommended operating free-air temperature range with internal clock and minimum sampling time of 4 µs, VDD = Vref + = 5 V and Vref – = 0 (unless otherwise noted) TLC1550I TA† Full range TLC1551I Full range PARAMETER EL Linearity error TEST CONDITIONS See Note 3 TLC1550I Zero scale error Zero-scale TLC1551I See Notes 2 and 4 Full scale error Full-scale Full range ±1 Full range ± 0.5 Full range ±1 ± 0.5 ±1 TLC1550I Full range ± 0.5 TLC1551I Full range See Notes 2 and 4 TLC1551I ±1 ± 0.5 25°C TLC1550I See Note 5 Full range ±1 Full range ± 0.5 Full range ±1 25°C ±1 TLC1550M fclock(external) = 4.2 MHz or internal clock tconv Conversion time ta(D) tv(D) Data access time after RD goes low tdis(D) ±1 ± 0.5 Full range TLC1550M Total unadjusted error MAX Data valid time after RD goes high See Figure 3 LSB LSB LSB LSB 6 µs 35 ns 5 Disable time, delay time from RD high to high impedance UNIT ± 0.5 25°C TLC1550M EFS TYP‡ 25°C TLC1550M EZS MIN ns 30 ns td(EOC) Delay time, RD low to EOC high 0 15 ns † Full range is – 40°C to 85°C for the TL155xI devices and – 55°C to 125°C for the TLC1550M. ‡ All typical values are at VDD = 5 V, TA = 25°C. NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied to REF – convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V. 3. Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value after zero-scale error and full-scale error have been removed. 4. Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale. Full-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale. 5. Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value. It includes contributions from zero-scale error, full-scale error, and linearity error. PARAMETER MEASUREMENT INFORMATION Source Current = 6 mA Test Point Output Under Test See Note A Vcp = 1 V CL = 62 pF Sink Current = 6 mA Vcp = voltage commutation point for switching between source and sink currents NOTE A: Equivalent load circuit of the Teradyne A500 tester for timing parameter measurement Figure 1. Test Load Circuit 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 APPLICATION INFORMATION simplified analog input analysis Using the circuit in Figure 2, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: ǒ Ǔ The capacitance charging voltage is given by V C + VS 1– e– tcńRtCi where (1) Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS – (VS /1024) (2) ǒ Ǔ Equating equation 1 to equation 2 and solving for time t c gives V and S * ǒ V Ǔ ń512 + VS 1– e– tcńRtCi S (3) t c (1/2 LSB) = Rt × Ci × ln(1024) (4) Therefore, with the values given, the time for the analog input signal to settle is t c (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(1024) (5) This time must be less than the converter sample time shown in the timing diagrams. Driving Source† TLC1550/1 Rs VS VI ri VC 1 kΩ MAX Ci 50 pF MAX VI = Input voltage at AIN VS = External driving source voltage Rs = Source resistance ri = Input resistance Ci = Input capacitance † Driving source requirements: • Noise and distortion for the source must be equivalent to the resolution of the converter. • Rs must be real at the input frequency. Figure 2. Input Circuit Including the Driving Source POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7 TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043C – MAY 1991 – REVISED MARCH 1995 PRINCIPLES OF OPERATION The operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550 and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder output to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low. Once CS is low, the on-board system clock permits the conversion to begin with a simple write command and the converted data to be presented to the data bus with a simple read command. The device remains in a sampling (track) mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode. After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, the end-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch. Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle. th(CS) tsu(CS) CS 0.8 V 1.4 V 0.8 V 0.8 V tconv tw(WR) WR 0.8 V 0.8 V 2V 1.4 V th(CS) tsu(CS) 2V RD 0.8 V tv(D) ta(D) 2V Data Valid 0.8 V D0 – D9 td(EOC) 2V EOC 0.8 V Figure 3. TLC1550 or TLC1551 Operating Sequence 2–8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tdis(D) 2V 0.8 V IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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