EMIF06-1005N12 6-line IPAD™, low capacitance EMI filter and ESD protection in Narrow Micro QFN package Features ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency in EMI filtering at frequencies from 900 MHz to 1.8 GHz ■ Very low PCB space consumption: 2.5 mm x 1.2 mm 12 1 Narrow Micro QFN 2.5 mm x 1.2 mm ■ Very thin package: 0.55 mm max ■ High efficiency in ESD suppression on inputs pins (IEC 61000-4-2 level 4) Figure 1. Pin configuration (top view) 1 Input Output 12 ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging 2 Input Output 11 ■ Lead-free package 3 Input Output 10 4 Input Output 9 5 Input Output 8 6 Input Output 7 Complies with the following standards ■ ■ IEC 61000-4-2 level 4 input and output pins – + 15 kV (air discharge) – + 8 kV (contact discharge) MIL STD 883G - Method 3015-7 Class 3B (all pins) Applications Figure 2. Where EMI filtering in ESD sensitive equipment is required: ■ LCD and camera for mobile phones ■ Computers and printers ■ Communication systems ■ MCU boards ■ Keypad for portable equipment TM: IPAD is a trademark of STMicroelectronics. January 2010 Basic cell configuration Input 100 Ω Output Typical line capacitance = 45 pF @ 0 V Description EMIF06-1005N12 is a 6-line, highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference.This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input pins. Doc ID 16959 Rev 1 1/12 www.st.com 12 Characteristics 1 EMIF06-1005N12 Characteristics Table 1. Absolute ratings (limiting values) Symbol VPP Tj Parameter and test conditions Unit 15 15 2 kV ESD discharge IEC 61000-4-2, level 4 air discharge contact discharge ESD-Machine Model : (MM: C = 200 pF, R = 25 Ω L = 500 nH) ESD-Charged Device Model: (JESD22-C101D) 1 Junction temperature at Tamb = 25 °C 125 °C Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C Figure 3. Symbol VBR VCL IRM VRM IF IPP IR VF Rd IPP RI/O Cline Table 2. Electrical characteristics (definitions) = = = = = = = = = = = = Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Forward current Peak pulse current Breakdown current Forward voltage drop Dynamic impedance Forward current Series resistanc between input and output Input capacitance per line I IF VF VCL VBR VRM V IRM IR IPP Electrical characteristics (Tamb = 25 °C) Symbol 2/12 Value Test conditions Min. Typ. Max. Unit VBR IR = 1 mA 6 8 10 V VF IF = 10 mA 0.5 1 1.5 V IRM VRM = 3 V per line 200 nA RI/O Tolerance ± 15% 85 100 115 Ω Cline Vline = 0 V, Vosc = 30 mV, F = 1 MHz 38 45 52 pF Doc ID 16959 Rev 1 EMIF06-1005N12 Figure 4. 0.0 Characteristics S21 attenuation measurement Figure 5. S21 (dB) Analog cross talk measurements 0.0 XTalk (dB) VBIAS = 0V - 10 VBIAS = 0V - 20 - 10 - 30 - 40 - 20 I2-O5 I2-O3 - 50 - 30 - 40 I2-O2 I4-O4 I1-O1 - 60 I3-O3 I5-O5 I6-O6 - 80 - 50 - 70 - 90 - 100 S21(dB) S21(dB) FC = 110 MHz F = 900 MHz F = 1.8 GHz - 60 300k Figure 6. 1M 3M 10M 30M F(Hz) 100M 300M 1G VCL max 27.2 V VCL @ t = 30 ns 4.6 V - 120 F(Hz) - 130 300k 3G ESD response to IEC 61000-4-2 (+8 kV contact discharge). Remaining voltage on filter output 5 V/Div OUTPUT - 110 -31 -35 Figure 7. 1M 3M 10M 30M 100M 300M 1G 3G ESD response to IEC 61000-4-2 (-8 kV contact discharge). Remaining voltage on filter output 5 V/Div VCL @ t = 100 ns 3.3 V C1 OUTPUT VCL max -20.7 V VCL @ t = 30 ns VCL @ t = 100 ns -3.2 V -787 mV C1 20 ns/Div Figure 8. 20 ns/Div ESD test conditions for figure 6 and figure 7 >500MHz Oscilloscope with 50 Ohm input mode D.U.T Attenuator 20…60dB 50 Ohm Doc ID 16959 Rev 1 3/12 Characteristics Figure 9. EMIF06-1005N12 ESD response to IEC 61000-4-2 (+15 kV air discharge) on one line Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge) on one line 5 V/Div 5 V/Div INPUT C2 INPUT C2 100 ns/Div 100 ns/Div 2 V/Div 2 V/Div C3 OUTPUT OUTPUT C3 100 ns/Div 100 ns/Div Figure 11. Line capacitance versus applied voltage 50 C(pF) 45 40 35 30 25 20 15 10 5 VR(V) 0 0 4/12 1 2 3 Doc ID 16959 Rev 1 4 5 6 EMIF06-1005N12 2 Ordering information scheme Ordering information scheme Figure 12. Ordering information scheme EMIF yy - xxx z Nx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package Nx = Narrow Micro QFN x leads Doc ID 16959 Rev 1 5/12 Package information 3 EMIF06-1005N12 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. Micro QFN 1.45x1.00 6L dimensions Dimensions D Ref. E A Millimeters Min. Typ. Max. Min. Typ. Max. 0.45 0.5 0.55 0.018 0.020 0.022 0.02 0.05 A1 TOP VIEW A Inches 0.0008 0.002 b 0.15 0.2 0.25 0.006 0.008 0.010 D 2.45 2.5 2.55 0.096 0.098 0.10 D2 1.75 1.8 1.85 0.069 0.071 0.73 E 1.15 1.2 1.25 0.045 0.047 0.050 E2 0.25 0.3 0.35 0.010 0.012 0.014 A1 SIDE VIEW e b PIN#1 ID E2 L e 0.4 0.016 D2 BOTTOM VIEW L Figure 13. Footprint recommendations 0.4 0.15 0.25 0.35 0.006 Figure 14. Marking 1.8 2.2 6/12 Doc ID 16959 Rev 1 KB 0.3 1.6 0.45 0.2 0.010 0.014 EMIF06-1005N12 Package information Figure 15. Flip-Chip tape and reel specification Ø 1.55 ± 0.05 2.0 ± 0.05 4.0 ± 0.1 1.75 ± 0.1 Dot identifying Pin A1 location 0.25 ± 0.02 8.0 ± 0.20 3.5 ±- 0.05 2.70 ±0.10 KB KB KB 1.40 ±0.10 4.0 ± 0.1 1.20 ± 0.10 All dimensions in mm Note: User direction of unreeling Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Doc ID 16959 Rev 1 7/12 Recommendation on PCB assembly EMIF06-1005N12 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 16. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 17. Recommended stencil window position 5 µm 5 µm 0.4 190 µ m 15 µ m 0.2 0.45 4 5 0 µm 4 2 0 µm 15 µ m 0.3 1.6 200 µ m 1 7 0 µm 3 0 0 µm 1800 µ m 100 µ m 8/12 65 µ m 1.8 2.2 65 µ m 1600 µ m Stencil Window 100 µ m Doc ID 16959 Rev 1 Footprint EMIF06-1005N12 4.2 4.3 4.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Doc ID 16959 Rev 1 9/12 Recommendation on PCB assembly 4.5 EMIF06-1005N12 Reflow profile Figure 18. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 10/12 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 16959 Rev 1 EMIF06-1005N12 5 Ordering information Ordering information Table 4. 6 Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF06-1005N12 KB Narrow µQFN 4.48 mg 3000 Tape and reel 7” Revision history Table 5. Document revision history Date Revision 12-Jan-2010 1 Changes Initial release. Doc ID 16959 Rev 1 11/12 EMIF06-1005N12 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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