STD90N02L STD90N02L-1 N-channel 25V - 0.0052Ω - 60A - DPAK - IPAK STripFET™ III Power MOSFET Features Type VDSS RDS(on) Max ID STD90N02L 25V <0.006Ω 60A STD90N02L-1 25V <0.006Ω 60A ■ RDS(ON) * Qg industry’s benchmark ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold device ■ In compliance with the 2002/95/ec european directive DPAK Application ■ 3 3 2 1 Figure 1. 1 IPAK Internal schematic diagram Switching applications Description This series of products utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved. Table 1. Device summary Order codes Marking Package Packaging STD90N02L-1 D90N02L IPAK Tube STD90N02L D90N02L DPAK Tape & reel November 2007 Rev 4 1/17 www.st.com 17 Contents STD90N02L - STD90N02L-1 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STD90N02L - STD90N02L-1 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Vspike (1) VDS VDGR Parameter Value Unit Drain-source voltage rating 30 V Drain-source voltage (VGS = 0) 25 V Drain-gate voltage (RGS = 20kΩ) 25 V ± 20 V VGS Gate-source voltage ID (2) Drain current (continuous) at TC = 25°C 60 A ID Drain current (continuous) at TC = 100°C 42 A IDM (3) Drain current (pulsed) 240 A PTOT Total dissipation at TC = 25°C 70 W Derating factor 0.47 W/°C EAS (4) Single pulse avalanche energy 360 mJ Tj Operating junction temperature Storage temperature -55 to 175 °C Value Unit Rthj-case Thermal resistance junction-case max. 2.14 °C/W Rthj-amb Thermal resistance junction-amb max. 100 °C/W 275 °C Tstg 1. Guaranteed when external Rg=4.7Ω and Tf<Tfmax 2. Value limited by wire bonding 3. Pulse width limited by safe operating area 4. Starting Tj = 25°C, ID = 30A, VDD = 15V Table 3. Symbol Tl Thermal data Parameter Maximum lead temperature for soldering purpose 3/17 Electrical characteristics 2 STD90N02L - STD90N02L-1 Electrical characteristics (Tcase =25°C unless otherwise specified) Table 4. Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown ID = 25mA, VGS= 0 voltage Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ±20V VGS(th) Gate threshold voltage VDS= VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS= 5V, ID= 15A Symbol gfs (1) Ciss Coss Crss Qg 1 Unit V 1 10 µA µA ±100 nA 1.8 V 0.0052 0.006 0.007 0.011 Ω Ω Dynamic Parameter Test conditions Forward transconductance VDS =10V, ID = 18A Input capacitance Output capacitance Reverse transfer capacitance VDS =16V, f=1MHz, VGS=0 Min. VDD=10V, ID = 60A Qgd RG Gate input resistance f=1MHz Gate DC Bias =0 test signal level =20mV open drain Output charge VDS =10V, VGS =0V (see Figure 17) Pulsed: pulse duration = 300µs, duty cycle 1.5% 2. Qoss.= Coss * D Vin, Coss = Cgd + Cgd. (see Buck converter) 4/17 Max. 25 VGS= 10V, ID= 30A VGS =5V QOSS(2) Typ. VDS = 20V,Tc = 125°C Total gate charge Gate-source charge Gate-drain charge Qgs Min. VDS = 20V, IDSS Table 5. 1. On /off states 0.5 Typ. Max. Unit 27 S 2050 545 70 pF pF pF 17 7.7 3.5 22 nC nC nC 1.5 3 Ω 14 nC STD90N02L - STD90N02L-1 Electrical characteristics Table 6. Switching times Symbol Parameter td(on) tr td(off) tf Table 7. Turn-on delay time Rise time Turn-off delay time Fall time Parameter ISD Source-drain current Source-drain current (pulsed) VSD (1) trr Qrr IRRM Min. Typ. Max Unit 12 110 18 8 VDD=10V, ID=30A, RG=4.7Ω, VGS=5V (see Figure 16) ns ns ns ns Source drain diode Symbol ISDM Test conditions Test conditions Forward on voltage ISD=30A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD=60A, di/dt = 100A/µs, VDD=15V, Tj=150°C (see Figure 18) Min. Typ. 36 65 3.6 Max. Unit 60 240 A A 1.3 V ns nC A 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% 5/17 Electrical characteristics STD90N02L - STD90N02L-1 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance 6/17 STD90N02L - STD90N02L-1 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Figure 12. Source-drain diode forward characteristics Figure 13. Normalized BVDSS vs temperature 7/17 Electrical characteristics STD90N02L - STD90N02L-1 Figure 14. Allowable IAV vs time in avalanche The previous curve gives the single pulse safe operating area for unclamped inductive loads, under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV) EAS(AR) =PD(AVE) *tAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tAV is the time in avalanche 8/17 STD90N02L - STD90N02L-1 3 Buck converter Buck converter Figure 15. Synchronous buck converter The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: Very low RDS(on) to reduce conduction losses Small QGLS to reduce the gate charge losses Small COSS to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon. The high side (SW1) device requires: Small RG and LG to allow higher gate current peak and to limit the voltage feedback on the gate Small QG to have a faster commutation and to reduce gate charge losses Low RDS(on) to reduce the conduction losses 9/17 Buck converter STD90N02L - STD90N02L-1 Table 8. Power losses High side switch (SW1) Low side switch (SW2) 2 R DS ( on ) • I L • δ Pconduction Pswitching in 2 R DS ( on ) • I L • ( 1 – δ) I • ( Q gsth ( SW1 ) + Q gd ( SW1 ) ) • f • I recovery Not applicable conduction Not applicable Zero voltage switching 1 Vin • Q rr ( SW2 ) • f Pdiode Pgate(Qg) Q g ( SW1 ) • V gg • f PQoss V in • Q oss ( SW1 ) • f -------------------------------------------------2 Table 9. Q gls ( SW2 ) • V gg • f V in • Q oss ( SW2 ) • f ------------------------------------------------2 Power losses parameters Parameter 10/17 V f ( SW2 ) • I L • t deadtime • f Meaning d Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction On state losses Pswitching On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate driver losses PQoss Output capacitance losses STD90N02L - STD90N02L-1 4 Test circuits Test circuits Figure 16. Switching times test circuit for resistive load Figure 17. Gate charge test circuit Figure 18. Test circuit for inductive load Figure 19. Unclamped inductive load test switching and diode recovery times circuit Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform 11/17 Package mechanical data 5 STD90N02L - STD90N02L-1 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:www.st.com 12/17 STD90N02L - STD90N02L-1 Package mechanical data TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 B5 0.033 0.3 0.012 B6 0.95 C 0.45 C2 0.48 D 6 E 6.4 6.6 0.037 0.6 0.017 0.023 0.6 0.019 0.023 6.2 0.236 0.244 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A1 C2 A3 A C H B B3 = 1 = 2 G = = = E B2 = 3 B5 L D B6 L2 L1 0068771-E 13/17 Package mechanical data STD90N02L - STD90N02L-1 DPAK MECHANICAL DATA mm. inch DIM. MIN. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 TYP 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 MAX. MIN. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 6.6 0.252 5.1 6.4 0.260 0.090 4.6 10.1 0.173 0.368 0.039 2.8 0.8 0.181 0.397 0.110 0.031 1 0.023 0.2 0° 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.185 2.28 0.6 MAX. 0.200 4.7 4.4 9.35 1 TYP. 0.039 0.008 8° 0° 8° 0068772-F 14/17 STD90N02L - STD90N02L-1 6 Package mechanical data Package mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 D 1.5 D1 1.5 E 1.65 MIN. 12.1 0.476 1.6 0.059 0.063 1.85 0.065 0.073 7.4 7.6 0.291 0.299 2.55 2.75 0.100 0.108 0.153 0.161 P0 3.9 4.1 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 40 15.7 MAX. 330 12.992 13.2 0.504 0.520 18.4 0.645 0.724 0.059 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 0.059 F R MIN. MAX. K0 W inch MAX. 1.574 16.3 0.618 0.641 15/17 Revision history 7 STD90N02L - STD90N02L-1 Revision history Table 10. 16/17 Document revision history Date Revision Changes 29-Aug-2005 1 First release 07-Apr-2006 2 New template 03-May-2006 3 New value on Table 4, new curve (see Figure 14) 24-Oct-2007 4 Corrected value on Table 6, Updated BVdss value STD90N02L - STD90N02L-1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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