STP60NH2LL N-channel 24V - 0.010Ω - 40A TO-220 STripFET™ Power MOSFET General features Type VDSS (@Tjmax) RDS(on) ID STP60NH2LL 24V <0.011Ω 40A(1) 1. Value limited by wire bonding ■ RDS(ON) * Qg industry’s benchmark ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold device 3 1 2 TO-220 Description The STP60NH2LL utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STP60NH2LL P60NH2LL TO-220 Tube January 2007 Rev 3 1/14 www.st.com 14 Contents STP60NH2LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 ................................................ 8 STP60NH2LL 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit Vspike(1) Drain-source Voltage Rating 30 V VDS Drain-source voltage (VGS = 0) 24 V VGS Gate-source voltage ±18 V ID Drain current (continuous) at TC = 25°C 40 A ID Drain current (continuous) at TC=100°C 28 A Drain current (pulsed) 160 A Total dissipation at TC = 25°C 60 W Derating factor 0.4 W/°C Single pulse avalanche energy 600 mJ -55 to 175 °C Thermal resistance junction-case Max 2.5 °C/W Rthj-a Thermal resistance junction-ambient Max 100 °C/W Tl Maximum lead temperature for soldering purpose 275 °C IDM (2) PTOT EAS(3) Tstg Tj Storage temperature Max. operating junction temperature 1. Guaranteed when external Rg=4.7 Ω and tf < tfmax 2. Pulse width limited by safe operating area 3. Starting Tj = 25 oC, ID = 20A, VDD = 15V Table 2. Rthj-case Thermal data 3/14 Electrical characteristics 2 STP60NH2LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol On/off states Parameter Test conditions Drain-source breakdown voltage ID = 25 mA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max rating, VDS = Max rating TC=125°C IGSS Gate body leakage current (VDS = 0) VGS = ±16V VGS(th) Gate threshold voltage VDS= VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS= 10V, ID= 20A VGS= 4.5V, ID= 20A V(BR)DSS Table 4. Symbol (1) Typ. Max. 24 Unit V 1 10 µA µA ± 100 nA 1 V 0.010 0.011 0.012 0.0135 Ω Dynamic Parameter Test conditions Min. Typ. Max. Unit Forward transconductance VDS = 10V, ID = 10A 18 S Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS =25V, f=1 MHz, VGS=0 990 385 40 pF pF pF td(on) tr td(off) tf Turn-on delay time rise time Turn-off delay time fall time VDD = 10 V, ID = 20 A RG = 4.7 Ω, VGS = 4.5 V (see Figure 13) 5 56 13 10 ns ns ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge 0.44 ≤VDD=10V, ID = 40A VGS =4.5V 8.7 4.2 2.4 Output charge VDS= 16 V, VGS= 0 V 7.6 nC Gate input resistance f=1MHz Gate DC Bias=0 test signal level=20mV open drain 1.3 Ω gfs Qoss(2) Rg 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 2. Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Chapter 4: Appendix A 4/14 Min. 27 nC nC nC STP60NH2LL Electrical characteristics Table 5. Symbol ISD ISDM VSD(1) trr Qrr IRRM Source drain diode Parameter Max Unit Source-drain current 40 A Source-drain current (pulsed) 160 A 1.3 V Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Test conditions Min. Typ. ISD=20A, VGS=0 ISD=40A, di/dt = 100A/µs, VDD=15V, Tj=150°C (see Figure 15) 32.5 28 1.7 ns µC A 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/14 Electrical characteristics STP60NH2LL 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/14 STP60NH2LL Electrical characteristics Figure 7. Gate charge vs. gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs. temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs. temperature Figure 12. Normalized Breakdown Voltage vs. Temperature 7/14 Test circuit 3 STP60NH2LL Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/14 Figure 18. Switching time waveform STP60NH2LL 4 Appendix A Appendix A Figure 19. Buck converter: power losses estimation The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. ● The low side (SW2) device requires: ● Very low RDS(on) to reduce conduction losses ● Small Qgls to reduce the gate charge losses ● Small Coss to reduce losses due to output capacitance ● Small Qrr to reduce losses on SW1 during its turn-on ● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source ● voltage to avoid the cross conduction phenomenon; ● The high side (SW1) device requires: ● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate ● Small Qg to have a faster commutation and to reduce gate charge losses ● Low RDS(on) to reduce the conduction losses. 9/14 Appendix A STP60NH2LL Table 6. Power losses calculation High side switching (SW1) Low side switch (SW2) R DS(on)SW1 * I 2L * δ R DS(on)SW2 * I 2L * (1 − δ ) Pconduction Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * Pswitching Recovery (1) Not applicable Conductio n Not applicable IL Ig Zero Voltage Switching Vin * Q rr(SW2) * f Pdiode Vf(SW2) * I L * t deadtime * f Pgate(QG) Q g(SW1) * Vgg * f Q gls(SW2) * Vgg * f PQoss Vin * Q oss(SW1) * f Vin * Q oss(SW2) * f 2 2 1. Dissipated by SW1 during turn-on Table 7. Parameters meaning Parameter d Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction Pswitching 10/14 Meaning On state losses On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate drive losses PQoss Output capacitance losses STP60NH2LL 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/14 Package mechanical data STP60NH2LL TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 12/14 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STP60NH2LL 6 Revision history Revision history Table 8. Revision history Date Revision Changes 31-May-2005 1 First release. 06-Sep-2006 2 The document has been reformatted. 31-Jan-2007 3 Typo mistake on Table 1. 13/14 STP60NH2LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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