STD95NH02L N-channel 24V - 0.005239Ω - 80A - DPAK Ultra low gate charge STripFET™ Power MOSFET General features Type VDSS RDS(on) ID STD95NH02L 24V <0.005Ω 80A(1) 1. Value limited by wire bonding ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold device 3 1 DPAK Description The device is based on the latest generation of ST’s proprietary STripFET™ technology. An innovative layout enables the device to also exhibit extremely low gate charge for the most demanding requirements in high-frequency DCDC converters. It’s therefore ideal for high-density converters in Telecom and Computer applications. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STD95NH02LT4 D95NH02L DPAK Tape & reel August 2006 Rev 3 1/15 www.st.com 15 Contents STD95NH02L Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 ................................................ 8 STD95NH02L 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Vspike (1) VDS VDGR VGS ID (2) ID(2) IDM (3) PTOT EAS (4) Tj Tstg Value Unit Drain-source voltage rating 30 V Drain-source voltage (VGS = 0) 24 V Drain-gate voltage (RGS = 20kΩ) 24 V ± 20 V Drain current (continuous) at TC = 25°C 80 A Drain current (continuous) at TC = 100°C 68 A Drain current (pulsed) 320 A Total dissipation at TC = 25°C 100 W Derating factor 0.67 W/°C Single pulse avalanche energy 600 mJ Operating junction temperature Storage temperature -55 to 175 °C Gate-source voltage 1. Guaranted when external Rg= 4.7Ω and Tf < Tfmax 2. Value limited by wire bonding 3. Pulse width limited by safe operating area 4. Starting Tj =25°C, Id = 40A, Vdd = 22V Table 2. Thermal data Rthj-case Thermal resistance junction-case max 1.5 °C/W Rthj-amb Thermal resistance junction-to ambient max 100 °C/W Maximum lead temperature for soldering purpose 275 °C TJ 3/15 Electrical characteristics 2 STD95NH02L Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage ID = 250µA, VGS =0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 20V VDS = 20V, TC = 125°C IGSS Gate-body leakage current (VDS = 0) VGS = ± 20V VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V, ID = 40A VGS = 5V, ID = 40A Table 4. Symbol Test conditions Typ. Max. 24 Unit V 1 10 µA µA ±100 nA 1 V 0.0039 0.0055 0.005 0.009 Ω Ω Typ. Max. Unit Dynamic Parameter Test conditions Min. gfs (1) Forward transconductance VDS = 10V, ID = 10A 30 S Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 15V, f = 1MHz, VGS = 0 2070 990 90 pF pF pF td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 12V, ID = 40A RG = 4.7Ω VGS = 10V (see Figure 13) 20 110 47 20 ns ns ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 12V, ID = 80A, VGS = 5V, RG = 4.7Ω (see Figure 14) 17 7.6 6.8 nC nC nC Qoss(2) Output charge VDS =19V, VGS =0V 22.6 nC Qgls(3) Third-quadrant gate chatge VDS < 0V, VGS = 5V 15 nC Gate Input Resistance f=1MHz Gate DC Bias =0 Test Signal Level =20mV Open Drain 1.8 Ω RG 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Qoss.= Coss * ∆ Vin, Coss = Cgd + Cgd. See Chapter 4: Appendix A 3. Gate charge for synchronous operation 4/15 Min. STD95NH02L Electrical characteristics Table 5. Symbol Source drain diode Parameter ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD trr Qrr IRRM Test conditions Min. Typ. ISD = 40A, VGS = 0 Reverse recovery time ISD = 80A, di/dt = 100A/µs, Reverse recovery charge VDD = 20V, Tj = 150°C Reverse recovery current (see Figure 15) 42 50.4 2.4 Max. Unit 80 320 A A 1.3 V ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 5/15 Electrical characteristics STD95NH02L 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/15 STD95NH02L Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized BVDSS vs temperature 7/15 Test circuit 3 STD95NH02L Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/15 Figure 18. Switching time waveform STD95NH02L 4 Appendix A Appendix A Figure 19. Buck converter: power losses estimation The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. ● The low side (SW2) device requires: ● Very low RDS(on) to reduce conduction losses ● Small Qgls to reduce the gate charge losses ● Small Coss to reduce losses due to output capacitance ● Small Qrr to reduce losses on SW1 during its turn-on ● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source ● voltage to avoid the cross conduction phenomenon; ● The high side (SW1) device requires: ● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate ● Small Qg to have a faster commutation and to reduce gate charge losses ● Low RDS(on) to reduce the conduction losses. Table 6. Power losses calculation Pconduction Pswitching High side switching (SW1) Low side switch (SW2) R DS(on)SW1 * I 2L * δ R DS(on)SW2 * I 2L * (1 − δ ) Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * IL Ig Zero Voltage Switching 9/15 Appendix A STD95NH02L Table 6. Power losses calculation High side switching (SW1) Low side switch (SW2) (1) Not applicable Vin * Q rr(SW2) * f Conductio n Not applicable Vf(SW2) * I L * t deadtime * f Pgate(QG) Q g(SW1) * Vgg * f Q gls(SW2) * Vgg * f PQoss Vin * Q oss(SW1) * f Vin * Q oss(SW2) * f 2 2 Recovery Pdiode 1. Dissipated by SW1 during turn-on Table 7. Paramiters meaning Parameter d Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction Pswitching 10/15 Meaning On state losses On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate drive losses PQoss Output capacitance losses STD95NH02L 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/15 Package mechanical data STD95NH02L DPAK MECHANICAL DATA mm. inch DIM. MAX. MIN. A A1 A2 B b4 MIN. 2.2 0.9 0.03 0.64 5.2 TYP 2.4 1.1 0.23 0.9 5.4 0.086 0.035 0.001 0.025 0.204 0.094 0.043 0.009 0.035 0.212 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 0.45 0.48 6 0.6 0.6 6.2 0.017 0.019 0.236 0.023 0.023 0.244 6.6 0.252 5.1 6.4 0.173 0.368 0.039 2.8 0.8 0.181 0.397 0.110 0.031 1 0.023 0.2 0° 0.260 0.185 0.090 4.6 10.1 0.6 MAX. 0.200 4.7 2.28 4.4 9.35 1 TYP. 0.039 0.008 8° 0° 8° 0068772-F 12/15 STD95NH02L 6 Packing mechanical data Packing mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 D 1.5 D1 1.5 E 1.65 MIN. 12.1 0.476 1.6 0.059 0.063 1.85 0.065 0.073 7.4 7.6 0.291 0.299 2.55 2.75 0.100 0.108 0.153 0.161 P0 3.9 4.1 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 40 15.7 MAX. 330 12.992 13.2 0.504 0.520 18.4 0.645 0.724 0.059 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 0.059 F R MIN. MAX. K0 W inch MAX. 1.574 16.3 0.618 0.641 13/15 Revision history 7 STD95NH02L Revision history Table 8. 14/15 Revision history Date Revision Changes 13-Sep-2004 1 First release 27-May-2005 2 Some values changed in Table 4: Dynamic. 09-Aug-2006 3 New template, no content change STD95NH02L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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