TI TPS53314RGFT

TPS53314
SLUSAK3 – MAY 2011
www.ti.com
6-A Step-Down Regulator with Integrated Switcher
Check for Samples: TPS53314
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
EN
31
30
29
28
27
26
25
24
23
22
21
LL
LL
LL
LL
PGOOD
32
LL
VREG
The TPS53314 is available in a 5 mm × 7 mm 40-pin,
QFN package and is specified from –40°C to 85°C.
LL
•
•
•
The conversion input voltage ranges from 3 V to
15 V, the supply voltage range is from 4.5 V to 25 V,
and the output voltage range is from 0.6 V to 5.5 V.
LL
•
This device features single-rail input support, one
20-mΩ and one 7.5-mΩ integrated MOSFET,
accurate 1%, 0.6 V Reference, and integrated boost
switch. A sample of competitive features include:
greater than 96% maximum efficiency, 3 V to 15 V
wide input voltage range, very low external
component count, D-CAP™ mode control for super
fast transient, selectable auto-skip and PWM
operation, internal soft-start control, adjustable
frequency, and no need for compensation.
LL
•
•
•
TPS53314 is a D-CAP™ mode, 6-A synchronous
switcher with integrated MOSFETs. It is designed for
ease of use, low external component count, and
small package power systems.
N/C
•
•
DESCRIPTION
VBST
•
•
Server and Desktop Computers
Notebook Computers
Telecommunication Equipments
N/C
•
•
Conversion Input Voltage Range: 3 V to 15 V
VDD Input Voltage Range: 4.5 V to 25 V
Output Voltage Range: 0.6 V to 5.5 V
5-V LDO Output
Integrated Power MOSFETs with 6-A
Continuous Output Current
<10-μA Shut Down Current
Auto-Skip Eco-mode™ for Light-Load
Efficiency
D-CAP™ Mode with Fast Transient Response
Selectable Switching Frequency from 250 kHz
to 1 MHz with an External Resistor
Built-in 1%, 0.6-V Reference
0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms Selectable
Internal Voltage Servo Soft-Start
Pre-Charged Start-up Capability
Integrated Boost Switch
Adjustable Overcurrent Limit Via External
Resistor
Overvoltage/Undervoltage, UVLO and
Over-Temperature Protection
Support All Ceramic Output Capacitors
Open Drain Power Good Indication
40-pin QFN Package with PowerPAD™
PGOOD
2
VOUT
LL 20
33
N/C
34
N/C
LL 19
35
TRIP
LL 18
36
EN
LL 17
TPS53314
LL 16
VFB
38
RF
VIN 15
39
MODE
VIN 14
40
VDD
VREG
GND2
PGND
PGND
PGND
PGND
PGND
PGND
VIN
VIN
1
2
3
4
5
6
7
8
9
10
11
12
VDD
4.5 V to 25 V
VIN
3 V to 15 V
VIN 13
PGND
GND1
37
Pad
UDG-11138
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Eco-mode, D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
PACKAGE
–40°C to 85°C
Plastic QFN
(RGF)
(1)
ORDERING
NUMBER
PINS
TRANSPORT
MEDIA
MINIMUM
QUANTITY
TPS53314RGFR
40
Tape and reel
3000
TPS53314RGFT
40
Mini reel
250
ECO PLAN
Green (RoHS and
no Pb/Br)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
Input voltage range
VIN (main supply)
–0.3 to 17
VDD
–0.3 to 28
VBST
–0.3 to 24
VBST(with respect to LL)
–0.3 to 7
EN, TRIP, VFB, RF, MODE
–0.3 to 7
LL
Output voltage range
V
–1 to 23
DC
Pulse < 20 ns, E = 5 μJ
–7
–0.3 to 7
PGOOD, VREG
V
–0.3 to 0.3
PGND
Source/Sink Current
UNIT
VBST
50
mA
Operating free-air temperature, TA
–40 to 85
°C
Storage temperature range, Tstg
–55 to 150
°C
Junction temperature range, TJ
–40 to 150
°C
300
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS53314
RGF(40 PINS)
θJA
Junction-to-ambient thermal resistance
35.8
θJCtop
Junction-to-case (top) thermal resistance
23.8
θJB
Junction-to-board thermal resistance
10.1
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
10.0
θJCbot
Junction-to-case (bottom) thermal resistance
2.8
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
VALUE
VIN (main supply)
Input voltage range
Output voltage range
Source/Sink Current
VDD
4.5 to 25
VBST
4.5 to 21
VBST(with respect to LL)
4.5 to 6.5
EN, TRIP, VFB, RF, MODE
–0.1 to 6.5
LL
–0.8 to 15
PGOOD, VREG
–0.1 to 6.5
VBST
Junction temperature range, TJ
Copyright © 2011, Texas Instruments Incorporated
UNIT
3 to 15
V
V
50
mA
–40 to 125
°C
3
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VDD = 12 V (Unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND SUPPLY CURRENT
VVIN
VIN pin power conversion input
voltage
VDD
Supply input voltage
IVIN(leak)
VIN pin leakage current
VEN = 0 V
IVDD
VDD supply current
VDD current, TA = 25°C, No Load, VEN = 5 V,
VVFB = 0.630 V
IVDDSDN
VDD shutdown current
VDD current, TA = 25°C, No Load, VEN = 0 V
3
15
V
4.5
25
V
1
µA
590
µA
10
µA
420
INTERNAL REFERENCE VOLTAGE
VFB voltage, CCM condition (1)
VVFB
VFB regulation voltage
0.6000
TA = 25°C
TA = 0°C to 85°C
TA = -40°C to 85°C
IVFB
VFB input current
V
0.597
0.600
0.603
0.5952
0.600
0.6048
0.594
0.600
0.606
0.002
0.2
5.0
5.35
VVFB = 0.630 V, TA = 25°C
V
µA
LDO OUTPUT
VVREG
LDO output voltage
0 mA ≤ IVREG ≤ 30 mA
IVREG
LDO output current (1)
Maximum current allowed from LDO
VDO
LDO drop out voltage
VDD = 4.5 V, IVREG = 30 mA
4.77
V
30
mA
295
mV
BOOT STRAP SWITCH
VFBST
Forward voltage
VVREG-VBST, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakage current
VVBST = 23 V, VLL = 17 V, TA = 25°C
0.1
0.2
V
0.01
1.5
µA
260
400
DUTY AND FREQUENCY CONTROL
tOFF(min)
tON(min)
Minimum off time
TA = 25°C
Minimum on time
VVIN = 17 V, VOUT = 0.6 V, RRF = 0 Ω to VREG,
TA = 25°C (1)
150
35
RMODE = 39 kΩ
0.7
RMODE = 100 kΩ
1.4
RMODE = 200 kΩ
2.8
RMODE = 470 kΩ
5.6
ns
SOFTSTART
Internal SS time from VOUT = 0 to
VOUT = 95%
tSS
ms
POWERGOOD
VTHPG
PG threshold
PG in from lower
92.5%
PG in from higher
107.5%
PG hysteresis
96%
98.5%
110% 112.5%
2.5%
5%
7.8%
RPG
PG transistor on-resistance
15
30
55
Ω
tPGDEL
PG Delay after soft-start
0.8
1
1.2
ms
(1)
4
Ensured by design. Not production tested.
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VDD = 12 V (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD AND SETTING CONDITIONS
VEN
EN voltage threshold
IEN
EN input current
Enable
1.8
0.6
VEN = 5 V
1.0
RRF = 0 Ω to GND, TA = 25°C
fSW
Switching frequency
V
Disable
(1)
200
250
300
RRF = 187 kΩ to GND, TA = 25°C (1)
250
300
350
RRF = 619 kΩ to GND, TA = 25°C (1)
350
400
450
RRF = Open, TA = 25°C
(1)
450
500
550
RRF = 866 kΩ to VREG, TA = 25°C (1)
580
650
720
RRF = 309 kΩ to VREG, TA = 25°C (1)
670
750
820
(1)
RRF = 124 kΩ to VREG, TA = 25°C
770
850
930
RRF = 0 Ω to VREG, TA = 25°C (1)
880
970
1070
VTRIP = 1 V, TA = 25°C
9.4
10.0
10.6
µA
kHz
PROTECTION: CURRENT SENSE
ITRIP
TRIP source current
(2)
TCITRIP
TRIP current temperature coefficent
On the basis of 25°C
VTRIP
Current limit threshold setting range
VTRIP-GND voltage
0.2
VTRIP = 0.6 V
67
VOCL
Current limit threshold
VOCLN
Negative current limit threshold
VAZCADJ
Auto zero cross adjustable range
VTRIP = 0.2
4700
ppm/°C
0.6
75
19
26
33
–83
–75
–67
VTRIP = 0.2 V
–33
–26
–19
3
V
83
VTRIP = 0.6 V
Positive
µA
15
mV
mV
–15
–3
115%
120%
125%
65%
70%
75%
0.8
1
1.2
ms
2.0
2.6
3.2
ms
4.00
4.20
4.32
Negative
PROTECTION: UVP and OVP
VOVP
OVP trip threshold
OVP detect
tOVPDEL
OVP propagation delay time
VFB delay with 50-mV overdrive
VUVP
Output UVP trip threshold time
UVP detect
tUVPDEL
Output UVP propagation delay time
tUVPEN
Output UVP enable delay time
from EN to UVP workable, RMODE = 39 kΩ
µs
1
UVLO
VUVVREG
VREG UVLO threshold
Wake up
Hysteresis
0.25
Shutdown temperature (2)
145
V
THERMAL SHUTDOWN
TSDN
(1)
(2)
Thermal shutdown threshold
Hysteresis (2)
10
°C
Not production tested. Test condition is VIN = 12 V, VOUT= 1.1 V, IOUT= 5 A using application circuit shown in Figure 33.
Ensured by design. Not production tested.
Copyright © 2011, Texas Instruments Incorporated
5
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
0.6 V +10/15%
0.6 V –30%
+
UV
PGOOD
+
Delay
Delay
+
0.6 V –10/15%
Ramp
Compensation
Control Logic
+
+20%
+
VFB
OV
UVP/OVP
Logic
RF
VBST
0.6 V
SS
10 ?A
VREG
GND
TRIP
+
+ PWM
VIN
tON
OneShot
+
+ OCP
LL
LL
XCON
+
ZC
PGND
Control
Logic
PGND
SS
FCCM/
Skip
Decode
MODE
EN
·
·
·
·
·
On/Off time
Minimum On /Off
Light load
OVP/UVP
FCCM/Skip
LL
Fault
Sdn
VREG
+
LDO
VDD
V5OK
+
4.2 V/3.95 V
Enable
1.2 V/0.95 V
+
THOK
EN
145°C/
135°C
TPS53314
UDG-11139
6
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
PIN CONFIGURATION
PGOOD
N\C
VBST
N/C
LL
LL
LL
LL
LL
LL
LL
LL
TPS53314
RGF-40
(TOP VIEW)
32
31
30
29
28
27
26
25
24
23
22
21
N/C
33
20
LL
N/C
34
19
LL
TRIP
35
18
LL
EN
36
17
LL
TPS53314
VDD
40
13
VIN
1
2
3
4
5
6
7
8
9
10
11
12
VIN
VIN
VIN
14
PGND
39
PGND
MODE
PGND
VIN
PGND
15
PGND
38
PGND
RF
GND2
LL
VREG
16
PGND
37
GND1
VFB
PIN DESCRIPTIONS
PIN
NAME
NO.
I/O/P (1)
DESCRIPTION
EN
36
I
Enable pin.
GND1
1
G
GND for controller
GND2
4
G
GND for half-bridge
B
Output of converted power. Connect this pin to the output Inductor.
I
Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The soft-start
time is detected and stored into internal register during start-up.
16
17
18
19
20
21
LL
22
23
24
25
26
27
28
MODE
(1)
39
I=Input, O=Output, B=Bidirectional, P=Supply, G=Ground
Copyright © 2011, Texas Instruments Incorporated
7
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
PIN DESCRIPTIONS (continued)
PIN
NAME
NO.
I/O/P (1)
DESCRIPTION
29
N/C
31
No connection
33
34
PGOOD
32
O
Open drain power good flag. Provides a 1-ms start up delay after the VFB pin voltage falls within
specified limits. When the VFB pin voltage goes outside the specified limits, the PGOOD pin goes low
within 10 µs.
G
Power GND
Switching frequency selection. Connect a resistance to GND or VREG to select switching frequency using
Table 2. The switching frequency is detected and stored during the startup.
2
5
6
PGND
7
8
9
10
RF
38
I
TRIP
35
I
OCL detection threshold setting pin. 10 µA at room temperature, 4700 ppm/°C current is sourced and set
the OCL trip voltage as follows.
space VOCL = VTRIP/8
( VTRIP ≤ 0.6 V, VOCL ≤ 75 mV)
VBST
30
P
Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL-node.
Internally connected to the VREG pin via bootstrap MOSFET switch.
VDD
40
P
Controller power supply input.
VFB
37
I
Output feedback input. Connect this pin to VOUT through a resistor divider.
P
Conversion power input.
11
12
VIN
13
14
15
VREG
3
P
5-V LDO output.
Pad
–
–
Package thermal pad. Use proper number of vias to connect to GND plane for heat dissipation.
8
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
6
600
5
VDD Shutdown Current (µA)
VDD Supply Current (µA)
TYPICAL CHARACTERISTICS
700
500
400
300
200
VEN = 5 V
VVDD = 12 V
VVFB = 0.63 V
No Load
100
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
3
2
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 2. VDD Shutdown Current vs. Temperature
16
140
15
120
TRIP Pin Current (µA)
14
100
80
60
40
13
12
11
10
9
8
20
0
−40 −25 −10
OVP
UVP
5
20 35 50 65
Temperature (°C)
80
95
7
VVDD = 12 V
6
−40 −25 −10
110 125
Figure 3. OVP/UVP Trip Threshold vs. Temperature
5
20 35 50 65
Temperature (°C)
80
110 125
Switching Frequency (kHz)
1000
100
fSET = 300 kHz
VIN = 12 V
VOUT = 1.1 V
10
100
fSET = 500 kHz
VIN = 12 V
VOUT = 1.1 V
10
FCCM
Skip Mode
1
0.01
95
Figure 4. Trip Pin Current vs. Temperature
1000
Switching Frequency (kHz)
VEN = 0 V
VVDD = 12 V
No Load
1
0
−40 −25 −10
110 125
Figure 1. VDD Supply Current vs. Temperature
OVP/UVP Trip Threshold (%)
4
0.1
Output Current (µA)
1
FCCM
Skip Mode
6
Figure 5. Frequency vs. Temperature (fSET = 300 kHz)
Copyright © 2011, Texas Instruments Incorporated
1
0.01
0.1
Output Current (A)
1
6
Figure 6. Frequency vs. Temperature (fSET = 500 kHz)
9
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
1000
Switching Frequency (kHz)
Switching Frequency (kHz)
1000
100
fSET = 750 kHz
VIN = 12 V
VOUT = 1.1 V
10
100
fSET = 1 MHz
VIN = 12 V
VOUT = 1.1 V
10
FCCM
Skip Mode
1
0.01
0.1
Output Current (A)
1
FCCM
Skip Mode
1
0.01
6
1200
1.120
1000
1.115
6
1.110
800
600
400
200
fSW = 300 kHz
fSW = 500 kHz
fSW = 750 kHz
fSW = 1 MHz
0
−200
1
Figure 8. Frequency vs. Temperature (fSET = 1 MHz)
Output Voltage (V)
Switching Frequency (kHz)
Figure 7. Frequency vs. Temperature (fSET = 750 kHz)
0.1
Output Current (A)
0
1
2
1.105
1.100
1.095
1.090
IOUT =5 A
VIN = 12 V
3
4
Output Voltage (V)
5
1.085
1.080
6
Figure 9. Switching Frequency vs. Output Voltage
Skip Mode
FCCM
0
1
2
3
4
Output Current (A)
5
6
Figure 10. Output Voltage vs. Output Current
1.120
100
1.115
90
80
70
Efficiency (%)
Output Voltage (V)
1.110
1.105
1.100
1.095
60
50
30
1.090
fSW = 500 kHz
VIN = 12 V
1.085
1.080
FCCM, No Load
Skip Mode, No Load
FCCM and Skip Mode, IOUT = 5 A
4
5
6
7
8
9 10 11 12
Input Voltage (V)
13
14
15
Figure 11. Output Voltage vs. Input Voltage
10
16
VIN = 12 V
VOUT = 1.1 V
40
20
10
0
0.01
Skip Mode, fSW = 500 kHz
FCCM, fSW = 500 kHz
Skip Mode, fSW = 300 kHz
FCCM, fSW = 300 kHz
0.1
1
Output Current (A)
10
Figure 12. Efficiency vs. Output Current
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
98
94
94
90
90
Efficiency (%)
Efficiency (%)
TYPICAL CHARACTERISTICS
98
86
82
78
86
82
78
VIN = 12 V
FCCM
fSW = 300 kHz
74
70
0
1
2
1.0
1.1
1.2
3
4
Output Current (A)
VOUT (V)
1.5
1.8
VIN = 12 V
Skip Mode
fSW = 300 kHz
74
70
5
0
6
98
98
94
94
90
90
86
82
78
VIN = 12 V
FCCM
fSW = 500 kHz
74
1.0
1.1
1.2
3
4
Output Current (A)
5
6
86
82
78
VOUT (V)
1.5
1.8
3.3
5.0
VIN = 12 V
Skip Mode
fSW = 500 kHz
74
70
1.0
1.1
1.2
VOUT (V)
1.5
1.8
3.3
5.0
70
0
1
2
3
4
Output Current (A)
5
0
6
Figure 15. Efficiency vs Output Current,
Inductors: VOUT ≤ 3.3 V: PCMC065T-1R0, VOUT = 5 V:
PG0642.222
98
98
94
94
90
90
86
82
1
2
3
4
Output Current (A)
VIN = 5 V
FCCM
fSW = 500 kHz
74
1.0
1.1
1.2
VOUT (V)
1.5
1.8
3.3
6
86
82
78
78
5
Figure 16. Efficiency vs Output Current,
Inductors: VOUT ≤ 3.3 V: PCMC065T-1R0, VOUT = 5 V:
PG0642.222
Efficiency (%)
Efficiency (%)
2
VOUT (V)
1.5
1.8
Figure 14. Efficiency vs Output Current,
Inductors: PCMC065T-1R0
Efficiency (%)
Efficiency (%)
Figure 13. Efficiency vs Output Current,
Inductors: PCMC065T-1R0
1
1.0
1.1
1.2
VIN = 5 V
Skip Mode
fSW = 500 kHz
74
1.0
1.1
1.2
VOUT (V)
1.5
1.8
3.3
70
70
0
2
4
6
8
Output Current (A)
10
Figure 17. Efficiency vs Output Current,
Inductor: PCMC065T-1R0
Copyright © 2011, Texas Instruments Incorporated
12
0
1
2
3
4
Output Current (A)
5
6
Figure 18. Efficiency vs Output Current,
Inductor: PCMC065T-1R0
11
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SLUSAK3 – MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
FCCM Mode
V IN=12V
IOUT=5A
EN (5V/div)
FCCM Mode
V IN=12V
IOUT=0A
EN (5V/div)
V OUT (0.5V/div)
V OUT (0.5V/div)
0.5V pre-biased
VREG(5V/div)
VREG(5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
Time (1 ms/div)
Time (1 ms/div)
Figure 19. Start-Up
Figure 20. Pre-Bias Start-Up
EN (5V/div)
FCCM Mode
V EN=5V
IOUT=5A
V DD =VIN
V IN(5V/div)
V OUT (0.5V/div)
FCCM Mode
V IN=12V
IOUT=5A
V OUT (0.5V/div)
VREG(5V/div)
VREG(5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
Time (4 ms/div)
Figure 21. Turn-Off
12
Time (2 ms/div)
Figure 22. UVLO Start-Up
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
Skip Mode
VIN = 12 V
IOUT= 0 A
FCCM
VIN = 12 V
IOUT = 0 A
VOUT (20 mV/div)
VOUT (20 mV/div)
LL (5 V/div)
LL (5 V/div)
IL (2 A/div)
IL (2 A/div)
Time (2 µs/div)
Time (1 µs/div)
Figure 23. 1.1-V Output FCCM Steady-State Operation
Skip Mode
VIN = 12 V
Figure 24. 1.1-V Output Skip Mode Steady-State Operation
VOUT (20 mV/div)
VOUT (20 mV/div)
VOUT = 1.1 V
Skip Mode
VIN = 12 V
LL (5 V/div)
LL (5 V/div)
VOUT = 1.1 V
IL (2 A/div)
Time (100 µs/div)
Figure 25. CCM to DCM Transition
Copyright © 2011, Texas Instruments Incorporated
IL (2 A/div)
Time (100 µs/div)
Figure 26. DCM to CCM Transition
13
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
Skip Mode
VIN = 12 V
FCCM
VIN = 12 V
VOUT = 1.1 V
VOUT (20 mV/div)
IOUT from 0 A to 5 A, 2.5A/µs
VOUT = 1.1 V
VOUT (20 mV/div)
IOUT from 0 A to 5 A, 2.5A/µs
IOUT (5 A/div)
IOUT (5 A/div)
Time (2 µs/div)
Time (100 µs/div)
Figure 27. FCCM Load Transient
Figure 28. Skip Mode Load Transient
V IN=12V
IOUT from 5A to 7A
V OUT (1V/div)
EN (5 V/div)
LL(10V/div)
VOUT (1 V/div)
IL (5A/div)
PGOOD (5 V/div)
PGOOD(5V/div)
VIN = 12 V
IOUT = 10 A
Time (10 ms/div)
Figure 29. Overcurrent Protection
14
Time (1 s/div)
Figure 30. Over-temperature Protection
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
Figure 31, shows the thermal signature of the TPS53314 EVM, VIN = 12 V, VOUT = 1.1 V, IOUT= 6 A, fSW = 500 kHz at room
temperature with no airflow.
Figure 32 shows the thermal signature of the TPS53314 EVM, VIN = 12 V, VOUT = 3.3 V, IOUT= 6 A, fSW = 650 kHz at room
temperature with no airflow.
Figure 31. Thermal Signature of TPS53314 EVM,
fSW = 500 kHz
Copyright © 2011, Texas Instruments Incorporated
Figure 32. Thermal Signature of TPS53314 EVM,
fSW = 650 kHz
15
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
APPLICATION INFORMATION
APPLICATION CIRCUIT DIAGRAM
Figure 33. Typical Application Circuit Diagram
16
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
Figure 34. Typical Application Circuit Diagram with Ceramic Output Capacitors
Copyright © 2011, Texas Instruments Incorporated
17
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
General Description
The TPS53314 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage
point-of-load applications in computing and similar digital consumer applications. The device features proprietary
D-CAP™ mode control combined with an adaptive on-time architecture. This combination is ideal for building
modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to
5.5 V. The conversion input voltage range is from 3 V up to 15 V. The D-CAP™ mode uses the ESR of the
output capacitor(s) to sense the device current. One advantage of this control scheme is that it does not require
an external phase compensation network. This allows a simple design with a low external component count.
Eight preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or
the VREG pin. Adaptive on-time control tracks the preset switching frequency over a wide input and output
voltage range while allowing the switching frequency to increase at the step-up of the load.
The TPS53314 has a MODE pin to select between auto-skip mode and forced continuous conduction mode
(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to
5.6 ms.
Enable and Soft Start
When the EN pin voltage rises above the enable threshold voltage (typically 1.2 V), the controller enters its
start-up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The
controller then uses the first 250 μs to calibrate the switching frequency setting resistance attached to the RF pin
and stores the switching frequency code in internal registers. However, switching is inhibited during this phase. In
the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the
MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the
output voltage is maintained during start-up regardless of load current.
Table 1. Soft-Start and MODE
MODE SELECTION
Auto Skip
Forced CCM (1)
(1)
18
ACTION
Pull down to GND
Connect to PGOOD
SOFT-START TIME
(ms)
RMODE
(kΩ)
0.7
39
1.4
100
2.8
200
5.6
475
0.7
39
1.4
100
2.8
200
5.6
475
The device transitions into FCCM after the PGOOD pin goes high.
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
Adaptive On-Time D-CAP™ Control
The TPS53314 does not have a dedicated oscillator to determine switching frequency. However, the device
operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the on-time
one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage
æ
VIN ö
ç tON µ
÷
VOUT ø .
and proportional to the output voltage è
This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range.
The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and
GND or between the RF pin and the VREG pin as shown in Table 2. (Leaving the resistance open sets the
switching frequency to 500 kHz.)
Table 2. Resistor and Switching Frequency
RESISTOR (RRF) CONNECTIONS
SWITCHING FREQUENCY
(kHz)
0 Ω to GND
250
187 kΩ to GND
300
619 kΩ to GND
400
Open
500
866 kΩ to VREG
600
309 kΩ to VREG
750
124 kΩ to VREG
850
0 Ω to VREG
970
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When the signal values match, the
PWM comparator asserts a set signal to terminate the off-time (turn off the low-side MOSFET and turn on
high-side MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the
off-time is extended until the current level falls below the threshold.
Figure 35 and Figure 36 show two on-time control schemes.
VFB
VFB
VREF
VREF
tON
Compensation
Ramp
PWM
PWM
tON
tOFF
UDG-10208
Figure 35. On-Time Control Without Ramp
Compensation
Copyright © 2011, Texas Instruments Incorporated
tOFF
UDG-10209
Figure 36. On-Time Control With Ramp
Compensation
19
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 37.
TPS53314
VIN
Switching Modulator
VIN
R1
LL
VFB
PWM
37
+
R2
+
Control
Logic
and
Divider
L
VOUT
IIND
IC
IOUT
0.6 V
ESR
RLOAD
Voltage
Divider
VC
COUT
Output
Capacitor
UDG-10203
Figure 37. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on-cycle substantially
constant.
1
H (s ) =
s ´ ESR ´ COUT
(1)
For the loop stability, the 0 dB frequency, ƒ0, defined in Equation 2 must be lower than ¼ of the switching
frequency.
f
1
£ SW
f0 =
2p ´ ESR ´ COUT
4
(2)
According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor
chemistry. For example, specialty polymer capacitors (SP-CAP) have COUT on the order of several 100 µF and
ESR in range of 10 mΩ. These makes ƒ0 on the order of 100 kHz or less and the loop is stable. However,
ceramic capacitors have an ƒ0 at more than 700 kHz, and need special care when used with this modulator. An
application circuit using ceramic capacitors is described in External Parts Selection section under All Ceramic
Output Capacitors.
Ramp Signal
The TPS53314 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. The feedback
voltage is compared with the reference information to keep the output voltage in regulation. By adding a small
ramp signal to the reference, the signal-to-noise ratio at the onset of a new switching cycle is improved.
Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start with –7 mV at
the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in steady state.
20
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
Auto-Skip Eco-mode™ Light Load Operation
While the MODE pin is pulled low via RMODE, the TPS53314 automatically reduces the switching frequency at
light-load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the
load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is
maintained as it was in the continuous conduction mode so that it takes longer time to discharge the output
capacitor with smaller load current to the level of the reference voltage. The transition point to the light-load
operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated
as shown in Equation 3.
IOUT(LL ) =
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
where
•
ƒSW is the PWM switching frequency
(3)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 3. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
Adaptive Zero Crossing
The TPS53314 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It
prevents SW-node swing-up caused by postponed detection and minimizes diode conduction period caused by
premature detection. As a result, better light-load efficiency is delivered.
Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) during light-load conditions. In this mode, the switching frequency is maintained over the entire load range
which is suitable for applications needing tight control of the switching frequency at a cost of lower efficiency.
Power Good
The TPS53314 has powergood output that indicates high when switcher output is within the target. The
powergood function is activated after soft-start has finished. If the output voltage becomes within +10% or –5% of
the target value, internal comparators detect the powergood state and the powergood signal becomes high after
a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good
signal becomes low after two microsecond (2-μs) internal delay. The powergood output is an open drain output
and must be pulled up externally.
In order for the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic
before the TPS53314 is powered up, it is recommended the PGOOD be pull to VREG (either directly or through
a resistor divider) because VREG remains low when the device is off.
Current Sense and Overcurrent Protection
TPS53314 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller maintains the OFF state during the period in that the inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53314 supports
temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip
voltage setting resistor, RTRIP. The TRIP pin sources ITRIP current, which is 10 μA typically at room temperature,
and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 4.
VTRIP (mV ) = RTRIP (kW )´ ITRIP (mA )
Copyright © 2011, Texas Instruments Incorporated
(4)
21
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
The inductor current is monitored by the voltage between the GND pin and the SW pin so that the SW pin should
be connected to the drain terminal of the low-side MOSFET properly. ITRIP has 4700 ppm/°C temperature slope
to compensate the temperature dependency of the RDS(on). The GND pin is used as the positive current sensing
node. The GND pin should be connected to the proper current sensing device, (for example, the source terminal
of the low-side MOSFET.)
As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load
current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 5.
IOCP =
VTRIP
(8 ´ RDS(on) )
IIND(ripple)
+
2
=
VTRIP
(8 ´ RDS(on) )
+
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, therefore the
output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts down.
After a hiccup delay (16 ms with 0.7-ms sort-start), the controller restarts. If the overcurrent condition remains,
the procedure is repeated and the device enters hiccup mode.
During CCM, the negative current limit (NCL) protects the internal FET from carrying too much current. The NCL
detect threshold is set as the same absolute value as positive OCL but negative polarity. Note that the threshold
continues to represent the valley value of the inductor current.
Overvoltage and Undervoltage Protection
The TPS53314 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. When the
feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an
internal UVP delay counter begins counting. After 1 ms, TPS53314 latches OFF both high-side and low-side
MOSFETs drivers. The controller restarts after a hiccup delay (16 ms with 0.7-ms soft-start). This function is
enabled 1.5 ms after the soft-start is completed.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The
output voltage decreases. If the output voltage reaches the UV threshold, then both high-side MOSFET and
low-side MOSFET driver is OFF and the device restarts after a hiccup delay. If the OV condition remains, both
high-side MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed.
UVLO Protection
The TPS53314 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than the
UVLO threshold voltage, the switch mode power supply shuts off. This is a non-latch protection.
Thermal Shutdown
TPS53314 includes a temperature monitoring feature. If the temperature exceeds the threshold value (typically
145°C), TPS53314 shuts off. When the temperature falls approximately 10°C below the threshold value, the
device turns on again. This is a non-latch protection.
22
Copyright © 2011, Texas Instruments Incorporated
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
External Parts Selection
The external components selection is a simple process using D-CAP™ Mode.
1. CHOOSE THE INDUCTOR
The inductance value should be determined to give the ripple current of approximately 1/4 to ½ of maximum
output current. Larger ripple current increases output ripple voltage and improves signal-to-noise ratio and
helps stable operation.
L=
1
IIND(ripple ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
=
3
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
VIN(max)
)´ V
OUT
(6)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 7.
IIND(peak ) =
)
(
VIN(max ) - VOUT ´ VOUT
VTRIP
1
+
´
8 ´ RDS(on ) L ´ fSW
VIN(max )
(7)
2. CHOOSE THE OUTPUT CAPACITOR(S)
When organic semiconductor capacitor(s) or specialty polymer capacitor(s) are used, for loop stability,
capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to
determine ESR.
ESR =
VOUT ´ 10 (mV )´ (1 - D)
0.6 (V )´ IIND(ripple )
=
10 (mV )´ L ´ fSW
0.6 (V )
=
L ´ fSW
(W )
60
where
•
•
•
D is the duty factor
tSW is the switching period
the required output ripple slope is approximately 10 mV per tSW in terms of VVFB
(8)
3. DETERMINE THE VALUE OF R1 AND R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is
connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended R2 value is from 10kΩ to 20kΩ. Determine R1 using Equation 9.
IIND(ripple ) ´ ESR
- 0.6
VOUT 2
´ R2
R1 =
0.6
(9)
Copyright © 2011, Texas Instruments Incorporated
23
TPS53314
SLUSAK3 – MAY 2011
www.ti.com
External Parts Selection with All Ceramic Output Capacitors
When ceramic output capacitors are used, the stability criteria in Equation 2 cannot be satisfied. The ripple
injection approach as shown in Equation 10 is implemented to increase the ripple on the VFB pin and make the
system stable. C2 can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF.
The increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the
VFB pin has two components, one coupled from SW node and the other coupled from VOUT and they can be
calculated using Equation 10 and Equation 11.
V - VOUT
D
´
VINJ _ SW = IN
R7 ´ C1
fSW
(10)
VINJ _ OUT = ESR ´ IIND(ripple ) +
IIND(ripple )
8 ´ COUT ´ fSW
(11)
The DC value of VFB can be calculated by Equation 12:
VINJ _ SW + VINJ _ OUT
VVFB = 0.6 +
2
(12)
And the resistor divider value can be determined by Equation 13:
- VFB
V
´ R2
R1 = OUT
VFB
(13)
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a layout work using the TPS53314.
• The power components (including input/output capacitors, inductor and TPS53314) should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
plane(s) and shield feedback trace from power traces and components.
• Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
• Since the TPS53314 controls output voltage referring to voltage across the VOUT capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of VOUT capacitor. In a same manner
both bottom side resistor and GND pad of the device should be connected to the negative node of VOUT
capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component
side and avoid via(s) between these resistors and the device.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
• Connect the frequency setting resistor from RF pin to ground, or to the VREG pin, and make the connections
as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node.
• Connect the MODE setting resistor from MODE pin to ground, or to the PGOOD pin, and make the
connections as close as possible to the device. The trace from the MODE pin to the resistor and from the
resistor to ground should avoid coupling to a high-voltage switching node.
• The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
• Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 34) from the terminal of
ceramic output capacitor. The AC coupling capacitor (C2 in Figure 34) should be placed near the device and
R7 and C1 can be placed near the power stage.
24
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS53314RGFR
ACTIVE
VQFN
RGF
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS53314RGFT
ACTIVE
VQFN
RGF
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS53314RGFR
VQFN
RGF
40
3000
330.0
16.4
5.25
7.25
1.45
8.0
16.0
Q1
TPS53314RGFT
VQFN
RGF
40
250
180.0
16.4
5.25
7.25
1.45
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS53314RGFR
VQFN
RGF
40
3000
346.0
346.0
33.0
TPS53314RGFT
VQFN
RGF
40
250
190.5
212.7
31.8
Pack Materials-Page 2
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