Freescale Semiconductor Data Sheet MPC5200 Rev. 4, 01/2005 MPC5200 Data Sheet NOTE The information in this document is subject to change. For the latest data on the MPC5200, visit www.freescale.com and proceed to the MPC5200 Product Summary Page. 1 Overview The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on communications and systems integration. The G2_LE core design is based on the PowerPCTM core architecture. MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded G2_LE core. The MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers (PSC), I2C, SPI, CAN, J1850, Timers, and GPIOs. Table of Contents 1 2 3 4 5 6 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical and Thermal Characteristics . . . . . . . . . 6 3.1 DC Electrical Characteristics . . . . . . . . . . . . . 6 3.2 Oscillator and PLL Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 AC Electrical Characteristics . . . . . . . . . . . . 14 Package Description . . . . . . . . . . . . . . . . . . . . . . 64 4.1 Package Parameters . . . . . . . . . . . . . . . . . . 64 4.2 Mechanical Dimensions. . . . . . . . . . . . . . . . 64 4.3 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . 66 System Design Information. . . . . . . . . . . . . . . . . 71 5.1 Power UP/Down Sequencing . . . . . . . . . . . 71 5.2 System and CPU Core AVDD power supply filtering . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 Pull-up/Pull-down Resistor Requirements . . 73 5.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 79 Document Revision History. . . . . . . . . . . . . . . . . 79 “Definitive Data: Freescale reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.” © Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Features 2 Features Key features are shown below. • MPC603e series G2_LE core — Superscalar architecture — 760 MIPS at 400 MHz (-40 to +85 oC) — 16 k Instruction cache, 16 k Data cache — Double precision FPU — Instruction and Data MMU — Standard and Critical interrupt capability • SDRAM / DDR Memory Interface — up to 132-MHz operation — SDRAM and DDR SDRAM support — 256-MByte addressing range per CS, two CS available — 32-bit data bus — Built-in initialization and refresh • Flexible multi-function External Bus Interface — Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices — 8 programmable Chip Selects — Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address — Short or Long Burst capable — Multiplexed data access using 8/16/32 bit databus with up to 25-bit address • Peripheral Component Interconnect (PCI) Controller — Version 2.2 PCI compatibility — PCI initiator and target operation — 32-bit PCI Address/Data bus — 33- and 66-MHz operation — PCI arbitration function • ATA Controller — Version 4 ATA compatible external interface—IDE Disk Drive connectivity • BestComm DMA subsystem — Intelligent virtual DMA Controller — Dedicated DMA channels to control peripheral reception and transmission — Local memory (SRAM 16 kBytes) • 6 Programmable Serial Controllers (PSC), configurable for the following: — UART or RS232 interface MPC5200 Data Sheet, Rev. 4 2 Freescale Semiconductor Features • • • • • • • — CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97 — Full duplex SPI mode — IrDA mode from 2400 bps to 4 Mbps Fast Ethernet Controller (FEC) — Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface Universal Serial Bus Controller (USB) — USB Revision 1.1 Host — Open Host Controller Interface (OHCI) — Integrated USB Hub, with two ports. Two Inter-Integrated Circuit Interfaces (I2C) Serial Peripheral Interface (SPI) Dual CAN 2.0 A/B Controller (MSCAN) —Freescale Scalable Controller Area Network (FSCAN) architecture — Implementation of version 2.0A/B CAN protocol — Standard and extended data frames J1850 Byte Data Link Controller (BDLC) — J1850 Class B data communication network interface compatible and ISO compatible for low speed (<125 kbps) serial data communications in automotive applications. — Supports 4X mode, 41.6 kbps — In-frame response (IFR) types 0, 1, 2, and 3 supported Systems level features — Interrupt Controller supports four external interrupt request lines and 47 internal interrupt sources — GPIO/Timer functions – Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a variety of interrupt/WakeUp capabilities. – Eight GPIO pins with timer capability supporting input capture, output compare, and pulse width modulation (PWM) functions — Real-time Clock with one-second resolution — Systems Protection (watch dog timer, bus monitor) — Individual control of functional block clock sources — Power management: Nap, Doze, Sleep, Deep Sleep modes — Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN) MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 3 Features • • Test/Debug features — JTAG (IEEE 1149.1 test access port) — Common On-chip Processor (COP) debug port On-board PLL and clock generation Figure 1 shows a simplified MPC5200 block diagram. MPC5200 Data Sheet, Rev. 4 4 Freescale Semiconductor Freescale Semiconductor Reset / Clock Generation JTAG / COP Interface CommBus G2_LE Core 603 SDRAM / DDR Memory Controller SDRAM / DDR ATA Host Controller PCI Bus Controller Local Plus Controller GPIO/Timers Interrupt Controller System Functions Real-Time Clock Systems Interface Unit (SIU) Local Bus Features MSCAN 2x J1850 USB 2x SPI I2C 2x BestComm DMA Ethernet SRAM 16K PSC 6x Figure 1. Simplified Block Diagram—MPC5200 MPC5200 Data Sheet, Rev. 4 5 Electrical and Thermal Characteristics 3 Electrical and Thermal Characteristics 3.1 DC Electrical Characteristics 3.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5200 DC Electrical characteristics. Table 1 gives the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 Characteristic Symbol Min Max Unit SpecID Supply voltage - G2_LE core and peripheral logic VDD_CORE –0.3 1.8 V D1.1 VDD_IO, VDD_MEM_IO –0.3 3.6 V D1.2 Supply voltage - System APLL SYS_PLL_AVDD –0.3 2.1 V D1.3 Supply voltage - G2_LE APLL CORE_PLL_AVDD –0.3 2.1 V D1.4 Input voltage (VDD_IO) Vin –0.3 VDD_IO + 0.3 V D1.5 Input voltage (VDD_MEM_IO) Vin –0.3 VDD_MEM_IO + 0.3 V D1.6 Input voltage overshoot Vinos – 1.0 V D1.7 Input voltage undershoot Vinus – 1.0 V D1.8 Supply voltage - I/O buffers Storage temperature range Tstg –55 o 150 C D1.9 NOTES: 1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage. 3.1.2 Recommended Operating Conditions Table 2 gives the recommended operating conditions. Table 2. Recommended Operating Conditions Symbol Min1 Max(1) Unit SpecID VDD_CORE 1.42 1.58 V D2.1 VDD_IO 3.0 3.6 V D2.2 Supply voltage - memory I/O buffers (SDR) VDD_MEM_IOSDR 3.0 3.6 V D2.3 Supply voltage - memory I/O buffers (DDR) VDD_MEM_IODDR 2.42 2.63 V D2.4 Supply voltage - System APLL SYS_PLL_AVDD 1.42 1.58 V D2.5 Supply voltage - G2_LE APLL CORE_PLL_AVDD 1.42 1.58 V D2.6 Vin 0 VDD_IO V D2.7 VinSDR 0 VDD_MEM_IOSDR V D2.8 Characteristic Supply voltage - G2_LE core and peripheral logic Supply voltage - standard I/O buffers Input voltage - standard I/O buffers Input voltage - memory I/O buffers (SDR) MPC5200 Data Sheet, Rev. 4 6 Freescale Semiconductor Electrical and Thermal Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Input voltage - memory I/O buffers (DDR) Ambient operating temperature range Symbol Min1 Max(1) VinDDR 0 2 TA Unit SpecID VDD_MEM_IODDR V D2.9 +85 oC D2.10 -40 Extended ambient operating temperature range3 TAext -40 +105 o C D2.11 Die junction operating temperature range Tj -40 +115 oC D2.12 Tjext -40 +125 oC D2.13 Extended die junction operating temperature range NOTES: 1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. 2 Maximum G2_LE core operating frequency is 400 MHz 3 Maximum G2_LE core operating frequency is 264 MHz 3.1.3 DC Electrical Specifications Table 3 gives the DC Electrical characteristics for the MPC5200 at recommended operating conditions (see Table 2). Table 3. DC Electrical Specifications Characteristic Condition Symbol Min Max Unit SpecID Input high voltage Input type = TTL VDD_IO/VDD_MEM_IOSDR VIH 2.0 — V D3.1 Input high voltage Input type = TTL VDD_MEM_IODDR VIH 1.7 — V D3.2 Input high voltage Input type = PCI VDD_IO VIH 2.0 — V D3.3 Input high voltage Input type = SCHMITT VDD_IO VIH 2.0 — V D3.4 Input high voltage SYS_XTAL_IN CVIH 2.0 — V D3.5 Input high voltage RTC_XTAL_IN CVIH 2.0 — V D3.6 Input low voltage Input type = TTL VDD_IO/VDD_MEM_IOSDR VIL — 0.8 V D3.7 Input low voltage Input type = TTL VDD_MEM_IODDR VIL — 0.7 V D3.8 Input low voltage Input type = PCI VDD_IO VIL — 0.8 V D3.9 Input low voltage Input type = SCHMITT VDD_IO VIL — 0.8 V D3.10 Input low voltage SYS_XTAL_IN CVIL — 0.8 V D3.11 Input low voltage RTC_XTAL_IN CVIL — 0.8 V D3.12 MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 7 Electrical and Thermal Characteristics Table 3. DC Electrical Specifications (continued) Characteristic Condition Symbol Min Max Unit SpecID Vin = 0 or VDD_IO/VDD_IO_MEMSDR IIN — +10 µA D3.13 Input leakage current SYS_XTAL_IN Vin = 0 or VDD_IO IIN — +10 µA D3.14 Input leakage current RTC_XTAL_IN Vin = 0 or VDD_IO IIN — +10 µA D3.15 PULLUP VDD_IO Vin = 0 IINpu 40 109 µA D3.16 PULLUP_MEM VDD_IO_MEMSDR Vin = 0 IINpu 41 111 µA D3.17 PULLDOWN VDD_IO Vin = VDD_IO IINpd 36 106 µA D3.18 Output high voltage IOH is driver dependent2 VDD_IO, VDD_IO_MEMSDR VOH 2.4 — V D3.19 Output high voltage IOH is driver dependent2 VDD_IO_MEMDDR VOHDDR 1.7 — V D3.20 Output low voltage IOL is driver dependent2 VDD_IO, VDD_IO_MEMSDR VOL — 0.4 V D3.21 Output low voltage IOL is driver dependent2 VDD_IO_MEMDDR VOLDDR — 0.4 V D3.22 ICS -1.0 1.0 mA D3.23 Cin — 15 pF D3.24 Input leakage current 1 (depending on input type ) Input current, pullup resistor Input current, pullup resistor memory I/O buffers Input current, pulldown resistor DC Injection Current Per Pin3 Capacitance Vin = 0V, f = 1 MHz NOTES: Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. 2 See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 52. 3 All injection current is transferred to VDD_IO/VDD_IO_MEM. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. 1 Table 4. Drive Capability of MPC5200 Output Pins Driver Type Supply Voltage IOH IOL Unit SpecID DRV4 VDD_IO = 3.3V 4 4 mA D3.25 DRV8 VDD_IO = 3.3V 8 8 mA D3.26 MPC5200 Data Sheet, Rev. 4 8 Freescale Semiconductor Electrical and Thermal Characteristics Table 4. Drive Capability of MPC5200 Output Pins (continued) Driver Type Supply Voltage IOH IOL Unit SpecID VDD_IO = 3.3V - 8 mA D3.27 DRV16_MEM VDD_IO_MEM = 3.3V 16 16 mA D3.28 DRV16_MEM VDD_IO_MEM = 2.5V 16 16 mA D3.29 VDD_IO = 3.3V 16 16 mA D3.30 DRV8_OD PCI 3.1.4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (i.e., either GND or VCC ). Table 7 gives package thermal characteristics for this device. Table 5. ESD and Latch-Up Protection Characteristics Sym Rating Min Max Unit SpecID VHBM Human Body Model (HBM)—JEDEC JESD22-A114-B 2000 — V D4.1 VMM Machine Model (MM)—JEDEC JESD22-A115 200 — V D4.2 VCDM Charge Device Model (CDM)—JEDEC JESD22-C101 500 — V D4.3 Latch-up Current at TA=85oC positive negative +100 -100 — mA Latch-up Current at TA=27oC positive negative +200 -200 — mA ILAT ILAT 3.1.5 D4.4 D4.5 Power Dissipation Power dissipation of the MPC5200 is caused by 3 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated by the user for each application case using the following formula P IO = P IOint + ∑ N × C × VDD_IO 2 ×f M MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 9 Electrical and Thermal Characteristics where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5200 processor must not exceed the value, which would cause the maximum junction temperature to be exceeded. P total = P core + P analog + P IO Table 6. Power Dissipation Core Power Supply (VDD_CORE) SYS_XTAL/XLB/PCI/IPG/CORE (MHz) SpecID Mode Operational Doze Nap 33/66/33/33/264 33/132/66/132/396 Typ Typ 727.5 1080 — 600 — 225 Unit Notes mW 12 , D5.1 mW 13 , D5.2 mW 1,4 D5.3 Sleep — 225 mW 15 , D5.4 Deep-Sleep 52.5 52.5 mW 16 D5.5 , PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD) Mode Typ Unit Notes Typical 2 mW 7 D5.6 Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO8) Mode Typ Unit Notes Typical 33 mW 9 D5.7 NOTES: 1 Typical core power is measured at VDD_CORE = 1.5 V, Tj = 25 C 2 Operational power is measured while running an entirely cache-resident program with floating-point multiplication instructions in parallel with a continuous PCI transaction via BestComm. 3 Doze power is measured with the G2_LE core in Doze mode, the system oscillator, System PLL and Core PLL are active, all other system modules are inactive 4 Nap power is measured with the G2_LE core in Nap mode, the stem oscillator, System PLL and Core PLL are active, all other system modules are inactive 5 Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL and Core PLL are active, all other system modules are inactive 6 Deep-Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL, Core PLL and all other system modules are inactive 7 Typical PLL power is measured at SYS_PLL_AVDD = CORE_PLL_AVDD = 1.5 V, Tj = 25 C 8 IO power figures given in the table represent the worst case scenario. For the mem_io rail connected to 2.5V the IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3V. 9 Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IO SDR= 3.3 V, Tj = 25 C MPC5200 Data Sheet, Rev. 4 10 Freescale Semiconductor Electrical and Thermal Characteristics 3.1.6 Thermal Characteristics Table 7. Thermal Resistance Data Rating Value Unit Notes SpecID RθJA 30 °C/W 1,2 D6.1 Junction to Ambient Natural Convection Single layer board (1s) Junction to Ambient Natural Convection Four layer board (2s2p) RθJMA 22 °C/W 1,3 D6.2 Junction to Ambient (@200 ft/min) Single layer board (1s) RθJMA 24 °C/W 1,3 D6.3 Junction to Ambient (@200 ft/min) Four layer board (2s2p) RθJMA 19 °C/W 1,3 D6.4 RθJB 14 °C/W 4 D6.5 D6.6 D6.7 Junction to Board Junction to Case Junction to Package Top Natural Convection RθJC 8 °C/W 5 ΨJT 2 °C/W 6 NOTES: 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3.1.7 Heat Dissipation An estimation of the chip-junction temperature, TJ, can be obtained from the following equation: TJ = TA +(R θJA × PD ) Eqn. 1 where: TA = ambient temperature for the package (°C) R θJA = junction to ambient thermal resistance (°C/W) PD = power dissipation in package (W) The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 11 Electrical and Thermal Characteristics Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R θJA = R θJC +R θCA Eqn. 2 where: R θJA = junction to ambient thermal resistance (°C/W) R θJC = junction to case thermal resistance (°C/W) R θCA = case to ambient thermal resistance (°C/W) R θJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, R θCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance1-3. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT +(Ψ JT × PD ) Eqn. 3 where: TT = thermocouple temperature on top of package (°C) Ψ JT = thermal characterization parameter (°C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 3.2 Oscillator and PLL Electrical Characteristics The MPC5200 System requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. MPC5200 Data Sheet, Rev. 4 12 Freescale Semiconductor Electrical and Thermal Characteristics There is a separate oscillator for the independent Real-Time Clock (RTC) system. The MPC5200 clock generation uses two phase locked loop (PLL) blocks. • The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. • The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The G2_LE core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration. 3.2.1 System Oscillator Electrical Characteristics Table 8. System Oscillator Electrical Characteristics Characteristic Symbol Notes Min Typical Max Unit SpecID SYS_XTAL frequency fsys_xtal 15.6 33.3 35.0 MHz O1.1 Oscillator start-up time tup_osc — — 100 µs O1.2 3.2.2 RTC Oscillator Electrical Characteristics Table 9. RTC Oscillator Electrical Characteristics Characteristic RTC_XTAL frequency 3.2.3 Symbol Notes frtc_xtal Min Typical Max Unit SpecID — 32.768 — kHz O2.1 System PLL Electrical Characteristics Table 10. System PLL Specifications Characteristic SYS_XTAL frequency SYS_XTAL cycle time SYS_XTAL clock input jitter System VCO frequency System PLL relock time Symbol Notes Min Typical Max Unit SpecID fsys_xtal 1 15.6 33.3 35.0 MHz O3.1 Tsys_xtal (1) 66.6 30.0 28.5 ns O3.2 tjitter 2 — — 150 ps O3.3 fVCOsys (1) 250 533 800 MHz O3.4 tlock 3 — — 100 µs O3.5 NOTES: 1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating frequency. 3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 13 Electrical and Thermal Characteristics 3.2.4 G2_LE Core PLL Electrical Characteristics The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Table 11. G2_LE PLL Specifications Characteristic Symbol Notes Min Typical Max Unit SpecID G2_LE frequency fcore 1 50 — 550 MHz O4.1 G2_LE cycle time tcore (1) 2.85 — 40.0 ns O4.2 G2_LE VCO frequency fVCOcore (1) 400 — 1200 MHz O4.3 G2_LE input clock frequency fXLB_CLK 25 — 367 MHz O4.4 G2_LE input clock cycle time tXLB_CLK 2.73 — 50.0 ns O4.5 G2_LE input clock jitter G2_LE PLL relock time tjitter 2 — — 150 ps O4.6 tlock 3 — — 100 µs O4.7 NOTES: 1 The XLB_CLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating frequency. 3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. 3.3 AC Electrical Characteristics Hyperlinks to the indicated timing specification sections are provided below. • AC Operating Frequency Data • USB • Clock AC Specifications • SPI • Resets • MSCAN • External Interrupts • I2C • SDRAM • J1850 • PCI • PSC • Local Plus Bus • GPIOs and Timers • ATA • IEEE 1149.1 (JTAG) AC Specifications • Ethernet AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows: MPC5200 Data Sheet, Rev. 4 14 Freescale Semiconductor Electrical and Thermal Characteristics • • • • • TA = -40 to 85 oC Tj = -40 to 115 oC VDD_CORE = 1.42 to 1.58 V VDD_IO = 3.0 to 3.6 V Input conditions: All Inputs: tr, tf <= 1 ns Output Loading: All Outputs: 50 pF 3.3.1 AC Operating Frequency Data Table 12 provides the operating frequency information for the MPC5200. Table 12. Clock Frequencies 3.3.2 Min Max Units SpecID 1 G2_LE Processor Core — 400 MHz A1.1 2 SDRAM Clock — 133 MHz A1.2 3 XL Bus Clock — 133 MHz A1.3 4 IP Bus Clock — 133 MHz A1.4 5 PCI / Local Plus Bus Clock — 66 MHz A1.5 6 PLL Input Range 15.6 35 MHz A1.6 Clock AC Specifications t CYCLE t DUTY t DUTY t RISE t FALL CV IH SYSCLK VM VM VM CV IL Figure 2. Timing Diagram—SYS_XTAL_IN MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 15 Electrical and Thermal Characteristics Table 13. SYS_XTAL_IN Timing Sym Description t CYCLE SYS_XTAL_IN cycle time.1 t RISE SYS_XTAL_IN rise time. t FALL SYS_XTAL_IN fall time. ).2 Min Max Units SpecID 28.6 64.1 ns A2.1 — 5.0 ns A2.2 — 5.0 ns A2.3 40.0 60.0 % A2.4 t DUTY SYS_XTAL_IN duty cycle (measured at V M CV IH SYS_XTAL_IN input voltage high 2.0 — V A2.5 CV IL SYS_XTAL_IN input voltage low — 0.8 V A2.6 NOTES: 1 CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200 User Manual [1]. 2 SYS_XTAL_IN duty cycle is measured at V M. 3.3.3 Resets The MPC5200 has three reset pins: • PORRESET - Power on Reset • HRESET - Hard Reset • SRESET - Software Reset These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the DC Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs. Table 14. Reset Pulse Width Name Description Min Pulse Width Max Pulse Width Reference Clock SpecID PORRESET Power On Reset tVDD_stable+tup_osc+tlock — SYS_XTAL_IN A3.1 HRESET Hardware Reset 4 clock cycles — SYS_XTAL_IN A3.2 SRESET Software Reset 4 clock cycles — SYS_XTAL_IN A3.3 Notes: 1. For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards its minimum pulse width equals the minimum given for HRESET related to the same reference clock. 2. The tVDD_stable describes the time which is needed to get all power supplies stable. 3. For tlock, refer to the Oscillator/PLL section of this specification for further details. 4. For tup_osc, refer to the Oscillator/PLL section of this specification for further details. 5. Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles. 6. The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096 clock cycles. NOTE As long as VDD is not stable the HRESET output is not stable. MPC5200 Data Sheet, Rev. 4 16 Freescale Semiconductor Electrical and Thermal Characteristics Table 15. Reset Rise / Fall Timing Description Min Max Unit SpecID PORRESET fall time — 1 ms A3.4 PORRESET rise time — 1 ms A3.5 HRESET fall time — 1 ms A3.6 HRESET rise time — 1 ms A3.7 SRESET fall time — 1 ms A3.8 SRESET rise time — 1 ms A3.9 For additional information, see the MPC5200 User Manual [1]. NOTE Make sure that the PORRESET does not carry any glitches. The MPC5200 has no filter to prevent them from getting into the chip. NOTE HRESET and SRESET must have a monotonous rise time. 3.3.3.1 Reset Configuration Word During reset (HRESET and PORRESET) the Reset Configuration Word is cached in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and PORRESET) are inactive (high), the contents of this register get locked after two further SYS_XTAL cycles (see Figure 3). 4096 clocks 2 clocks SYS_XTAL PORRESET HRESET RST_CFG_WRD sample sample sample sample sample sample sample sample sample sample sample sample LOCK Figure 3. Reset Configuration Word Locking MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 17 Electrical and Thermal Characteristics NOTE Beware of changing the values on the pins of the reset configuration word after the deassertion of PORRESET. This may cause problems because it may change the internal clock ratios and so extend the PLL locking process. 3.3.4 External Interrupts The MPC5200 provides three different kinds of external interrupts: • Four IRQ interrupts • Eight GPIO interrupts with simple interrupt capability (not available in power-down mode) • Eight WakeUp interrupts (special GPIO pins) The propagation of these three kinds of interrupts to the core is shown in the following graphic: IRQ0 cint 8 GPIOs 8 8 GPIOs 8 GPIO Std Encoder core_cint core_int int GPIO WakeUp Grouper Encoder IRQ1 IRQ2 G2_LE Core PIs Main Interrupt Controller IRQ3 Notes: 1. PIs = Programmable Inputs 2. Grouper and Encoder functions imply programmability in software Figure 4. External interrupt scheme Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock Distribution Module (see Note Table 16). Table 16. External interrupt latencies Interrupt Type Interrupt Requests Pin Name Clock Cycles Reference Clock Core Interrupt SpecID IRQ0 10 IP_CLK critical (cint) A4.1 IRQ0 10 IP_CLK normal (int) A4.2 IRQ1 10 IP_CLK normal (int) A4.3 IRQ2 10 IP_CLK normal (int) A4.5 IRQ3 10 IP_CLK normal (int) A4.6 MPC5200 Data Sheet, Rev. 4 18 Freescale Semiconductor Electrical and Thermal Characteristics Table 16. External interrupt latencies (continued) Interrupt Type Standard GPIO Interrupts GPIO WakeUp Interrupts Pin Name Clock Cycles Reference Clock Core Interrupt SpecID GPIO_PSC3_4 12 IP_CLK normal (int) A4.7 GPIO_PSC3_5 12 IP_CLK normal (int) A4.8 GPIO_PSC3_8 12 IP_CLK normal (int) A4.9 GPIO_USB_9 12 IP_CLK normal (int) A4.10 GPIO_ETHI_4 12 IP_CLK normal (int) A4.11 GPIO_ETHI_5 12 IP_CLK normal (int) A4.12 GPIO_ETHI_6 12 IP_CLK normal (int) A4.13 GPIO_ETHI_7 12 IP_CLK normal (int) A4.14 GPIO_PSC1_4 12 IP_CLK normal (int) A4.15 GPIO_PSC2_4 12 IP_CLK normal (int) A4.16 GPIO_PSC3_9 12 IP_CLK normal (int) A4.17 GPIO_ETHI_8 12 IP_CLK normal (int) A4.18 GPIO_IRDA_0 12 IP_CLK normal (int) A4.19 DGP_IN0 12 IP_CLK normal (int) A4.20 DGP_IN1 12 IP_CLK normal (int) A4.21 Notes: 1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200 User Manual [1]. 2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt sources. Take care of interrupt prioritization which may increase the latencies. Since all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has to exceed a minimum pulse width of more than one IP_CLK cycle. Table 17. Minimum pulse width for external interrupts to be recognized Name All external interrupts (IRQs, GPIOs) Min Pulse Width Max Pulse Width Reference Clock SpecID > 1 clock cycle — IP_CLK A4.22 NOTES: 1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200 User Manual [1] for further information. 2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second interrupt will not be recognized at all. Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 19 Electrical and Thermal Characteristics 3.3.5 SDRAM 3.3.5.1 Memory Interface Timing-Standard SDRAM Read Command Table 18. Standard SDRAM Memory Read Timing Sym Description Min Max Units SpecID MEM_CLK period 7.5 — ns A5.1 tvalid Control Signals, Address and MBA Valid after rising edge of MEM_CLK — tmem_clk*0.5+0.4 ns A5.2 thold Control Signals, Address and MBA Hold after rising edge of MEM_CLK tmem_clk*0.5 — ns A5.3 tmem_clk DMvalid DQM valid after rising edge of MEM_CLK — tmem_clk*0.25+0.4 ns A5.4 DMhold DQM hold after rising edge of MEM_CLK tmem_clk*0.25-0.7 — ns A5.5 — 0.3 ns A5.6 0.2 — ns A5.7 datasetup MDQ setup to rising edge of MEM_CLK datahold MDQ hold after rising edge of MEM_CLK MEM_CLK tvalid thold Active Control Signals NOP READ DMvalid NOP NOP NOP NOP NOP DMhold DQM (Data Mask) datasetup datahold MDQ (Data) tvalid thold Row MA (Address) tvalid Column thold MBA (Bank Selects) NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing 3.3.5.2 Memory Interface Timing-Standard SDRAM Write Command In Standard SDRAM, all signals are activated on the Mem_clk from the Memory Controller and captured on the Mem_clk clock at the memory device. MPC5200 Data Sheet, Rev. 4 20 Freescale Semiconductor Electrical and Thermal Characteristics Table 19. Standard SDRAM Write Timing Sym Description Min Max Units SpecID MEM_CLK period 7.5 — ns A5.8 tvalid Control Signals, Address and MBA Valid after rising edge of MEM_CLK — tmem_clk*0.5+0.4 ns A5.9 thold Control Signals, Address and MBA Hold after rising edge of MEM_CLK tmem_clk*0.5 — ns A5.10 — tmem_clk*0.25+0.4 ns A5.11 tmem_clk*0.25-0.7 — ns A5.12 tmem_clk DMvalid DQM valid after rising edge of MEM_CLK DMhold DQM hold after rising edge of Mem_clk datavalid MDQ valid after rising edge of MEM_CLK — tmem_clk*0.75+0.4 ns A5.13 datahold MDQ hold after rising edge of MEM_CLK tmem_clk*0.75-0.7 — ns A5.14 MEM_CLK tvalid thold Active Control Signals NOP WRITE NOP NOP NOP NOP NOP DMhold DMvalid DQM (Data Mask) datavalid datahold MDQ (Data) tvalid thold Row MA (Address) tvalid Column thold MBA (Bank Selects) NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing 3.3.5.3 Memory Interface Timing-DDR SDRAM Read Command The SDRAM Memory Controller uses an internally skewed clock for reading DDR memory. The programmable bits in the Reset Configuration Register used to account for unknown board delays are in the CDM module. The internal read clock can be delayed up to 3 ns under worst operating conditions in 32 increments of 95 ps, (1.4 ns in 45 ps increments under best case operating conditions) by programming the CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration register are not ‘reset configured’ but have a hard coded reset value and are writable during operation. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 21 Electrical and Thermal Characteristics Table 20. DDR SDRAM Memory Read Timing Sym Min Max Units SpecID MEM_CLK period 7.5 — ns A5.15 tvalid Control Signals, Address and MBA valid after rising edge of MEM_CLK — tmem_clk*0.5+0.4 ns A5.16 thold Control Signals, Address and MBA hold after rising edge of MEM_CLK tmem_clk*0.5 — ns A5.17 tdata_sample_max Read Data sample window — 4.591 ns A5.18 tdata_sample_min Read Data sample window 1.552 — ns A5.19 tmem_clk Description NOTES: 1 Calculated with maximum number of Tap delay, 31 Tap delay are selected. 2 Calculated with minimum number of Tap delay, 0 Tap delay are selected. MPC5200 Data Sheet, Rev. 4 22 Freescale Semiconductor Electrical and Thermal Characteristics MEM_CLK MEM_CLK tvalid thold Active Control Signals NOP READ NOP NOP NOP NOP NOP MDQS (Data Strobe) tdata_valid_min tdata_valid_max MDQ (Data) Sample position A tdata_sample_min tdata_sample_max Read Data Sample Window MDQS (Data Strobe) tdata_valid_min tdata_valid_max MDQ (Data) 0.5 * MEM_CLK tdata_sample_min tdata_sample_max Sample position B Read Data Sample Window tvalid MA (Address) thold Row tvalid Column thold MBA (Bank Selects) Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the vaild MDQS signal NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 23 Electrical and Thermal Characteristics 8.34 delay [ns] tdata_valid_max 4.59 Memory Data valid window Possible sample time over PVT for one selected Tap delay tdata_sample_min tdata_sample_min tdata_valid_min 1.55 Working Tap Delay range for sample position B 0 Working Tap Delay range for sample position A selected Tap delay 31 Tap delay number Figure 8. Read Data sample window depend on the number of Tap delay The position of the tdata_valid window is depend on the clock / data flight time on the board. The MDQS signal indicate if the read data are valid. If the controller is not able to detect a valid MDQS signal on the sample time (sample position A) then the controller will look for valid MDQS / data on the next edge of the MEM_CLK signal (sample position B). Depend on the board travel time, different working tap delay configurations are possible. For a fast connection the data will be sampled with the next edge of MEM_CLK, this shows Figure 8, sample position A. With a longer connection maybe two sample positions are possible. Figure 8 shows a example with two working sample position (A and B). With a bigger board delay only sample position B will be possible. The equation below shows how to calculate the upper and lower limit. The right Tap delay number is selected, when the possible max and min sample timing is within the memory data valid window. • tdata_sample_max = max((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045)) • tdata_sample_min = min((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045)) MPC5200 Data Sheet, Rev. 4 24 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.5.4 Memory Interface Timing-DDR SDRAM Write Command Table 21. DDR SDRAM Memory Write Timing Sym Description tmem_clk tDQSS Min Max Units SpecID MEM_CLK period 7.5 — ns A5.20 Delay from write command to first rising edge of MDQS — tmem_clk+0.4 ns A5.21 MEM_CLK MEM_CLK Control Signals Write Write Write Write MDQS (Data Strobe) tdqss MDQ (Data) NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Figure 9. DDR SDRAM Memory Write Timing 3.3.6 PCI The PCI interface on the MPC5200 is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board, without any external buffers or other “glue logic.” Parameters apply at the package pins, not at expansion board edge connectors. The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each 33-MHz or 66-MHz PCI component in the system. Figure 10 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 22 summarizes the clock specifications. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 25 Electrical and Thermal Characteristics Tcyc 0.5Vcc 0.4Vcc PCI CLK 0.3Vcc T high 0.6Vcc T low 0.4Vcc, p-to-p (minimum) 0.2Vcc Figure 10. PCI CLK Waveform Table 22. PCI CLK Specifications 66 MHz Sym 33 MHz Description Units Notes SpecID 30 ns 1,3 A6.1 11 ns Min Max Min 30 Tcyc PCI CLK Cycle Time 15 Thigh PCI CLK High Time 6 t low PCI CLK Low Time 6 - PCI CLK Slew Rate 1.5 Max A6.2 A6.3 4 1 4 V/ns 2 A6.4 NOTES: 1. In general, all 66-MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 10. 3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. MPC5200 Data Sheet, Rev. 4 26 Freescale Semiconductor Electrical and Thermal Characteristics Table 23. PCI Timing Parameters 66 MHz Sym 33 MHz Description Units Notes SpecID 11 ns 1,2,3 A6.5 12 ns 1,2,3 A6.6 ns 1 A6.7 ns 1 A6.8 Min Max Min Max CLK to Signal Valid Delay - bused signals 2 6 2 Tval(ptp) CLK to Signal Valid Delay - point to point 2 6 2 Tval Ton Float to Active Delay Toff Active to Float Delay T su Input Setup Time to CLK - bused signals T su(ptp) Input Setup Time to CLK - point to point Th Input Hold Time from CLK 2 2 14 28 3 7 ns 3,4 A6.9 5 10,12 ns 3,4 A6.10 0 0 ns 4 A6.11 NOTES: 1. See the timing measurement conditions in the PCI Local Bus Specification [4]. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification [4]. 3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused. 4. See the timing measurement conditions in the PCI Local Bus Specification [4]. For Measurement and Test Conditions, see the PCI Local Bus Specification [4]. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 27 Electrical and Thermal Characteristics 3.3.7 Local Plus Bus The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz. Definition of Acronyms and Terms: WS = Wait State DC = Dead Cycle LB = Long Burst DS = Data size in Byte tPCIck = PCI clock period tIPBIck = IPBI clock period tPCIck PCI CLK tIPBIck IPBI CLK Figure 11. Timing Diagram—IPBI and PCI clock (example ratio: 4:1) 3.3.7.1 Non-MUXed Mode Table 24. Non-MUXed Mode Timing Sym Description Min Max Units Notes SpecID t CSA PCI CLK to CS assertion - 1.8 ns A7.1 t CSN PCI CLK to CS negation - 1.8 ns A7.2 (2+WS)*tPCIck (2+WS)*tPCIck ns t1 CS pulse width 1 A7.3 t2 ADDR valid before CS assertion tIPBIck tPCIck ns t3 ADDR hold after CS negation tIPBIck - ns t4 OE assertion before CS assertion - 0.4 ns A7.6 t5 OE negation before CS negation - 0.4 ns A7.7 t6 RW valid before CS assertion tPCIck - ns A7.8 t7 RW hold after CS negation tIPBIck - ns A7.9 t8 DATA output valid before CS assertion tIPBIck - ns A7.10 t9 DATA output hold after CS negation tIPBIck - ns A7.11 t10 DATA input setup before CS negation 2.8 - ns A7.12 t11 DATA input hold after CS negation 0 (DC+1)*tPCIck ns A7.13 t12 ACK assertion after CS assertion tPCIck - ns 3 A7.14 t13 ACK negation after CS negation - tPCIck ns 3 A7.15 A7.4 2 A7.5 MPC5200 Data Sheet, Rev. 4 28 Freescale Semiconductor Electrical and Thermal Characteristics Table 24. Non-MUXed Mode Timing (continued) Sym Description Min Max Units Notes SpecID - 0.8 ns 4 A7.16 t14 TS assertion before CS assertion t15 TS pulse width tPCIck tPCIck ns 4 A7.17 t16 TSIZ valid before CS assertion tIPBIck - ns 5 A7.18 t17 TSIZ hold after CS negation tIPBIck - ns 5 A7.19 NOTES: 1. ACK can shorten the CS pulse width. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from 0 - 65535. 2. In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment as the CS. This can cause that the address is changing earlier as CS is deasserted. 3. ACK is input and can be used to shorten the CS pulse width. 4. Only available in Large Flash and MOST Graphics mode. 5. Only available in MOST Graphics mode. t1 CS[x] t2 t3 ADDR t5 t4 OE t6 t7 R/W t8 t9 DATA (wr) t10 t11 DATA (rd) t12 ACK t14 t13 t15 TS t17 TSIZ[1:2] t16 Figure 12. Timing Diagram—Non-MUXed Mode MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 29 Electrical and Thermal Characteristics 3.3.7.2 Burst Mode Table 25. Burst Mode Timing Sym Description t CSA PCI CLK to CS assertion t CSN PCI CLK to CS negation t1 CS pulse width Min Max Units Notes SpecID - 1.8 ns A7.20 A7.21 - 1.8 ns (1+WS+4LB*2*(32/DS))* (1+WS+4LB*2*(32/DS)) ns tPCIck *tPCIck tIPBIck tPCIck ns A7.23 1,2 A7.22 t2 ADDR valid before CS assertion t3 ADDR hold after CS negation - -0.7 ns A7.24 t4 OE assertion before CS assertion - 0.4 ns A7.25 t5 OE negation before CS negation - 0.4 ns A7.26 t6 RW valid before CS assertion tPCIck - ns A7.27 t7 RW hold after CS negation tPCIck - ns A7.28 t8 DATA setup before rising edge of PCI 1.8 - ns A7.29 t9 DATA hold after rising edge of PCI 0 - ns A7.30 t10 DATA hold after CS negation 0 (DC+1)*tPCIck ns A7.31 t11 ACK assertion after CS assertion - (WS+1)*tPCIck ns A7.32 t12 ACK negation before CS negation - 0.6 ns 3 A7.33 t13 ACK pulse width 4LB*2*(32/DS)*tPCIck 4LB*2*(32/DS)*tPCIck ns 2,3 A7.34 t14 CS assertion after TS assertion - 0.8 ns A7.35 t15 TS pulse width tPCIck tPCIck ns A7.36 NOTES: 1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535. 2. Example: Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst on the internal XLB is executed. => LB = 1 Data bus width is 8 bit. => DS = 8 => 41*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line. Wait State is set to 10. => WS = 10 1+10+32 = 43 => CS is asserted for 43 PCI cycles. 3. ACK is output and indicates the burst. MPC5200 Data Sheet, Rev. 4 30 Freescale Semiconductor Electrical and Thermal Characteristics PCI CLK CS[x] t1 t3 t2 ADDR t5 t4 OE t6 t7 R/W t8 t10 DATA (rd) t9 t11 t12 ACK t14 t15 t13 TS Figure 13. Timing Diagram—Burst Mode MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 31 Electrical and Thermal Characteristics 3.3.7.3 MUXed Mode Table 26. MUXed Mode Timing Sym Description Min Max Units t CSA PCI CLK to CS assertion - 1.8 ns A7.15 t CSN PCI CLK to CS negation - 1.8 ns A7.16 tALEA PCI CLK to ALE assertion - 1 ns A7.16 t1 ALE assertion before Address, Bank, TSIZ assertion - 0.8 ns A7.17 t2 CS assertion before Address, Bank, TSIZ negation - 0.7 ns A7.18 t3 CS assertion before Data wr valid - 0.7 ns A7.19 t4 Data wr hold after CS negation tIPBIck - ns A7.20 t5 Data rd setup before CS negation 2.8 - ns A7.21 t6 Data rd hold after CS negation 0 (DC+1)*tPCIck ns t7 ALE pulse width - tPCIck ns A7.23 CS assertion after TS assertion - 0.8 ns A7.24 t8 TS pulse width - tPCIck ns A7.24 t9 CS pulse width (2+WS)*tPCIck (2+WS)*tPCIck ns A7.25 tTSA Notes 1 SpecID A7.22 tOEA OE assertion before CS assertion - 0.4 ns A7.26 tOEN OE negation before CS negation - 0.4 ns A7.27 tIPBIck - ns A7.26 - tPCIck ns A7.27 t10 RW assertion before ALE assertion t11 RW negation after CS negation t12 ACK assertion after CS assertion tIPBIck - ns 2 A7.28 t13 ACK negation after CS negation - tPCIck ns 2 A7.28 Note: 1. ACK can shorten the CS pulse width. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535. 2. ACK is input and can be used to shorten the CS pulse width. MPC5200 Data Sheet, Rev. 4 32 Freescale Semiconductor Electrical and Thermal Characteristics PCI CLK t1 t2 t4 AD[31,27] (wr) Data AD[30:28] (wr) TSIZ[0:2] bits Data AD[26:25] (wr) Bank[0:1] bits Data AD[24:0] (wr) Address[7:31] Data t3 t5 AD[31:0] (rd) t6 Data t7 ALE Address latch t8 TS t9 CSx OE t10 t11 RW t12 ACK t13 Address tenure Data tenure Figure 14. Timing Diagram—MUXed Mode 3.3.8 ATA The MPC5200 ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units (nano seconds). ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5200 User Manual [1]. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 33 Electrical and Thermal Characteristics The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes. • Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that required by the ATA-4 specification. • Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that required by the ATA-4 specification. All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive. Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates. Adequate data transfer rates are a function of the following: • The MPC5200 operating frequency (IP bus clock frequency) • Internal MPC5200 bus latencies • Other system load dependent variables The ATA clock is the same frequency as the IP bus clock in MPC5200. See the MPC5200 User Manual [1]. NOTE All output timing numbers are specified for nominal 50 pF loads. Table 27. PIO Mode Timing Specifications PIO Timing Parameter Min/Max (ns) Mode 0 (ns) Mode 1 (ns) Mode 2 (ns) Mode 3 (ns) Mode 4 (ns) SpecID t0 Cycle Time min 600 383 240 180 120 A8.1 t1 Address valid to DIOR/DIOW setup min 70 50 30 30 25 A8.2 t2 DIOR/DIOW pulse width 16-bit 8-bit min min 165 290 125 290 100 290 80 80 70 70 A8.3 t2i DIOR/DIOW recovery time min — — — 70 25 A8.4 t3 DIOW data setup min 60 45 30 30 20 A8.5 t4 DIOW data hold min 30 20 15 10 10 A8.6 t5 DIOR data setup min 50 35 20 20 20 A8.7 t6 DIOR data hold min 5 5 5 5 5 A8.8 t9 DIOR/DIOW to address valid hold min 20 15 10 10 10 A8.9 tA IORDY setup max 35 35 35 35 35 A8.10 tB IORDY pulse width max 1250 1250 1250 1250 1250 A8.11 MPC5200 Data Sheet, Rev. 4 34 Freescale Semiconductor Electrical and Thermal Characteristics CS[0]/CS[3]/DA[2:0] t2 t9 t1 DIOR/DIOW t8 t0 t3 t4 WDATA t5 t6 RDATA tA tB IORDY Figure 15. PIO Mode Timing Table 28. Multiword DMA Timing Specifications Multiword DMA Timing Parameters Min/Max Mode 0(ns) Mode 1(ns) Mode 2(ns) SpecID t0 Cycle Time min 480 150 120 A8.12 tC DMACK to DMARQ delay max — — — A8.13 tD DIOR/DIOW pulse width (16-bit) min 215 80 70 A8.14 tE DIOR data access max 150 60 50 A8.15 tG DIOR/DIOW data setup min 100 30 20 A8.16 tF DIOR data hold min 5 5 5 A8.17 tH DIOW data hold min 20 15 10 A8.18 tI DMACK to DIOR/DIOW setup min 0 0 0 A8.19 tJ DIOR/DIOW to DMACK hold min 20 5 5 A8.20 tKr DIOR negated pulse width min 50 50 25 A8.21 tKw DIOW negated pulse width min 215 50 25 A8.22 tLr DIOR to DMARQ delay max 120 40 35 A8.23 tLw DIOW to DMARQ delay max 40 40 35 A8.24 MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 35 Electrical and Thermal Characteristics t0 DMARQ (Drive) tL tC DMACK (Host) tI tD tJ tK DIOR DIOW (Host) tE RDATA (Drive) tS tF WDATA (Host) tH tG NOTE: The directionof signalassertionis towardsthe top of the page, and the direction of negation is towards the bottom of the page, irrespective of the electrical properties of the signal. Figure 16. Multiword DMA Timing Table 29. Ultra DMA Timing Specification Name (t) 2CYC MODE 0 (ns) MODE 1 (ns) MODE 2 (ns) Min Max Min Max Min Max 240 — 160 — 120 — Comment SpecID Typical sustained average two cycle time. A8.26 For information only, do not test. (t) CYC 114 — 75 — 55 — Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge A8.27 (t) 2CYC 235 — 156 — 117 — Two-cycle time allowing for clock variations, from rising edge to next rising edge or from falling edge to next falling edge of STROBE. A8.28 (t) DS 15 — 10 — 7 — Data setup time at recipient. A8.29 (t) DH 5 — 5 — 5 — Data hold time at recipient. A8.30 (t) DVS 70 — 48 — 34 — Data valid setup time at sender, to STROBE edge. A8.31 (t) DVH 6 — 6 — 6 — Data valid hold time at sender, from STROBE edge. A8.32 (t) FS 0 230 0 200 0 170 First STROBE time for drive to first negate DSTROBE from STOP during a data-in burst. A8.33 MPC5200 Data Sheet, Rev. 4 36 Freescale Semiconductor Electrical and Thermal Characteristics Table 29. Ultra DMA Timing Specification (continued) Name (t) LI (t) MLI MODE 0 (ns) MODE 1 (ns) MODE 2 (ns) Min Max Min Max Min Max 0 150 0 150 0 150 20 — 20 — 20 — Comment Limited Interlock time.1,2 Interlock time with SpecID A8.34 minimum.1,2 A8.35 1,2 A8.36 (t) UI 0 — 0 — 0 — Unlimited interlock time. (t) AZ — 10 — 10 — 10 Maximum time allowed for output drivers to release from being asserted or negated A8.37 (t) ZAH 20 — 20 — 20 — A8.38 (t) ZAD 0 — 0 — 0 — Minimum delay time required for output drivers to assert or negate from released state (t) ENV 20 70 20 70 20 70 Envelope time—from DMACK to STOP and HDMARDY during data out burst initiation. A8.40 (t) SR — 50 — 30 — 20 STROBE to DMARDY time, if DMARDY is negated before this long after STROBE edge, the recipient receives no more than one additional data word. A8.41 (t) RFS — 75 — 60 — 50 Ready-to-Final STROBE time—no STROBE edges are sent this long after negation of DMARDY. A8.42 (t) RP 160 — 125 — 100 — Ready-to-Pause time—the time recipient waits to initiate pause after negating DMARDY. A8.43 (t) IORDYZ — 20 — 20 — 20 Pull-up time before allowing IORDY to be released. A8.44 (t) ZIORDY 0 — 0 — 0 — Minimum time drive waits before driving IORDY A8.45 (t) ACK 20 — 20 — 20 — Setup and hold times for DMACK, before assertion or negation. A8.46 (t) SS 50 — 50 — 50 — Time from STROBE edge to negation of DMARQ or assertion of STOP, when sender terminates a burst. A8.47 A8.39 NOTES: 1 t ,t UI MLI, t LI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. • t UI is an unlimited interlock that has no maximum time value. • t MLI is a limited time-out that has a defined minimum. • t LI is a limited time-out that has a defined maximum. 2 All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender shall stop generating STROBE edges t RFS after negation of DMARDY. Both STROBE and DMARDY timing measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at 1.5 V. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 37 Electrical and Thermal Characteristics DMARQ (device) t UI DMACK (device) t ACK t ENV t FS t ZAD STOP (host) t ACK t ENV HDMARDY (host) t FS t ZAD t ZIORDY DSTROBE (device) t DVS t AZ t DVH DD(0:15) t ACK DA0, DA1, DA2, CS[0:1]1 Figure 17. Timing Diagram—Initiating an Ultra DMA Data In Burst t 2CYC t CYC t CYC t 2CYC DSTROBE at device tDVH tDVS tDVH tDVS tDVH DD(0:15) at device DSTROBE at host tDH tDS tDH tDS tDH DD(0:15) at host Figure 18. Timing Diagram—Sustained Ultra DMA Data In Burst MPC5200 Data Sheet, Rev. 4 38 Freescale Semiconductor Electrical and Thermal Characteristics DMARQ (device) DMARQ (host) t RP STOP (host) t SR HDMARDY (host) t RFS DSTROBE (device) DD[0:15] (device) Figure 19. Timing Diagram—Host Pausing an Ultra DMA Data In Burst DMARQ (device) DMACK (host) t LI t MLI t LI t ACK STOP (host) tLI HDMARDY (host) DSTROBE (device) t ACK t SS t IORDYZ t ZAH t AZ t DVS t DVH CRC DD[0:15] t ACK DA0,DA1,DA2, CS[0:1] Figure 20. Timing Diagram—Drive Terminating Ultra DMA Data In Burst MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 39 Electrical and Thermal Characteristics DMARQ (device) t LI DMACK (host) t RP t MLI t ZAH t ACK STOP (host) tACK t AZ HDMARDY (host) t RFS t LI t MLI DSTROBE (device) t IORDYZ t DVS t DVH DD[0:15] CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 21. Timing Diagram—Host Terminating Ultra DMA Data In Burst MPC5200 Data Sheet, Rev. 4 40 Freescale Semiconductor Electrical and Thermal Characteristics DMARQ (device) tUI DMACK (host) tACK tENV STOP (host) tLI tZIORDY tUI DDMARDY (host) tACK HSTROBE (device) tDVS tDVH DD[0:15] (host) tACK DA0,DA1,DA2, CS[0:1] Figure 22. Timing Diagram—Initiating an Ultra DMA Data Out Burst t 2CYC t CYC t CYC t 2CYC HSTROBE (host) t DVS t DVH t DVS t DVH t DVH DD[0:15] (host) HSTROBE (device) t DH t DS t DS t DH t DH DD[0:15] (device) Figure 23. Timing Diagram—Sustained Ultra DMA Data Out Burst MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 41 Electrical and Thermal Characteristics t RP DMARQ (device) DMACK (host) STOP (host) t SR DDMARDY (device) t RFS HSTROBE DD[0:15] (host) Figure 24. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst DMARQ (device) t LI t MLI DMACK (host) t SS t ACK t LI STOP (host) t LI t IORDYZ DDMARDY (device) tACK HSTROBE (host) t DVS DD[0:15] (host) t DVH CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 25. Timing Diagram—Host Terminating Ultra DMA Data Out Burst MPC5200 Data Sheet, Rev. 4 42 Freescale Semiconductor Electrical and Thermal Characteristics DMARQ (device) DMACK (host) t LI t MLI t ACK STOP (host) t RP t IORDYZ DDMARDY (device) t RFS t LI t MLI t ACK HSTROBE (host) t DVS DD[0:15] (host) t DVH CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 26. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst Table 30. Timing Specification ata_isolation Sym Description Min Max Units SpecID 1 ata_isolation setup time 7 - IP Bus cycles A8.48 2 ata_isolation hold time - 19 IP Bus cycles A8.49 DIOR ATA_ISOLATION 1 2 Figure 27. Timing Diagram-ATA-ISOLATION MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 43 Electrical and Thermal Characteristics 3.3.9 Ethernet AC Test Timing Conditions: • Output Loading All Outputs: 25 pF Table 31. MII Rx Signal Timing Sym Description Min Max Unit SpecID M1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 10 — ns A9.1 M2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 10 — ns A9.2 M3 RX_CLK pulse width high 35% 65% RX_CLK Period1 A9.3 M4 RX_CLK pulse width low 35% 65% RX_CLK Period1 A9.4 NOTES: 1 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification [6]. M3 RX_CLK (Input) M4 RXD[3:0] (inputs) RX_DV RX_ER M1 M2 Figure 28. Ethernet Timing Diagram—MII Rx Signal MPC5200 Data Sheet, Rev. 4 44 Freescale Semiconductor Electrical and Thermal Characteristics Table 32. MII Tx Signal Timing Sym Description Min Max Unit SpecID 0 25 ns A9.5 M5 TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER Delay M6 TX_CLK pulse width high 35% 65% TX_CLK Period1 A9.6 M7 TX_CLK pulse width low 35% 65% TX_CLK Period(1) A9.7 NOTES: 1 the TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification [6]. M6 TX_CLK (Input) M5 M7 TXD[3:0] (Outputs) TX_EN TX_ER Figure 29. Ethernet Timing Diagram—MII Tx Signal Table 33. MII Async Signal Timing Sym M8 Description CRS, COL minimum pulse width Min Max Unit SpecID 1.5 — TX_CLK Period A9.8 CRS, COL M8 Figure 30. Ethernet Timing Diagram—MII Async MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 45 Electrical and Thermal Characteristics Table 34. MII Serial Management Channel Signal Timing Sym Description Min Max Unit SpecID M9 MDC falling edge to MDIO output delay 0 25 ns A9.9 M10 MDIO (input) to MDC rising edge setup 10 — ns A9.10 M11 MDIO (input) to MDC rising edge hold 10 — ns A9.11 M12 MDC pulse width high1 160 — ns A9.12 M13 MDC pulse width low(1) 160 — ns A9.13 M14 MDC period2 400 — ns A9.14 NOTES: 1 MDC is generated by MPC5200 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5200 User Manual [1]. 2 The MDC period must be set to a value of less then or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5200 User Manual [1]. M12 M13 MDC (Output) M14 M9 MDIO (Output) MDIO (Input) M10 M11 Figure 31. Ethernet Timing Diagram—MII Serial Management 3.3.10 USB Table 35. Timing Specifications—USB Output Line Sym Description Min Max Units SpecID 1 USB Bit width1 83.3 667 ns A10.1 2 Transceiver enable time 83.3 667 ns A10.2 3 Signal falling time — 7.9 ns A10.3 4 Signal rising time — 7.9 ns A10.4 NOTES: 1 Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode). MPC5200 Data Sheet, Rev. 4 46 Freescale Semiconductor Electrical and Thermal Characteristics NOTE Output timing was specified at a nominal 50 pF load. 2 USB_OE 3 4 USB_TXN 1 1 4 3 USB_TXP Figure 32. Timing Diagram—USB Output Line 3.3.11 SPI Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Sym 1 Description Cycle time 2 Clock high or low time 3 Slave select clock delay 4 Min Max Units SpecID 4 1024 IP-Bus Cycle1 A11.1 1 2 512 IP-Bus Cycle A11.2 15.0 — ns A11.3 Output Data valid after Slave Select (SS) — 20.0 ns A11.4 5 Output Data valid after SCK — 20.0 ns A11.5 6 Input Data setup time 20.0 — ns A11.6 7 Input Data hold time 20.0 — ns A11.7 8 Slave disable lag time 15.0 — ns A11.8 9 Sequential transfer delay 1 — IP-Bus Cycle1 A11.9 10 Clock falling time — 7.9 ns A11.10 11 Clock rising time — 7.9 ns A11.11 NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. NOTE Output timing was specified at a nominal 50 pF load. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 47 Electrical and Thermal Characteristics 1 10 SCK (CLKPOL=0) Output 2 2 11 SCK (CLKPOL=1) Output 11 10 9 8 3 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 33. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym 1 Description Cycle time Min Max Units SpecID 4 1024 IP-Bus Cycle1 A11.12 1 2 512 IP-Bus Cycle A11.13 15.0 — ns A11.14 Output Data valid after Slave Select (SS) — 50.0 ns A11.15 5 Output Data valid after SCK — 50.0 ns A11.16 6 Input Data setup time 50.0 — ns A11.17 7 Input Data hold time 0.0 — ns A11.18 8 Slave disable lag time 15.0 — ns A11.19 9 Sequential Transfer delay 1 — IP-Bus Cycle1 A11.20 2 Clock high or low time 3 Slave select clock delay 4 NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. NOTE Output timing was specified at a nominal 50 pF load. MPC5200 Data Sheet, Rev. 4 48 Freescale Semiconductor Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 3 9 SS Input 6 7 MOSI Input 4 5 MISO Output Figure 34. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym 1 Description Cycle time Min Max Units SpecID 4 1024 IP-Bus Cycle1 A11.21 2 512 Cycle1 A11.22 15.0 — ns A11.23 — 20.0 ns A11.24 2 Clock high or low time IP-Bus 3 Slave select clock delay 4 Output data valid 5 Input Data setup time 20.0 — ns A11.25 6 Input Data hold time 20.0 — ns A11.26 7 Slave disable lag time 15.0 — ns A11.27 1 8 Sequential Transfer delay 1 — IP-Bus Cycle A11.28 9 Clock falling time — 7.9 ns A11.29 10 Clock rising time — 7.9 ns A11.30 NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. NOTE Output timing was specified at a nominal 50 pF load. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 49 Electrical and Thermal Characteristics 1 9 SCK (CLKPOL=0) Output 2 2 10 SCK (CLKPOL=1) Output 10 9 7 3 8 SS Output 4 MOSI Output 5 MISO Input 6 Figure 35. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 Cycle time 4 1024 IP-Bus Cycle1 A11.31 2 Clock high or low time 2 512 IP-Bus Cycle1 A11.32 3 Slave select clock delay 15.0 — ns A11.33 4 Output data valid — 50.0 ns A11.34 5 Input Data setup time 50.0 — ns A11.35 6 Input Data hold time 0.0 — ns A11.36 7 Slave disable lag time 15.0 — ns A11.37 8 Sequential Transfer delay 1 — IP-Bus Cycle1 A11.38 NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. NOTE Output timing was specified at a nominal 50 pF load. MPC5200 Data Sheet, Rev. 4 50 Freescale Semiconductor Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 7 3 SS Input 5 6 MOSI Input 4 MISO Output Figure 36. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 3.3.12 MSCAN The CAN functions are available as RX and TX pins at normal IO pads (I2C1+GPTimer or PSC2). There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured. 3.3.13 I2C Table 40. I2C Input Timing Specifications—SCL and SDA Sym 1 Description Start condition hold time Min Max Units SpecID 2 — IP-Bus Cycle1 A13.1 8 — 1 IP-Bus Cycle A13.2 2 Clock low period 4 Data hold time 0.0 — ns A13.3 6 Clock high time 4 — IP-Bus Cycle1 A13.4 7 Data setup time 0.0 — ns A13.5 1 8 Start condition setup time (for repeated start condition only) 2 — IP-Bus Cycle A13.6 9 Stop condition setup time 2 — IP-Bus Cycle1 A13.7 NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 51 Electrical and Thermal Characteristics Table 41. I2C Output Timing Specifications—SCL and SDA Sym 1 1 21 3 2 4 1 Description Min Max Units SpecID Cycle3 A13.8 Start condition hold time 6 — IP-Bus Clock low period 10 — IP-Bus Cycle3 A13.9 SCL/SDA rise time — 7.9 ns A13.10 Data hold time 7 — 51 SCL/SDA fall time — 7.9 ns A13.12 61 Clock high time 10 — IP-Bus Cycle3 A13.13 — IP-Bus Cycle3 A13.14 Cycle3 A13.15 A13.16 71 8 1 91 Data setup time 2 IP-Bus Cycle3 Start condition setup time (for repeated start condition only) 20 — IP-Bus Stop condition setup time 10 — IP-Bus Cycle3 A13.11 NOTES: 1 Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values 3 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. NOTE Output timing was specified at a nominal 50 pF load. 2 5 6 SCL 1 4 7 8 3 9 SDA Figure 37. Timing Diagram—I2C Input/Output 3.3.14 J1850 See the MPC5200 User Manual [1]. MPC5200 Data Sheet, Rev. 4 52 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.15 PSC 3.3.15.1 Codec Mode (8,16,24 and 32-bit) / I2S Mode Table 42. Timing Specifications—8,16, 24 and 32-bit CODEC / I2S Master Mode Sym Description Min Typ Max Units SpecID 40.0 — — ns A15.1 1 Bit Clock cycle time, programmed in CCS register 2 Clock pulse width — 50 — %1 A15.2 3 Bit Clock fall time — — 7.9 ns A15.3 4 Bit Clock rise time — — 7.9 ns A15.4 5 FrameSync valid after clock edge — — 8.4 ns A15.5 6 FrameSync invalid after clock edge — — 8.4 ns A15.6 7 Output Data valid after clock edge — — 9.3 ns A15.7 8 Input Data setup time 6.0 — — ns A15.8 NOTES: 1 Bit Clock cycle time NOTE Output timing was specified at a nominal 50 pF load. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 53 Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Output 2 3 2 4 BitClk (CLKPOL=1) Output 4 5 Frame (SyncPol = 1) Output Frame (SyncPol = 0) Output 3 6 7 TxD Output 8 RxD Input Figure 38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Master Mode Table 43. Timing Specifications — 8,16, 24, and 32-bit CODEC / I2S Slave Mode Sym 1 Description Bit Clock cycle time Min Typ Max Units SpecID 40.0 — — ns A15.9 A15.10 2 Clock pulse width — 50 — %1 3 FrameSync setup time 1.0 — — ns A15.11 4 Output Data valid after clock edge — — 14.0 ns A15.12 5 Input Data setup time 1.0 — — ns A15.13 6 Input Data hold time 1.0 — — ns A15.14 NOTES: 1 Bit Clock cycle time NOTE Output timing was specified at a nominal 50 pF load. MPC5200 Data Sheet, Rev. 4 54 Freescale Semiconductor Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 2 2 BitClk (CLKPOL=1) Input 3 Frame (SyncPol = 1) Input Frame (SyncPol = 0) Input 4 TxD Output 5 RxD Input 6 Figure 39. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Slave Mode 3.3.15.2 AC97 Mode Table 44. Timing Specifications — AC97 Mode Sym Description Min Typ Max Units SpecID 1 Bit Clock cycle time — 81.4 — ns A15.15 2 Clock pulse high time — 40.7 — ns A15.16 3 Clock pulse low time — 40.7 — ns A15.17 4 Frame valid after rising clock edge — — 13.0 ns A15.18 5 Output Data valid after rising clock edge — — 14.0 ns A15.19 6 Input Data setup time 1.0 — — ns A15.20 7 Input Data hold time 1.0 — — ns A15.21 NOTE Output timing was specified at a nominal 50 pF load. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 55 Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 4 Sync (SyncPol = 1) Output 5 3 2 Sdata_out Output 6 7 Sdata_in Input Figure 40. Timing Diagram — AC97 Mode 3.3.15.3 IrDA Mode Table 45. Timing Specifications — IrDA Transmit Line Sym Description Min Max Units SpecID 1 Pulse high time, defined in the IrDA protocol definition 0.125 10000 µs A15.22 2 Pulse low time, defined in the IrDA protocol definition 0.125 10000 µs A15.23 3 Transmitter rising time — 7.9 ns A15.24 4 Transmitter falling time — 7.9 ns A15.25 NOTE Output timing was specified at a nominal 50 pF load. 4 IrDA_TX (SIR / FIR / MIR) 1 2 3 Figure 41. Timing Diagram — IrDA Transmit Line MPC5200 Data Sheet, Rev. 4 56 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.15.4 SPI Mode Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.26 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.27 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A15.28 4 Output Data valid after Slave Select (SS) — 8.9 ns A15.29 5 Output Data valid after SCK — 8.9 ns A15.30 6 Input Data setup time 6.0 — ns A15.31 7 Input Data hold time 1.0 — ns A15.32 8 Slave disable lag time — 8.9 ns A15.33 9 Sequential Transfer delay, programable in the PSC CTUR / CTLR register 15.0 — ns A15.34 10 Clock falling time — 7.9 ns A15.35 11 Clock rising time — 7.9 ns A15.36 NOTE Output timing was specified at a nominal 50 pF load. 1 10 SCK (CLKPOL=0) Output 2 2 11 SCK (CLKPOL=1) Output 11 10 8 3 9 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 42. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 57 Electrical and Thermal Characteristics Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.37 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.38 3 Slave select clock delay 1.0 — ns A15.39 4 Input Data setup time 1.0 — ns A15.40 5 Input Data hold time 1.0 — ns A15.41 6 Output data valid after SS — 14.0 ns A15.42 7 Output data valid after SCK — 14.0 ns A15.43 8 Slave disable lag time 0.0 — ns A15.44 9 Minimum Sequential Transfer delay = 2 * IP Bus clock cycle time 30.0 — — A15.45 NOTE Output timing was specified at a nominal 50 pF load. 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 3 9 SS Input 5 4 MOSI Input 6 7 MISO Output Figure 43. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) MPC5200 Data Sheet, Rev. 4 58 Freescale Semiconductor Electrical and Thermal Characteristics Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.46 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.47 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A15.48 4 Output data valid — 8.9 ns A15.49 5 Input Data setup time 6.0 — ns A15.50 6 Input Data hold time 1.0 — ns A15.51 7 Slave disable lag time — 8.9 ns A15.52 8 Sequential Transfer delay, programable in the PSC CTUR / CTLR register 15.0 — ns A15.53 9 Clock falling time — 7.9 ns A15.54 10 Clock rising time — 7.9 ns A15.55 NOTE Output timing was specified at a nominal 50 pF load. 1 9 SCK (CLKPOL=0) Output 2 2 10 SCK (CLKPOL=1) Output 10 9 7 3 8 SS Output 4 MOSI Output 5 MISO Input 6 Figure 44. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 59 Electrical and Thermal Characteristics Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.56 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.57 3 Slave select clock delay 0.0 — ns A15.58 4 Output data valid — 14.0 ns A15.59 5 Input Data setup time 2.0 — ns A15.60 6 Input Data hold time 1.0 — ns A15.61 7 Slave disable lag time 0.0 — ns A15.62 8 Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time 30.0 — ns A15.63 NOTE Output timing was specified at a nominal 50 pF load. 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 7 3 8 SS Input 5 6 MOSI Input 4 MISO Output Figure 45. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) MPC5200 Data Sheet, Rev. 4 60 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.16 GPIOs and Timers 3.3.16.1 General and Asynchronous Signals The MPC5200 contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume a 133 MHz internal bus frequency. Figure 46 shows the GPIO Timing Diagram. Table 50 gives the timing specifications. Table 50. Asynchronous Signals Sym Description Min Max Units SpecID 7.52 — ns A16.1 tCK Clock Period tIS Input Setup for Async Signal 12 — ns A16.2 tIH Input Hold for Async Signals 1 — ns A16.3 tDV Output Valid — 15.33 ns A16.4 tDH Output Hold 1 — ns A16.5 tCK tDH tDV Output Input valid tIH tIS valid Figure 46. Timing Diagram—Asynchronous Signals MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 61 Electrical and Thermal Characteristics 3.3.17 IEEE 1149.1 (JTAG) AC Specifications Table 51. JTAG Timing Specification Sym Characteristic Min Max Unit SpecID — TCK frequency of operation. 0 25 MHz A17.1 1 TCK cycle time. 40 — ns A17.2 2 TCK clock pulse width measured at 1.5V. 1.08 — ns A17.3 3 TCK rise and fall times. 0 3 ns A17.4 10 — ns A17.5 5 — ns A17.6 5 — ns A17.7 15 — ns A17.8 0 30 ns A17.9 0 30 ns A17.10 4 TRST setup time to tck falling 5 TRST assert time. 6 7 8 Input data setup Input data hold edge1. time2. time2. 3. TCK to output data valid impedance3 9 TCK to output high 10 TMS, TDI data setup time. 5 — ns A17.11 11 TMS, TDI data hold time. 1 — ns A17.12 12 TCK to TDO data valid. 0 15 ns A17.13 13 TCK to TDO high impedance. 0 15 ns A17.14 . NOTES: TRST is an asynchronous signal. The setup time is for test purposes only. 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK. 1 1 2 TCK 2 VM 3 VM 3 VM VM = Midpoint Voltage Numbers shown reference Table 51. Figure 47. Timing Diagram—JTAG Clock Input MPC5200 Data Sheet, Rev. 4 62 Freescale Semiconductor Electrical and Thermal Characteristics TCK 4 TRST 5 Numbers shown reference Table 51. Figure 48. Timing Diagram—JTAG TRST TCK 6 DATA INPUTS 7 INPUT DATA VALID 8 DATA OUTPUTS OUTPUT DATA VALID 9 DATA OUTPUTS Numbers shown reference Table 51. Figure 49. Timing Diagram—JTAG Boundary Scan TCK 10 TDI, TMS 11 INPUT DATA VALID 12 TDO OUTPUT DATA VALID 13 TDO Numbers shown reference Table 51. Figure 50. Timing Diagram—Test Access Port MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 63 Package Description 4 Package Description 4.1 Package Parameters The MPC5200 uses a 27 mm x 27 mm TE-PBGA package. The package parameters are as provided in the following list: • Package outline 27 mm x 27 mm • Interconnects 272 • Pitch 1.27 mm 4.2 Mechanical Dimensions Figure 51 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200, 272 TE-PBGA package. MPC5200 Data Sheet, Rev. 4 64 Freescale Semiconductor Package Description PIN A1 INDEX D C 0.2 4X A 272X 0.2 A E 0.35 A E2 D2 0.2 M NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A. 4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. A B C B TOP VIEW DIM A A1 A2 A3 b D D1 D2 E E1 E2 e (D1) 19X 19X e Y W V U T R P N M L K J H G F E D C B A e (E1) 4X e /2 A1 A3 A2 A SIDE VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 b 3 272X BOTTOM VIEW MILLIMETERS MIN MAX 2.05 2.65 0.50 0.70 0.50 0.70 1.05 1.25 0.60 0.90 27.00 BSC 24.13 REF 23.30 24.70 27.00 BSC 24.13 REF 23.30 24.70 1.27 BSC 0.3 M A B C 0.15 M A CASE 1135A–01 ISSUE B DATE 10/15/1997 Figure 51. Mechanical Dimensions and Pinout Assignments for the MPC5200, 272 TE-PBGA MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 65 Package Description 4.3 Pinout Listings See details in the MPC5200 User Manual [1]. Table 52. MPC5200 Pinout Listing Name Alias Type Power Supply Output Driver Type Input Type Pull-up/ down SDRAM MEM_CAS MEM_CLK_EN CAS I/O VDD_MEM_IO DRV16_MEM TTL CLK_EN I/O VDD_MEM_IO DRV16_MEM TTL I/O VDD_MEM_IO DRV16_MEM TTL MEM_CS MEM_DQM[3:0] DQM I/O VDD_MEM_IO DRV16_MEM TTL MEM_MA[12:0] MA I/O VDD_MEM_IO DRV16_MEM TTL MEM_MBA[1:0] MBA I/O VDD_MEM_IO DRV16_MEM TTL MEM_MDQS[3:0] MDQS I/O VDD_MEM_IO DRV16_MEM TTL MEM_MDQ[31:0] MDQ I/O VDD_MEM_IO DRV16_MEM TTL MEM_CLK I/O VDD_MEM_IO DRV16_MEM TTL MEM_CLK I/O VDD_MEM_IO DRV16_MEM TTL I/O VDD_MEM_IO DRV16_MEM TTL I/O VDD_MEM_IO DRV16_MEM TTL MEM_RAS MEM_WE RAS PCI EXT_AD[31:0] I/O VDD_IO PCI PCI PCI_CBE_0 I/O VDD_IO PCI PCI PCI_CBE_1 I/O VDD_IO PCI PCI PCI_CBE_2 I/O VDD_IO PCI PCI PCI_CBE_3 I/O VDD_IO PCI PCI PCI_CLOCK I/O VDD_IO PCI PCI PCI_DEVSEL I/O VDD_IO PCI PCI PCI_FRAME I/O VDD_IO PCI PCI PCI_GNT I/O VDD_IO DRV8 TTL PCI_IDSEL I/O VDD_IO DRV8 TTL PCI_IRDY I/O VDD_IO PCI PCI PCI_PAR I/O VDD_IO PCI PCI PCI_PERR I/O VDD_IO PCI PCI PCI_REQ I/O VDD_IO DRV8 TTL PCI_RESET I/O VDD_IO PCI PCI PCI_SERR I/O VDD_IO PCI PCI PCI_STOP I/O VDD_IO PCI PCI MPC5200 Data Sheet, Rev. 4 66 Freescale Semiconductor Package Description Table 52. MPC5200 Pinout Listing (continued) Name Alias PCI_TRDY Type Power Supply Output Driver Type Input Type I/O VDD_IO PCI PCI Pull-up/ down Local Plus LP_ACK I/O VDD_IO DRV8 TTL LP_ALE I/O VDD_IO DRV8 TTL LP_OE I/O VDD_IO DRV8 TTL LP_RW I/O VDD_IO DRV8 TTL LP_TS I/O VDD_IO DRV8 TTL LP_CS0 I/O VDD_IO DRV8 TTL LP_CS1 I/O VDD_IO DRV8 TTL LP_CS2 I/O VDD_IO DRV8 TTL LP_CS3 I/O VDD_IO DRV8 TTL LP_CS4 I/O VDD_IO DRV8 TTL LP_CS5 I/O VDD_IO DRV8 TTL PULLUP ATA ATA_DACK I/O VDD_IO DRV8 TTL ATA_DRQ I/O VDD_IO DRV8 TTL PULLDOWN ATA_INTRQ I/O VDD_IO DRV8 TTL PULLDOWN ATA_IOCHRDY I/O VDD_IO DRV8 TTL PULLUP ATA_IOR I/O VDD_IO DRV8 TTL ATA_IOW I/O VDD_IO DRV8 TTL ATA_ISOLATION I/O VDD_IO DRV8 TTL Ethernet ETH_0 TX, TX_EN I/O VDD_IO DRV4 TTL ETH_1 RTS, TXD[0] I/O VDD_IO DRV4 TTL ETH_2 USB_TXP, TX, TXD[1] I/O VDD_IO DRV4 TTL ETH_3 USB_PRTPWR, TXD[2] I/O VDD_IO DRV4 TTL ETH_4 USB_SPEED, TXD[3] I/O VDD_IO DRV4 TTL ETH_5 USB_SUPEND, TX_ER I/O VDD_IO DRV4 TTL ETH_6 USB_OE, RTS, MDC I/O VDD_IO DRV4 TTL ETH_7 TXN, MDIO I/O VDD_IO DRV4 TTL MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 67 Package Description Table 52. MPC5200 Pinout Listing (continued) Alias Type Power Supply Output Driver Type Input Type ETH_8 RX_DV I/O VDD_IO DRV4 TTL ETH_9 CD, RX_CLK I/O VDD_IO DRV4 Schmitt ETH_10 CTS, COL I/O VDD_IO DRV4 TTL ETH_11 TX_CLK I/O VDD_IO DRV4 Schmitt ETH_12 RXD[0] I/O VDD_IO DRV4 TTL ETH_13 USB_RXD, CTS, RXD[1] I/O VDD_IO DRV4 TTL ETH_14 USB_RXP, UART_RX, RXD[2] I/O VDD_IO DRV4 TTL ETH_15 USB_RXN, RX, RXD[3] I/O VDD_IO DRV4 TTL ETH_16 USB_OVRCNT, CTS, RX_ER I/O VDD_IO DRV4 TTL ETH_17 CD, CRS I/O VDD_IO DRV4 TTL Name Pull-up/ down IRDA PSC6_0 IRDA_RX, TxD I/O VDD_IO DRV4 TTL PSC6_1 RxD I/O VDD_IO DRV4 TTL PSC6_2 Frame, CTS I/O VDD_IO DRV4 TTL PSC6_3 IR_USB_CLK,BitC lk, RTS I/O VDD_IO DRV4 TTL USB USB_0 USB_OE I/O VDD_IO DRV4 TTL USB_1 USB_TXN I/O VDD_IO DRV4 TTL USB_2 USB_TXP I/O VDD_IO DRV4 TTL USB_3 USB_RXD I/O VDD_IO DRV4 TTL USB_4 USB_RXP I/O VDD_IO DRV4 TTL USB_5 USB_RXN I/O VDD_IO DRV4 TTL USB_6 USB_PRTPWR I/O VDD_IO DRV4 TTL USB_7 USB_SPEED I/O VDD_IO DRV4 TTL USB_8 USB_SUPEND I/O VDD_IO DRV4 TTL USB_9 USB_OVRCNT I/O VDD_IO DRV4 TTL I2C I2C_0 SCL I/O VDD_IO DRV4 Schmitt I2C_1 SDA I/O VDD_IO DRV4 Schmitt I2C_2 SCL I/O VDD_IO DRV4 Schmitt MPC5200 Data Sheet, Rev. 4 68 Freescale Semiconductor Package Description Table 52. MPC5200 Pinout Listing (continued) Name I2C_3 Alias Type Power Supply Output Driver Type Input Type SDA I/O VDD_IO DRV4 Schmitt Pull-up/ down PSC PSC1_0 TxD, Sdata_out, MOSI, TX I/O VDD_IO DRV4 TTL PSC1_1 RxD, Sdata_in, MISO, TX I/O VDD_IO DRV4 TTL PSC1_2 Mclk, Sync, RTS I/O VDD_IO DRV4 TTL PSC1_3 BitClk, SCK, CTS I/O VDD_IO DRV4 TTL PSC1_4 Frame, SS, CD I/O VDD_IO DRV4 TTL PSC2_0 TxD, Sdata_out, MOSI, TX I/O VDD_IO DRV4 TTL PSC2_1 RxD, Sdata_in, MISO, TX I/O VDD_IO DRV4 TTL PSC2_2 Mclk, Sync, RTS I/O VDD_IO DRV4 TTL PSC2_3 BitClk, SCK, CTS I/O VDD_IO DRV4 TTL PSC2_4 Frame, SS, CD I/O VDD_IO DRV4 TTL PSC3_0 USB_OE, TxDS, TX I/O VDD_IO DRV4 TTL PSC3_1 USB_TXN, RxD, RX I/O VDD_IO DRV4 TTL PSC3_2 USB_TXP, BitClk, RTS I/O VDD_IO DRV4 TTL PSC3_3 USB_RXD, Frame, SS, CTS I/O VDD_IO DRV4 TTL PSC3_4 USB_RXP, CD I/O VDD_IO DRV4 TTL PSC3_5 USB_RXN I/O VDD_IO DRV4 TTL PSC3_6 USB_PRTPWR, Mclk, MOSI I/O VDD_IO DRV4 TTL PSC3_7 USB_SPEED. MISO I/O VDD_IO DRV4 TTL PSC3_8 USB_SUPEND, SS I/O VDD_IO DRV4 TTL PSC3_9 USB_OVRCNT, SCK I/O VDD_IO DRV4 TTL GPIO/TIMER GPIO_WKUP_6 MEM_CS1 I/O VDD_MEM_IO DRV16_MEM TTL GPIO_WKUP_7 I/O VDD_IO DRV8 TTL TIMER_0 I/O VDD_IO DRV4 TTL PULLUP_MEM MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 69 Package Description Table 52. MPC5200 Pinout Listing (continued) Name Alias TIMER_1 Type Power Supply Output Driver Type Input Type I/O VDD_IO DRV4 TTL Pull-up/ down TIMER_2 MOSI I/O VDD_IO DRV4 TTL TIMER_3 MISO I/O VDD_IO DRV4 TTL TIMER_4 SS I/O VDD_IO DRV4 TTL TIMER_5 SCK I/O VDD_IO DRV4 TTL TIMER_6 I/O VDD_IO DRV4 TTL TIMER_7 I/O VDD_IO DRV4 TTL VDD_IO DRV4 Schmitt Schmitt Clock SYS_XTAL_IN SYS_XTAL_OUT RTC_XTAL_IN RTC_XTAL_OUT Input VDD_IO Output VDD_IO Input VDD_IO Output VDD_IO Misc Input PORRESET HRESET I/O VDD_IO DRV8_OD1 SRESET I/O VDD_IO DRV8_OD1 Schmitt IRQ0 I/O VDD_IO DRV4 TTL IRQ1 I/O VDD_IO DRV4 TTL IRQ2 I/O VDD_IO DRV4 TTL IRQ3 I/O VDD_IO DRV4 TTL Test/Configuration SYS_PLL_TPA I/O VDD_IO DRV4 TTL TEST_MODE_0 Input VDD_IO DRV4 TTL TEST_MODE_1 Input VDD_IO DRV4 TTL TEST_SEL_0 I/O VDD_IO DRV4 TTL TEST_SEL_1 I/O VDD_IO DRV8 TTL PULLUP JTAG_TCK TCK Input VDD_IO DRV4 TTL PULLUP JTAG_TDI TDI Input VDD_IO DRV4 TTL PULLUP JTAG_TDO TDO I/O VDD_IO DRV8 TTL JTAG_TMS TMS Input VDD_IO DRV4 TTL PULLUP JTAG_TRST TRST Input VDD_IO DRV4 TTL PULLUP MPC5200 Data Sheet, Rev. 4 70 Freescale Semiconductor System Design Information Table 52. MPC5200 Pinout Listing (continued) Name Alias Type Power Supply Output Driver Type Input Type Pull-up/ down Power and Ground VDD_IO - VDD_MEM_IO - VDD_CORE - VSS_IO/CORE - SYS_PLL_AVDD - CORE_PLL_AVDD - NOTES: All “open drain” outputs of the MPC5200 are actually regular three-state output drivers with the output data tied low and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200 I/O power rail if the external signal is driven above the MPC5200 I/O power rail voltage. 1 5 System Design Information 5.1 Power UP/Down Sequencing Figure 52 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL VDD (PLL_AVDD), and Core VDD (VDD_CORE). MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 71 DC Power Supply Voltage System Design Information 3.3V VDD_IO, VDD_IO_MEM (SDR) 2.5V VDD_IO_MEM (DDR) 1.5V 1 VDD_CORE, PLL_AVDD 2 0 Time Note: 1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time, including power-up. 2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM, VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up. 4. Use 1 microsecond or slower rise time for all supplies. Figure 52. Supply Voltage Sequencing The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE. 5.1.1 Power Up Sequence If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: Use one microsecond or slower rise time for all supplies. MPC5200 Data Sheet, Rev. 4 72 Freescale Semiconductor System Design Information VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. 5.1.2 Power Down Sequence If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: Drop VDD_CORE/PLL_AVDD to 0V. Drop VDD_IO/VDD_IO_MEM supplies. 5.2 System and CPU Core AVDD power supply filtering Each of the independent PLL power supplies require filtering external to the device. The following drawing is a recommendation for the required filter circuit. Power Supply source <1Ω 10 Ω AVDD device pin 10 µF 200-400 pF Figure 53. Power Supply Filtering 5.3 Pull-up/Pull-down Resistor Requirements The MPC5200 requires external pull-up or pull-down resistors on certain pins. 5.3.1 Pull-down Resistor Requirements for TEST pins The MPC5200 requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1. MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 73 System Design Information 5.3.2 Pull-up Requirements for the PCI Control Lines If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash Mode. PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ. 5.3.3 Pull-up/Pull-down Requirements for MEM_MDQS pins (SDRAM) The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode. 5.4 JTAG The MPC5200 provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5200's imbedded Freescale (formerly Motorola) MPC603e G2_LE processor. This interface provides a means for executing test routines and for performing software development & debug functions. 5.4.1 JTAG_TRST Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted during power-on reset. 5.4.1.1 JTAG_TRST and PORRESET The JTAG interface can control the direction of the MPC5200 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5200 comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released. For more details refer to the Reset and JTAG Timing Specification. MPC5200 Data Sheet, Rev. 4 74 Freescale Semiconductor System Design Information PORRESET required assertion of JTAG_TRST optional assertion of JTAG_TRST JTAG_TRST Figure 54. PORRESET vs. JTAG_TRST 5.4.1.2 Connecting JTAG_TRST The wiring of the JTAG_TRST depends on the existence of a board-related debug interface (see Table 53 below). Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the MPC5200. 5.4.2 G2_LE COP/BDM Interface There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector. 5.4.2.1 Boards interfacing the JTAG port via a COP connector The MPC5200 functional pin interface and internal logic provides access to the embedded G2_LE processor core through the Freescale (formerly Motorola) standard COP/BDM interface. Table 53 gives the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order. Table 53. COP/BDM Interface Signals BDM Pin # MPC5200 I/O Pin BDM Connector Internal PullUp/Down External PullUp/Down I/O 1 16 — GND — — — 15 TEST_SEL_0 ckstp_out — — I 14 — KEY — — — 13 HRESET hreset 10k Pull-Up O 12 — GND — — 11 SRESET sreset 10k Pull-Up O 10 — N/C — — — 9 JTAG_TMS tms 100k Pull-Up 10k Pull-Up O — MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 75 System Design Information Table 53. COP/BDM Interface Signals (continued) BDM Pin # MPC5200 I/O Pin BDM Connector Internal PullUp/Down External PullUp/Down I/O 1 8 — N/C — — — 7 JTAG_TCK tck 100k Pull-Up 10k Pull-Up O 6 — VDD 2 — — — 5 See Note 3. halted 3 — — I 4 JTAG_TRST trst 100k Pull-Up 10k Pull-Up O 3 JTAG_TDI tdi 100k Pull-Up 10k Pull-Up O qack 4 — — O tdo — — I 2 1 See Note 4. JTAG_TDO NOTES: With respect to the emulator tool’s perspective: Input is really an output from the embedded G2_LE core. Output is really an input to the core. 2 From the board under test, power sense for chip power. 3 HALTED is not available from G2_LE core. 4 Input to the G2_LE core to enable/disable soft-stop condition during breakpoints. MPC5200 internal ties core_qack_ to GND in its normal/functional mode (always asserted). 1 For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended. To reset the MPC5200 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5200. The circuitry shown in Figure 55 allows the COP to assert HRESET or JTAG_TRST separately, while any other board sources can drive PORRESET. MPC5200 Data Sheet, Rev. 4 76 Freescale Semiconductor System Design Information PORRESET PORRESET COP Header 13 11 10Kohm HRESET SRESET 1 2 3 4 5 6 7 8 9 10 11 12 13 K 15 16 4 62 Key 3 SRESET VDD JTAG_TRST 10Kohm TMS VDD JTAG_TMS 12 7 VDD TRST Key 14 9 MPC5200 VDD 10Kohm 10Kohm 16 COP Connector Physical Pinout HRESET 10Kohm TCK VDD VDD JTAG_TCK 10Kohm TDI VDD JTAG_TDI 15 1 CKSTP_OUT TEST_SEL_0 TDO JTAG_TDO halted 53 NC qack 4 2 NC 10 NC 8 NC Figure 55. COP Connector Diagram MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 77 System Design Information 5.4.2.2 Boards without COP connector If the JTAG interface is not used, JTAG_TRST should be tied to PORRESET, so that it is asserted when the system reset signal (PORRESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 56 shows the connection of the JTAG interface without COP connector. PORRESET PORRESET HRESET 10Kohm SRESET 10Kohm HRESET MPC5200 VDD VDD SRESET JTAG_TRST 10Kohm VDD JTAG_TMS 10Kohm VDD JTAG_TCK 10Kohm VDD JTAG_TDI TEST_SEL_0 JTAG_TDO Figure 56. JTAG_TRST wiring for boards without COP connector MPC5200 Data Sheet, Rev. 4 78 Freescale Semiconductor Ordering Information 6 Ordering Information Table 54. Ordering Information Part Number 7 Speed Ambient Temp Qualification MPC5200BV400 400 0C to 70C Commercial MPC5200CBV266 266 -40C to 85C Industrial MPC5200CBV400 400 -40C to 85C Industrial SPC5200CBV400 400 -40C to 85C Automotive - AEC Document Revision History Table 55 provides a revision history for this hardware specification. Table 55. Document Revision History Rev. No. Substantive Change(s) 0.1 First Preliminary release with some TBD’s in spec tables (6/2003) 0.2 Added AC specs for missing modules, power-on sequence, misc other updates (7/2003) 0.2.1 Corrected maximum core operating frequency (7/2003) 0.3 Added Memory Interface Timing values, misc other updates (8/2003) 1.0 Added Information about JTAG_TRST (11/2003) 2.0 Added Power Numbers (Section 3.1.5), updated Oscillator and PLL Characteristics (Section 3.2), updated SDRAM AC Characteristics (Section 3.3.5) 3.0 Change to Freescale brand and format (8/2004) 4.0 Updates to LPC timing, DDR SDRAM timing, JTAG section, replaced TBD’s (1/2005) Rev 4 has been regenerated with the new Freescale appearance guidelines, the title was changed and the reference to www.mobilegt.com in the first paragraph (Note) was changed to www. freescale.com (3/2006). For more detailed information, refer to the following documentation: [1] MPC5200 User Manual MPC5200UM [2] PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors, Rev. 2: MPCFPE32B/AD [3] G2 Core Reference Manual, Rev. 0: G2CORERM/D [4] PCI Local Bus Specification, Revision 2.2, December 18, 1998 [5] ANSI ATA-4 Specification [6] IEEE 802.3 Specification (ETHERNET) MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 79 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] MPC5200 Rev. 4, 01/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved.