Freescale Semiconductor Advance Information Document Number: MC33810 Rev. 4.0, 2/2008 Automotive Engine Control IC 33810 The 33810 is an eight channel output driver IC intended for automotive engine control applications. The IC consists of four integrated low side drivers and four low side gate pre-drivers. The low side drivers are suitable for driving fuel injectors, solenoids, lamps, and relays. The four gate pre-drivers can function either as ignition IGBT gate pre-drivers or as general purpose MOSFET gate predrivers. When configured as ignition IGBT gate pre-drivers, additional features are enabled such as spark duration, dwell time, and ignition coil current sense. When configured as a general purpose gate predriver, the 33810 provides external MOSFETs with short circuit protection, inductive flyback protection and diagnostics. The device is packaged in a 32 pin (0.65mm pitch) exposed pad SOIC. ENGINE CONTROL EK SUFFIX (Pb-FREE) 98ARL10543D 32 PIN SOICW EP Features • Designed to operate over the range of 4.5V ≤ VPWR ≤ 36V • Quad ignition IGBT or MOSFET gate pre-driver with Parallel/SPI and/or PWM control • Quad injector driver with Parallel/SPI control • Interfaces directly to MCU using 3.3V / 5.0V SPI protocol • Injector driver current limit - 4.5A max. • Independent fault protection and diagnostics • VPWR standby current 10µA max. • Pb-free packaging designated by suffix code EK VDD VPWR VDD MCU MOSI SI Device Temperature Range (TA) Package PCZ33810EK/R2 -40°C to 125°C 32 SOICW-EP VBAT 33810 VBAT ORDERING INFORMATION OUT0 VBAT OUT1 OUT2 OUT3 GND SCLK SCLK VBAT VBAT VBAT FB0 CS CS MISO SO ETPU DIN0 ETPU DIN3 ETPU GIN0 FB2 ETPU GIN3 GD2 GPIO OUT EN ETPU SPKDUR ETPU NOMI ETPU MAXI GD0 VBAT FB1 GD1 FB3 GD3 RSP RSN Figure 1. MC33810 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006 - 2008. All rights reserved. VBAT VBAT INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWR VDD VDD VDD ~50µA ~50µA CS SI SCLK OUTEN VPWR, VDD V8.0 Analog V2.5 Logic POR, Over-voltage Under-voltage LOGIC CONTROL Oscillator Bandgap Bias ~15µA VDD ~15µA SPI INTERFACE V2.5 OUT0 OUT1 OUT2 OUT3 Outputs 0 to 3 SO Gate Control DIN0 VOC1 75µA ~50µA PARALLEL CONTROL Current Limit Temperature Limit Short/Open DIN1 + – ~50µA lLimit Exposed Pad PWM CONTROLLER DIN2 RS ~50µA DIN3 ~50µA NOMI,MAXI DAC SPARK DURATION + – SPI + – SPI FB0 FB1 FB2 FB3 GIN0 + VPWR − SPARK DAC GIN1 100µA VLVC Open Secondary ~50µA VOC GPGD Only ~50µA Low V Clamp GATE DRIVE CONTROL GIN2 GPGD Clamp ~50µA GD0 GD1 GD2 GD3 GIN3 ~50µA VDD NOMI + – DAC + – DAC ~50µA SPKDUR MAXI RSP RSN NOMI MAXI Exposed Pad GND Figure 2. 33810 Simplified Internal Block Diagram 33810 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS OUT0 FB0 GD0 CS SCLK SI SO VDD OUTEN DIN0 DIN1 DIN2 DIN3 GD1 FB1 OUT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OUT2 FB2 GD2 MAXI NOMI RSN RSP VPWR GIN0 GIN1 GIN2 GIN3 SPKDUR GD3 FB3 OUT3 Figure 3. 33810 Pin Connections Table 1. 33810 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 13. Pin Number Pin Name Pin Function Formal Name Definition 8 VDD Input Digital Logic Supply Voltage The VDD input supply voltage determines the interface voltage levels between the device and the MCU, and is used to supply power to the Serial Out buffer (SO), SPKDUR buffer, MAXI, NOMI, and pull-up current source for the Chip Select (CS). 6 SI Input Serial Input Data The SI input pin is used to receive serial data from the MCU. 5 SCLK Input Serial Clock Input The SCLK input pin is used to clock in and out the serial data on the SI and SO pins, while being addressed by the CS. 4 CS Input Chip Select The Chip Select input pin is an active low signal sent by the MCU to indicate that the device is being addressed. This input requires CMOS logic levels and has an internal active pull-up current source. 7 SO Output Serial Output Data The SO output pin is used to transmit serial data from the device to the MCU. 10, 11, 12, 13 DIN0,DIN1, DIN2,DIN3 Input Driver Input 0, Driver Input 1, Driver Input 2, Driver Input 3 Active HIGH input control for injector outputs OUT0 - 3. The parallel input data is logically OR’d with the corresponding SPI input data register contents. 24, 23, 22, 21 GIN0,GIN1, GIN2,GIN3 Input Gate Driver Input 0 Gate Driver Input 1 Gate Driver Input 2 Gate Driver Input 3 These pins are the active HIGH input control for IGBT/General Purpose Gate Driver outputs 0 - 3. The parallel input data is logically OR'd with the corresponding SPI input data register contents in General Purpose Mode Only. Spark Duration Output This pin is the Spark Duration Output. This open drain output is low while feedback inputs FB0 through FB3 are above the programmed spark detection threshold. 20 SPKDUR Output 25 VPWR Input Exposed Pad GND Ground Ground OUTEN Input Output Enable Analog Supply Voltage VPWR is the main voltage input for all internal analog bias circuitry. (bottom of package) 9 This exposed pad is the only ground reference for analog, digital and power ground connections. The Output Enable pin (OUTEN) is an active low input. When the OUTEN pin is low, the device outputs are active. The outputs are disabled when OUTEN is high. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33810 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 13. Pin Number Pin Name Pin Function Formal Name Definition 29 MAXI Output Maximum Ignition Coil Current This pin is the Maximum Ignition Coil Current output flag. This output is asserted when the IGBT Collector-Emitter current exceeds the selected level of the DAC. This signal also latches off the gate pre-drive outputs when configured as a General Purpose Gate pre-Driver. The MAXI current level is determined by the voltage drop across an external sense resistor connected to pins RSP and RSN. 28 NOMI Output Nominal Ignition Coil Current 2, 15, 31, 18 FB0 - FB3 Input Feedback Voltage Sense In IGBT ignition gate pre-driver mode, these feedback inputs monitor the IGBT's collector voltage to provide the spark duration timer control signal. 3, 14, 30,19 GD0 -GD3 Output Gate Drive Output IGBT/General Purpose Gate pre-driver outputs are controlled by GIN0 GIN3. Pull-up and pull-down current sources are used to provide a controlled slew rate to an external IGBT or MOSFET connected as a low side driver. 26 RSP Input Resistor Sense Positive This pin is the Positive input of a current sense amplifier. 27 RSN Input Resistor Sense Negative This pin is the Negative input of a current sense amplifier. Output Low Side Injector Driver Output 1, 16, 32, 17 OUT0 -OUT3 This pin is the Nominal Ignition Coil Current output flag. This output is asserted when the IGBT Collector-Emitter current exceeds the level selected by the DAC. These pin are the Open drain low side injector driver outputs. 33810 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Ratings Symbol Value Unit VPWR -1.5 to 45 VDC VDD -0.3 to 7.0 VDC VIL -0.3 to VDD VDC VFB -1.5 to 60 VDC VOUTX -1.5 to 60 VDC VGDx -0.3 to 10 VDC ECLAMP 100 mJ ECLAMP 100 mJ IOSSSS 2.0 A Maximum Voltage for RSN and RSP inputs VRSX -0.3 - VDD VDC Frequency of SPI Operation (VDD = 5.0V) – 6.0 MHz VESD1 VESD2 VESD3 ±2000 ±200 ±750 Ambient TA -40 to 125 Junction2 TJ -40 to 150 Case TC -40 to 125 TSTG -55 to 150 °C PD 1.7 W ELECTRICAL RATINGS VPWR Supply Voltage(1) VDD Supply Voltage(1) SPI Interface and Logic Input Voltage (CS, SI, SO, SCLK, OUTEN, DIN0 - DIN3, GIN0 - GIN3, SPKDUR, NOMI, MAXI, RSP,RSN) IGBT/General Purpose Gate Pre-driver Drain Voltage (VFB0 to VFB3) Injector Output Voltage (OUTx) General Purpose Gate Pre-driver Output Voltage (GDx) Output Clamp Energy (OUT0 to OUT3)(Single Pulse) VIH TJUNCTION = 150°C, IOUT = 1.5A Output Clamp Energy (OUT0 to OUT3)(Continuous Pulse) TJUNCTION = 125°C, IOUT = 1.0A (Max Injector frequency is 70Hz) Output Continuous Current (OUT0 to OUT3) TJUNCTION = 150°C ESD Voltage (2), (3) Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) V THERMAL RATINGS °C Operating Temperature Storage Temperature Power Dissipation (TA = 25°C) Peak Package flow Temperature During Solder Mounting °C TSOLDER DWB Suffix 240 EW Suffix 245 Thermal Resistance Junction-to-Ambient Junction- to-Lead Junction-to-Flag °C/W RθJA RθJL RθJC 75 8.0 1.2 Notes 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. ESD data available upon request. 3. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-002), the Machine Model (MM) (AEC-Q100003), and the Charge Device Model (CDM), Robotic (AEC-Q100-011). 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, -40°C ≤ TC ≤ 125°C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13V, TA = 25°C. Characteristic Symbol Min Typ Max Unit VPWR (FO) 4.5 9.0 – 36 18 V POWER INPUT (VDD, VPWR) Supply Voltage(4) Fully Operational Full Parameter Specification Supply Current IVPWR (ON) All Outputs Disabled (Normal Mode) mA – Sleep State Supply Current (Must have VDD ≤ 0.8V for sleep state), 10.0 14.0 µA IVPWR (SS) VPWR = 18V – 15 30 VPWR(OV) 36.5 39 42 V VPWR(OV-HYS) 0.5 1.5 3.0 V VPWR(UV) 3.0 4.0 4.4 V VPWR(UV-HYS) 100 200 300 mV VPWR(LOV) 5.3 – 8.99 V VDD Supply Voltage VDD 3.0 – 5.5 V VDD Supply Current IVDD – – 1.0 0.8 2.5 2.8 – – 0.3 – 0.2 – – – – 3.0 – 6.0 A 2.0 2.5 3.0 V 40 75 100 VPWR Over-voltage Shutdown Threshold Voltage(5) VPWR Over-voltage Shutdown Hysteresis Voltage VPWR Under-voltage Shutdown Threshold Voltage (6) VPWR Under-voltage Shutdown Hysteresis Voltage VPWR Low Operating Voltage (Low-voltage reported via the SPI)(7) Static Condition and does not include VDD current out of device VDD Supply Under-voltage (Sleep State) Threshold Voltage(8) VDD(UV) mA V INJECTOR DRIVER OUTPUTS (OUT 0:3) Drain-to-Source ON Resistance IOUT = 1.0A, TJ = 125°C, VPWR = 13V IOUT = 1.0A, TJ = 25°C, VPWR = 13V IOUT = 1.0A, TJ = -40°C, VPWR = 13V Output Self Limiting Current Output Fault Detection Voltage IOUT (LIM) Threshold(9) Ω RDS (ON) VOUT(FLT-TH) Outputs Programmed OFF (Open Load) Outputs Programmed ON (Short to Battery) Output OFF Open Load Detection Current Output ON Open Load Detection Current Current less then specification value considered open µA I(OFF)OCO VDRAIN = 18V, Outputs Programmed OFF I(ON)OCO mA 20 100 200 Notes 4. These parameters are guaranteed by design, but not production tested. Fully operational means driver outputs will toggle as expected with input toggling. SPI is guaranteed to be operational when VPWR > 4.5V. SPI may not report correctly when VPWR < 4.5V. 5. Over-voltage thresholds minimum and maximum include hysteresis. 6. Under-voltage thresholds minimum and maximum include hysteresis. 7. Device is functional provided TJ is less than 150°C. Some table parameters may be out of specification. 8. 9. Device in Sleep State, returns from sleep state with power on reset. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts. 33810 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, -40°C ≤ TC ≤ 125°C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13V, TA = 25°C. Characteristic Symbol Min Typ Max Unit INJECTOR DRIVER OUTPUTS (OUT 0:3) (Continued) Output Clamp Voltage 1 VOC1 ID = 20mA Output Leakage Current V 48 53 58 – – – – – – 20 3000 10 TLIM 155 – 185 °C TLIM (HYS) 5.0 10 15 °C V GS (ON) V GS (OFF) 5 0 7.0 0.375 9.0 0.5 V R GS (PULLDOW 100 200 300 KΩ µA IOUT (LKG) VDD = 5.0V, VDRAIN = 24V, Open Load Detection Current Disabled VDD = 5.0V, VDRAIN = VOC - 1.0V, Open Load Detection Current Disabled VDD = 0V, VDRAIN = 24V, Sleep State Over-temperature Shutdown(10) Over-temperature Shutdown Hysteresis(10) IGNITION (IGBT) GATE DRIVER PARAMETERS (GD 0:3 FB0:3) Gate Drive Output Voltage IGD = 500µA IGD = -500µA Sleep Mode Gate to Source Resistor N) Sleep Mode FBx pin Leakage Current µA IFBX (LKG) VDD = 0V, VFBx = 24V, – Feedback Sense Current (FBx Input Current) – 1.0 µA IFBX(FLT-SNS) FBx = 18V, Outputs Programmed OFF 1.0 Gate Drive Source Current (1 ≤ VGD ≤ 3) Gate Drive Turn Off Resistance I GATEDRIVE 685 780 875 µA Ω RDS(ON) 500 – 1000 VPWR +9.0 VPWR +11 VPWR + 13 18 21 24 2.0 4.9 7.4 9.9 2.75 5.5 8.2 11.00 3.5 6.1 9.1 12.1 11.5 – 15.5 – 4.0 SOFT SHUTDOWN FUNCTION (VOLTAGES REFERENCED TO IGBT COLLECTOR) Low Voltage Flyback Clamp Driver Command Off, Soft Shutdown Enabled, GDx = 2.0V VLVC Spark Duration Comparator Threshold (referenced to IC Ground Tab) VTH-RISE Rising Edge Relative to VPWR Spark Duration Comparator Threshold (referenced to IC Ground Tab)(11) VTH-FALL Falling Edge Relative to VPWR, Default = 5.5V Assuming ideal external 10:1 voltage divider. Voltage measured at high end of divider, not at pin. Tolerance of divider not included Open Secondary Comparator Threshold (referenced from primary to V VTH-RISE Rising Edge Relative to GND. No hysteresis with 10:1 voltage divider. V V V CURRENT SENSE COMPARATOR (RSP, RSN) NOMI Trip Threshold Accuracy - Steady State Condition 3.0A across 0.02Ω (RSP - RSN = 60mV) 10.75A across 0.04Ω (RSP - RSN = 430mV) NOMITRIPTA % -4.0 Notes 10. This parameter is guaranteed by design, however is not production tested. 11. Assuming Ideal external 10:1 Voltage Divider. Tolerance of 10:1 Voltage Divider is not included. Voltage is measured on the High End of Divider - not at the pin. 10:1 N.3.A 10:1 Voltage Divider is produced using two resistors with a 9:1 resistance ratio by the basic formula: VOUT R1 ------------------ = ---------------------VIN R1 + R2 Where R2 = 9XR1 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, -40°C ≤ TC ≤ 125°C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13V, TA = 25°C. Characteristic Symbol Min Typ Max Unit 7.5 % – +15 % – 50 µA % of VT CURRENT SENSE COMPARATOR (RSP, RSN) (CONTINUED) MAXI Trip Threshold Accuracy Steady State Condition 6.0A across 0.02Ω (RSP - RSN = 120mV) 21A across 0.04Ω (RSP - RSN = 840mV) MAXI Trip Point During Overlapping Dwell Input Bias Current RSP and RSN MAXITRIPTA – -7.5 MAXITRIPOD -15 IBIASRSX -50 Comparator Hysteresis Voltage NOMI MAXI Input Voltage Range (Maximum voltage between RSN and RSP) Ground Offset Voltage Range NOMIHYS MAXIIHYS 40 – 60 40 – 60 VCMVRCMVR 0.0 – 2.0 V VGNDOVR -0.3 – 0.3 V IGD 1.0 2.0 5 mA V GS (ON) V GS (OFF) 5.0 7.0 9.0 V 0.0 0.2 0.5 V Maximum offset between RSN pin and IC Ground (Exposed Pad) GENERAL PURPOSE GATE DRIVER PARAMETERS (GD 0:3) Gate Drive Sink and Source Current Gate Drive Output Voltage IGD = 1mA IGD = -1mA Short to Battery Fault Detection Voltage Threshold VDS(FLT-TH) VDD = 5.0V, Outputs Programmed ON Programmable from 0.5V to 3.0V in 0.5V increments. (Table 14) Open Fault Detection Voltage Threshold (referenced to IC ground tab) V 2.0 2.5 3.0 40 75 100 48 53 58 µA IFBX(FLT-SNS) FBx = 18V, Outputs Programmed OFF Output Clamp Voltage +20% VDS(FLT-TH) VDD = 5.0V, Outputs Programmed OFF Output OFF Open Load Detection Current V -20% VOC Driver Command Off, Clamp Enabled, VGATE = 2.0V V DIGITAL INTERFACE Input Logic High-voltage Thresholds VIH 0.7 x VDD – VDD + 0.3 V Input Logic Low-voltage Thresholds VIL GND - 0.3 – 0.2 x VDD V VHYS 100 – 300 mV CIN – – 20 Input Logic-voltage Hysteresis Input Logic Capacitance Sleep Mode Input Logic Current VDD = 0V -10 – 10 30 50 100 5.0 15 25 -30 -50 -100 µA Input Logic Pull-down Current 0.8V to 5.0V (DINX and GINX) Input Logic Pull-down Current ILOGIC_PD OUT_EN = 0.0V, VDD = 5.0V µA ISI_PD 0.8V to 5.0V (SI) Input Logic Pull-up Current on OUT_EN pF µA I LOGIC_SS µA IOUT_EN_PU 33810 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, -40°C ≤ TC ≤ 125°C, and calibrated timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13V, TA = 25°C. Characteristic Symbol Min Typ Max Unit DIGITAL INTERFACE (CONTINUED) OUT_EN Leakage Current to VDD SCLK Pull-down Current SO High State Output Voltage CSO NOMI, MAXI High State Output Voltage INOMI-LOW = 250µA IMAXI-LOW = 250µA 10 µA -10 – 10 -30 -50 -100 – – 50 – 20 – VDD - 0.4 – – – – 0.4 30 70 100 – – 0.4 30 50 100 µA µA ISPKDUR_PV pF V V µA VSPKDUR_LO V VI_HIGH INOMI-HIGH = -1.0mA IMAXI-HIGH = -1.0mA NOMI, MAXI Low State Output Voltage – IPD ISPKDUR = 1.0mA Output Pull-up Current for SPKDUR µA VSO_LOW NOMI, MAXI = 0.8V, VDD = 5.0V SPKDUR Output Voltage µA VSO_HIGH ISO-LOW = 1.0mA NOMI, MAXI in V10 Mode Pull-down Current 25 ICS(LKG) ISO-HIGH = -1.0mA SO Low State Output Voltage 15 ICS_PU CS = 5.0V, VDD = 0V SO Input Capacitance in Tri-state Mode 5 -10 CS = 0V CS Leakage Current to VDD 50 ICS CS = VDD CS Pull-up Current – I TRISO 0V to 5.0V CS Input Current – I SCLK VSCLK = VDD Tri-state SO Output µA IOUT_EN(LKG) OUT_EN = 5.0V, VDD = 0V µA V VDD - 0.4 – – VI_LOW V – – 0.4 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions of 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, -40°C ≤ TC ≤ 125°C, and calibrated timers, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13V, TA = 25°C. Characteristic Symbol Min Typ Max Unit 1.0 – – 1.0 – – tSC 30 60 90 µs t(ON)OC 3.0 7.5 12 ms 10 15 ms 400 µs POWER INPUT Required Low State Duration on VPWR for Under-voltage Detect Required Low State Duration on VDD for Power On Reset µs tUV VPWR ≤ 0.2V µs t RESET VDD ≤ 0.2V INJECTOR DRIVERS Output ON Current Limit Fault Filter Timer (Short to Battery Fault) Output ON Open Circuit Fault Filter Timer Output Retry Timer tREF – Output OFF Open Circuit Fault Filter Timer t(OFF)OC 100 Output Slew Rate (No faster than 1.5µs from off to on and on to off) t SR(RISE) RLOAD = 14Ω, VLOAD = 14V V/µs 1.0 Output Slew Rate 5.0 10 t SR(FALL) RLOAD = 14Ω, VLOAD = 14V V/µs 1.0 Propagation Delay (Input Rising Edge OR CS to Output Falling Edge) 5.0 10 tPHL 1.0 5.0 µs tPLH 1.0 5.0 µs tPLH 0.2 1.0 µs tPHL 0.2 1.0 µs Input @ 50%VDD to Output voltage 90% of VLOAD Propagation Delay (Input Falling Edge OR CS to Output Rising Edge) Input @ 50%VDD to Output voltage 10% of VLOAD IGNITION & GENERAL PURPOSE GATE DRIVER PARAMETERS Propagation Delay (GINx Input Rising Edge OR CS to Output Rising Edge) Input @ 50%VDD to Output voltage 10% of V GS (ON) Propagation Delay (Input Falling Edge OR CS to Output Falling Edge) Input @ 50%VDD to Output voltage 90% of V GS (ON) IGNITION PARAMETERS Open Secondary Fault Timer accuracy (uncalibrated) -35 – 35 % Maximum Dwell Timer Accuracy (uncalibrated) -35 – 35 % (12) -35 – 35 % End of Spark Filter Accuracy (uncalibrated) Notes 12. This parameter is guaranteed by design, however it is not production tested. 33810 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions of 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, -40°C ≤ TC ≤ 125°C, and calibrated timers, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13V, TA = 25°C. Characteristic Symbol Min Typ Max Unit GENERAL PURPOSE GATE DRIVER PARAMETERS Short to Battery Fault Detection Filter Timer Accuracy VDS(flt-th) % VDD = High, Outputs Programmed ON Programmable from 30µs to 960µs in replicating increments Tolerance of timer after using calibration command -10 +10 Tolerance of timer before using calibration command -35 +35 Output OFF Open Circuit Fault Filter Timer t(OFF)OC µs VDD = 5.0V, Outputs Off Tolerance of timer before using calibration command 100 400 PWM Frequency 10Hz to 1.28kHz Tolerance after using calibration command PWMFREQ -10% 10% PWM Frequency 10Hz to 1.28kHz Tolerance before using calibration command PWMFREQ -35% 35% Gate Driver Short Fault Duty Cycle SPI DIGITAL INTERFACE GDSHRT_DC 1.0 3.0 % TIMING(13) Falling Edge of CS to Rising Edge of SCLK t LEAD Required Setup Time ns 100 – – 50 – – 16 – – 20 – – t R (SI) – 5.0 – ns t F (SI) – 5.0 – ns t SO (EN) – – 55 ns t SO (DIS) – – 55 ns t VALID – 25 55 ns tSTR 1.0 – – µs Calibrated Timer Accuracy t TIMER – – 10 % Un-calibrated Timer Accuracy t TIMER – – 35 % Falling Edge of SCLK to Rising Edge of CS t LAG Required Setup Time SI to Rising Edge of SCLK t SI (SU) Required Setup Time Rising Edge of SCLK to SI SI, CS, SCLK Signal Rise Time(14) Time(15) Time from Falling Edge of CS Low-impedance (16) Time from Rising Edge off CS to SO High-impedance Time from Falling Edge of SCLK to SO Data Valid Sequential Transfer Rate ns t SI (HOLD) Required Hold Time SI, CS, SCLK Signal Fall ns (18) (17) ns Time required between data transfers DIGITAL INTERFACE Notes 13. 14. 15. 16. 17. 18. These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface. This parameter is guaranteed by design, however it is not production tested. Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the fall of SCLK with 200pF load. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CS 0.2 VDD tLAG tLEAD 0.7 VDD 0.2 VDD SCLK tSI(SU) SI 0.7 VDD 0.2 VDD tSI(HOLD) MSB IN tSO(EN) SO 0.7 VDD 0.2 VDD tVALID MSB OUT tSO(DIS) LSB OUT 33810 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ANALOG SUPPLY VOLTAGE (VPWR) SERIAL INPUT DATA (SI) The VPWR pin is the battery input to the 33810 IC. The VPWR pin requires external reverse battery and transient protection. All IC analog current and internal logic current is provided from the VPWR pin. With VDD applied to the IC, the application of VPWR will perform a POR. The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 16 bits of information or multiples of 8 there of must be entered into the device. DIGITAL LOGIC SUPPLY VOLTAGE (VDD) The VDD input pin is used to determine communication logic levels between the microprocessor and the 33810 IC. Current from VDD is used to drive SO output and the pull-up current for CS. VDD must be applied for normal mode operation. Removing VDD from the IC will place the device in sleep mode. With VPWR applied to the IC, the application of VDD will perform a POR. GROUND (GND) The bottom pad or FLAG provides the only ground connection for the IC. The VPWR and VDD supplies are both referenced to the GND pad. The GND pad is used for both de-coupling the power supplies as well as power ground for the output drivers. Although the silicon die is epoxy attached to the top side of the pad, the pad must be grounded for proper electrical operation. SERIAL CLOCK INPUT (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33810. The SI data is latched into the input shift register on the rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the MCU to read on the rising edge of SCLK. With CS in a logic high state, signals on the SCLK and SI pins will be ignored and the SO pin is tri-state CHIP SELECT (CS) The system MCU selects the 33810 to receive communication using the chip select (CS) pin. With the CS in a logic low state, command words may be sent to the 33810 via the serial input (SI) pin, and status information is received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output and transfers status information into the SO buffer. Rising edge of the CS initiates the following operation: Disables the SO driver (high-impedance) Activates the received command word, allowing the 33810 to activate/deactivate output drivers. To avoid any spurious data, it is essential that the high-tolow and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. Internal to the 33810 device is an active pull-up to VDD on CS. SERIAL OUTPUT DATA (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All normal operating drivers are reported as zero, all faulted drivers are reported as one. The negative transition of CS enables the SO driver. The SI / SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. OUTPUT ENABLE (OUTEN) The OUTEN pin is an active low input. When the OUTEN pin is low, all the device outputs are active. The outputs are all disabled when OUTEN pin is high. SPI and parallel communications are still active in either state of OUTEN. FEEDBACK VOLTAGE SENSOR (FB0-FB3) The FBx pin has multiple functions for control and diagnostics of the external MOSFET/IGBT Ignition gate driver. In Ignition (IGBT) Gate Driver Mode, the feedback inputs monitor the IGBT's collector voltage to provide the spark duration timer control signal. The spark duration timer monitors this input to determine if the secondary clamp function should be activated. In secondary clamp mode, the IGBT's collector voltage is internally clamped to VPWR+11V. In the General Purpose Gate Driver mode, this input monitors the drain of an external MOSFET to provide shortcircuit and open circuit detection by monitoring the MOSFET's drain to source voltage. The filter timer and threshold voltage are easily programmed through SPI (See tables 18 and 19 for SPI messages). In General Purpose Gate Driver mode the FBx pin also provides a drain to gate clamp for fast turn off of inductive loads and external MOSFET protection. GATE DRIVER OUTPUT (GD0-GD3) The GDX pins are the gate drive outputs for an external MOSFET or IGBT. Internal to the device is a Gate to Source resistor designed to hold the external device in the OFF state while the device is in the POR or SLEEP state. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION LOW SIDE INJECTOR DRIVER OUTPUT (OUT0 OUT3) OUT0 - OUT3 are the Open drain low side (Injector) driver outputs. The drain voltage is actively clamped during turn off of inductive loads. These outputs can be connected in parallel for higher current loads provided the turn off energy rating is not exceeded. SPARK DURATION OUTPUT (SPKDUR) SPKDUR is the Spark Duration output. This open drain output is low while feedback inputs FB0 through FB3 are above the programmed spark detection threshold. This output indicates an ignition flyback event. Each feedback input (FB0 - FB3) is logically OR'd to drive the SPKDUR output. There is a 50µA pull up current source connected internally to the SPKDUR pin. RESISTOR SENSE POSITIVE (RSP) Resistor Sense Positive - Positive input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage across an external resistor connected between RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI comparators. Note: RSN and RSP must be grounded in V10 mode. RESISTOR SENSE NEGATIVE (RSN) Resistor Sense Negative - Negative input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage across an external resistor connected to RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI comparators. Note: RSN and RSP must be grounded in V10 mode. NOMINAL IGNITION COIL CURRENT (NOMI) Nominal ignition coil current output flag. This output is asserted when the output current exceeds the level selected by the DAC. NOMI can be configured as an input pin for V10 mode applications where the gate drive needs to be latched off by another device’s MAXI current sense amplifier output. The NOMI input will latch off gate drivers 5 and 6 when configured as a V10 mode ignition gate driver See Figure 10. MAXIMUM IGNITION COIL CURRENT (MAXI) Maximum ignition coil current output flag. This output is asserted when the output ignition coil current exceeds the selected level of the DAC. This signal also latches off the gate drive outputs when configured as an ignition gate driver. The MAXI current level is determined by the voltage drop across an external sense resistor connected to pins RSP and RSN. MAXI can be configured as an input pin for V10 applications where the gate drive needs to be latched off by another devices MAXI current sense amplifier output. The MAXI input will latch off gate drivers 7 and 8 when configured as ignition gate drive outputs See Figure 10. DRIVER INPUT (DIN0-DIN3), GATE DRIVER INPUT (GIN0-GIN3) Parallel input pins for OUT0-OUT3 low side drivers and GD0-GD3 gate drivers. Each parallel input control pin is active high and has an internal pull-down current sink. The parallel input data is logically OR’d with the corresponding SPI input data register contents, except for the ignition mode IGBT drivers. They are only controlled by the parallel inputs GIN0-GIN3. In GPGD mode, GIN0-GIN3 are logically OR’d with SPI input data. All outputs are disabled when the OUTEN pin is HIGH, regardless of the state of the command inputs. 33810 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Figure 4. Functional Internal Block Diagram POWER SUPPLY/POR The 33810 is designed to operate from 4.5V to 36V on the VPWR pin. The VPWR pin supplies power to all internal regulators, analog, and logic circuit blocks. The VDD supply is used for setting communication threshold levels and supplying power to the SO driver. This IC architecture provides a low quiescent current sleep mode. Applying VPWR and VDD to the device will generate a Power On Reset (POR) and place the device in the Normal State. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing a POR. with the corresponding SPI input data register contents. All outputs are disabled when the OUTEN pin is HIGH, regardless of the state of the command inputs. INJECTOR DRIVERS: OUT0 – OUT3 These pins are the Open drain low side (Injector) driver outputs. The drain voltage is actively clamped during turn off of inductive loads. These outputs can be connected in parallel for higher current loads, provided the turn off energy rating is not exceeded. IGNITION GATE PRE-DRIVERS: GD0 – GD3 MCU INTERFACE AND OUTPUT CONTROL This component provides parallel input pins for OUT0OUT3 low side drivers and GD0-GD3 gate drivers. Each parallel input control pin is active high and has an internal pulldown current sink. The parallel input data is logically OR’d These pins are the gate drive outputs for an external MOSFET or IGBT. Internal to the device is a Gate to Source resistor designed to hold the external device in the OFF state while the device is in the POR or Sleep State. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER SUPPLY The 33810 is designed to operate from 4.5V to 36V on the VPWR pin. The VPWR pin supplies power to all internal regulators, analog and logic circuit blocks. The VDD supply is used for setting communication threshold levels and supplying power to the SO driver. This IC architecture provides flexible microprocessor interfacing and low quiescent current sleep mode. POWER-ON RESET (POR) Applying VPWR and VDD to the device will generate a Power On Reset (POR) and place the device in the Normal State. The Power On Reset circuit incorporates a filter to prevent high frequency transients from causing a POR. All outputs are disabled when the OUTEN input pin is HIGH regardless of the SPI control registers or the logic level on the parallel input pins. With the OUTEN pin high, SPI messages may be sent and received by the device. Upon enabling the device (OUTEN low), outputs will be activated based on the state of the command register or parallel input. Table 5. Operational States VDD OUTEN OUTPUTS STATE L L X OFF Power Off L H X OFF POR H L X OFF SLEEP X OFF POR X OFF POR H MODES OF OPERATION In Normal State, the 33810 gate driver has three modes of operation, ignition Mode, GPGD (General Purpose Gate Driver) Mode and V10 mode.The operating mode of each gate driver may be set individually and is programmed using the Mode Select Command. MODE SELECT COMMAND VPWR H Control register settings from a Power-ON Reset (POR) are as follows: • All outputs off • IGNITION gate driver mode enabled (IGBT Ignition Mode). • PWM frequency and duty cycle control disabled. • Off State open load detection enabled (LSD) • MAXI dac set to 14A, NOMI DAC set to 5.5A • Spark detect level VIL DAC set to VPWR +5.5V • Open secondary timer set to 100µs • Dwell timer set 32ms • Soft shutdown disabled • Low-voltage flyback clamp disabled • Dwell overlap MAXI offset disabled The MODE Select Command is used to set the operating mode for the GDx gate driver outputs, over/under-voltage operation and to enable V10 Mode and the PWM generators. The Mode Select Command programmable features are listed below. • Ignition/GPGD Mode select (gate drivers) • V10 Mode enable • Over/Under-voltage operation for all drivers • GPGD PWM controller enable IGNITION/GPGD MODE SELECT L X OFF SLEEP H H L ACTIVE NORMAL H H H OFF NORMAL SLEEP STATE Sleep State is entered when the VDD supply voltage is removed from the VDD pin. In Sleep State all outputs are off. Applying VDD will force the device to exit the Sleep State and generates a POR. NORMAL STATE The default Normal State is entered when power is applied to the VPWR and VDD pins. The Ignition/General Purpose Gate Driver Mode select bits determine independently, the operating mode of each of the GDx gate driver outputs. Bits 8,9,10,11 correspond to GD0, GD1, GD2, GD3 respectively. Setting the bit to a logic 0 sets the GDx driver to the Ignition Mode. Setting the bit to a logic 1 commands the GDX driver to the General Purpose Mode and disables the ignition features for that particular gate driver (except the MAXI current shutdown feature). Further information on GDx gate driver in Ignition Mode and General Purpose Mode is provided later in this section of the data sheet. V10 MODE ENABLE BIT The V10 Enable bit allows the user to configure the device for 10 cylinder applications. When the V10 Mode is enabled, the device configures the NOMI pin and MAXI pin as digital inputs rather than outputs. The new MAXI input pin receives 33810 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES the MAXI shutdown signal for GD0 and GD2 and the new NOMI input pin receives the MAXI shutdown signal for GD1 and GD3. Further information on V10 Mode is provided in the V10 Application section. Note: RSN and RSP must be grounded in V10 Mode. OVER/UNDER-VOLTAGE SHUTDOWN/RETRY BIT The Over/Under-voltage Shutdown/Retry bit allows the user to select the global over and under-voltage fault strategy for all the outputs. In an over-voltage or under-voltage condition on the VPWR pin, all outputs are commanded off. The Over/Under-voltage control bit sets the operation of the outputs when returning from over/under- voltage. Setting the Over/Under-voltage bit to logic [1] will force all outputs to remain OFF when VPWR returns to normal level. To turn the output on again, the corresponding input pin or SPI bit must be reactivated. Setting the Over/Under-voltage bit to logic [0] will command all outputs to resume their previous state when VPWR returns to normal level. Table 6 below provides the output state when returning from over or under-voltage. Table 6. Over-voltage/Under-voltage Truth Table GINx DINx Input Pin SPI Bit Over/ Undervoltage Control Bit X X X 1 OFF X X 1 0 OFF 0 0 0* 0 OFF X 1 0* 0 ON 1 X 0* 0 ON OUTEN Input pin State When Returning From Over/Under-voltage * Default Setting Note: The SPI bit does not control the Gate Driver outputs in the Ignition Mode, only in the GPGD Mode. An under-voltage condition on VDD results in the global shutdown of all outputs and reset of all internal control registers. The VDD under-voltage threshold is between 0.8V and 2.8V PWMX ENABLE BIT Gate Driver outputs programmed as General Purpose Gate Drivers may be used as low frequency PWM outputs. The PWM generators are enabled via bits 0 through 3 in the Mode Select Command. Bits 0 through 3 correspond to outputs GD0 through GD3 respectively. Once the frequency and duty cycle are programmed through the PWM Frequency & DC command, the PWM output may be turned ON and OFF through the PWM enable bit. Further information on PWM control is provided in the General Purpose Gate Driver Mode section of this data sheet. IGNITION (IGBT) GATE DRIVER MODE The MC33810 contains dedicated circuitry necessary for automotive ignition control systems. Each gate driver may be individually configured as an Ignition Gate Driver with the following features: • • • • • • • • Spark duration signal Open secondary timer Soft shutdown control Low-voltage flyback clamp Ignition ignition coil current measurement MAXI output and control NOMI output Maximum dwell timer In the Ignition Mode, several control strategies are in place to control the IGBT for enhanced system performance. Information acquired from the FBx pin allows the device to produce a spark duration signal output (SPKDUR) and detect open secondary ignition coils. Based on the FBx signal and Spark Command register settings, the device performs the appropriate gate control (Low-voltage Flyback Clamp, Soft Shutdown) and produces the SPKDUR output. The FBx pin is connected to the collector of the IGBT through an external 9:1 resistor divider network. The recommended values for the resistor divider network is 36K and 4.02K, with the 36K resistor connected from the IGBT collector to the FBx pin and the 4.02K resistor connected from the FBx pin to ground. Additional controls to the gate driver are achieved by sensing the current through the external IGBT. The Resistor Sense Positive (RSP) and Resistor Sense Negative (RSN) inputs are use to measure the voltage across an external 20mΩ or 40mΩ current sense resistor. A gain select bit in the Spark Command SPI Command messages should be set to 1 (gain of 2) when using a 20mΩ current sense resistor. When using a 40mΩ current sense resistor, the gain select bit should be set to 0 (gain of 1 is the default value). The ignition coil current is compared with the output of the DACs which have been programmed via the SPI Commands. The comparison generates the Nominal Current signal (NOMI) and the Maximum Current signal (MAXI). Both signals have a low output when the ignition coil current is below the programmed DAC value and a high output when the current is above the programmed DAC value. When the GDx output is shutdown because of the control strategy, the output may be activated again by toggling the input control. SPARK COMMAND The Spark Command is an ignition mode command used to program the parameters for the ignition mode features listed below: • End spark threshold (EndSparkTh bits) • Open secondary fault timer (OSFLT bits) 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • • • • • • • Secondary clamp (secondary clamp bit) Soft shutdown enable (SoftShutDn bit) Ignition ignition coil current amplifier gain (Gain Sel bit) Overlapping dwell disable (Overlap Dwell Disable bit) Maximum dwell enable (MaxDwellEn bit) Maximum dwell timer (MaxDwellTimer bits) End of spark filter timer value Spark Command address and data bits are listed in Table 20 NOTE: Gate driver outputs programmed to be General Purpose Gate Drivers are not affected by the Spark Commands. SPARK DURATION SIGNAL The Spark Duration is defined as the beginning of current flow to the end of current flow across the spark plug gap. Because the extremely high-voltage ignition coil secondary output is difficult to monitor, corresponding lower voltage signals generated on the ignition coil primary are often used. The FBx pins monitor the ignition coil primary voltage (IGBT Collector) through a 10 to 1 voltage divider. When the IGBT is disabled, the rise in the FBx signal indicates a sparkout condition is occurring at the spark plug gap. The device considers the initial thresholds for spark duration to be VIH = VPWR + 21V for rising edge as measured on the collector of the IGBT. The spark duration falling edge reference is programmable via SPI through the End Spark Threshold bits 0 and 1 (See Table 7). Figure 5 illustrates a typical ignition event with dwell time and spark duration indicated. Figure 5. Ignition Coil Charge and Spark Event VPWR = 16.0V Default settings Begin spark threshold VIH = VPWR + 21V End spark threshold VIL = VPWR +5.5V The pulse width of the SPKDUR signal is measured by the MCU timer/input capture port to determine the actual spark duration. Spark duration information is then used by the MCU spark control algorithm to optimize the dwell time. Table 7. End Spark Threshold Spark Command Bit<b1,b0> End Spark Threshold (VIL) 00 VPWR + 2.75 01 VPWR + 5.5 10 VPWR + 8.2 11 VPWR + 11.0 OPEN SECONDARY TIMER A fault due to open in the ignition coil secondary circuit can be determined by waveforms established on the ignition coil primary during a spark event. The spark event is initiated by the turn off of the IGBT. The voltage on the collector of the IGBT rises up to the IGBT’s internal collector to gate clamp voltage (typically 400 volts). Collector to gate clamp events normally last 5µs to 50µs. In an open ignition coil secondary fault condition, the collector to gate clamp event lasts much longer. The oscilloscope waveform in Figure 6 and Figure 7 compare a normal spark signature with that of an open secondary fault condition signature. Figure 6. Normal Spark Event Ignition Coil Current, 5.0A/div DWELL Time SPKDUR~3.0ms Channel 1: GINx IGBT Gate Drive Channel 2: IGBT Collector Voltage Channel 3: IGBT Current @ 5.0A/Div 33810 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Figure 7. Open Secondary Spark Event The Low-voltage Clamp spreads out the energy dissipation over a longer period of time, thus allowing the use of a lower energy rated IGBTs. The internal low-voltage clamp is connected between the IGBT's collector (through an external resistor) and the IGBT's gate. The energy stored in the ignition coil is dissipated by the IGBT, not the internal clamp. The internal clamp only provides the bias to the IGBT. Several logical signals are required as inputs to activate the GDx Low-voltage Clamp feature. The GDx Low-voltage Clamp feature may be disabled through bit 4 of the Spark Command message. Figure 8. Low-voltage Clamp SPARK DURATION + – SPI + – SPI FB0 FB1 FB2 FB3 100µA Open Secondary VPWR + − 13V The Open Secondary timer is initiated on the rising edge of the ignition coil primary spark signal and terminated on the falling edge. The rising edge Open Secondary Threshold is VIH= 135V at primary, no hysteresis. The falling edge Open Secondary threshold is VIL = 135V. Collector to gate clamp durations that last longer than the selected Open Secondary Fault Time interval (Table 8) indicates a failed spark event. When the Open Secondary Fault Time is exceeded and the Low-voltage Clamp is enabled, the GDx output will activate the Low-voltage Clamp shown in figure 16. The Logic for this Low-voltage Clamp is defined in Figure 9 53V SPI input GATE DRIVE CONTROL Low V Clamp GPGD Clamp GD0 GD1 GD2 GD3 Figure 9. Low-voltage Clamp Logic OSFLT_En IGN Mode Table 8. Open Secondary Timer Spark Command Bits<b3,b2> Open Secondary Fault Timer OSFLT (µs) 00 10 01 20 10 50 11 100 LOW-VOLTAGE CLAMP The Low-voltage Clamp is an internal clamp circuit which biases the IGBT's gate voltage in order to control the collector to emitter voltage to VPWR+11V. This technique is used to dissipate the energy stored in the ignition coil over a longer period of time than if the internal IGBT clamp were used. In the open secondary fault condition, all of the stored energy in the ignition coil is dissipated by the IGBT. This fault condition requires the use of a higher energy rated IGBT than would otherwise be needed. Activate Low-voltage Clamp OSFLT MaxDwell MaxDwellEn SoftShutDnEn IGN Mode VPWR OVER-VOLTAGE OUTEN SOFT SHUTDOWN ENABLE The soft shutdown feature is enabled via the SPI by asserting control bit 5 in the Spark Command message. When enabled, the following events initiate a soft shutdown control of the gate driver. • OUTEN = High (Outputs Disabled) • Over-voltage on VPWR pin 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • Max dwell time Soft Shutdown is designed to prevent an ignition spark while turning off the external IGBT. The Low-voltage Clamp is activated to provide the mechanism for a soft shutdown. The Max Dwell gate turn off signal is a logically ANDed with the Soft Shutdown bit to activate a Low-voltage Active Clamp (See Figure 9). Table 10. Maximum Dwell Timer GAIN SELECT BIT The ignition coil current comparators are used to compare the programmed NOMI and MAXI DAC value with voltage across the external current sense resistor. When selecting a gain of two, the ignition coil current sense resistor must be reduced from 40mΩ to 20mΩ. OVERLAPPING DWELL ENABLE BIT Overlapping dwell occurs when two or more ignition mode drivers are commanded ON at the same time. In this condition, with the Overlapping Dwell Bit enabled the MAXI DAC threshold value is increased as a percentage of the nominal programmed value. The percent increase is determined by bit 5 through bit 7 of the DAC Command. Table 9. Overlapping Dwell Compensation DAC Command Bits<b7,b6,b5> Overlap Compensation (%) 000 0% 001 7% 010 15% 011 24% 100 35% (default) 101 47% 110 63% 111 80% MAXIMUM DWELL ENABLE BIT Bit 8, the Maximum Dwell Enable bit allows the user to enable the Maximum Dwell Gate Turnoff Feature. When the Max Dwell bit is programmed as logic 0 (disabled) the device will not perform a Low-voltage Clamp due to Max Dwell (See Figure 9). MAXIMUM DWELL GATE TURN OFF FEATURE In automotive ignition systems, dwell time is defined as the duration of time that an ignition coil is allowed to charge. The MC33810 starts the measure of time from the gate drive ON command. If the dwell time is greater than the Max Dwell Timer setting (Table 10), the offending ignition gate driver is commanded OFF. The Max Dwell Gate Turn Off Feature may be disabled via bit 8 of the Spark Command. When the feature is disabled, the Max Dwell fault bits are always logic 0. The Max Dwell Timer feature pertains to Ignition Mode only and does not affect gate drivers configured as general purpose gate drivers. Spark Command Bit<b11,b10,b9> MAX Dwell Timer MaxDwell (ms) 000 2 001 4 010 8 011 16 100 32 (default) 101 64 110 64 111 64 DAC COMMAND (DIGITAL TO ANALOG CONVERSION COMMAND) The DAC Command is an ignition mode command that sets the nominal ignition coil current (NOMI) and maximum ignition coil current (MAXI) DAC values. Bits 0 through 4 set the NOMI threshold value and, bits 8 through 11 set the MAXI threshold values. The DAC command and default values are listed in the SPI Command Summary Table 20. The NOMI output is used by the MCU as a variable in dwell and spark control algorithms. NOMI DAC BITS The NOMI output signal is generated by comparing the external current sense resistor differential voltage (Resistor Sense Positive, Resistor Sense Negative) with the SPI programmed NOMI DAC value. When the NOMI event occurs, the NOMI output pin is asserted (High). The NOMI output is only a flag to the MCU and it’s output does not affect the gate driver. When using a 20 mΩ resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 2, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =1. When using a 40mΩ resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 1, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =0. This is also the default value. The NOMI output provides a means to alert the MCU when the ignition coil primary current equals the value programmed into the NOMI DAC. In V10 Mode, the NOMI pin is reconfigured as a MAXI input pin from a third MC33810 device in the system. In this mode a NOMI input has effectively the same control as an internal MAXI signal. Further information is provided in the V10 Mode application section of this data sheet. 33810 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 11. Nominal Current DAC Select Table 11. Nominal Current DAC Select DAC Command Bits<4,3,2,1,0> NOMI Current (A) Differential Voltage (mV Rs = 20mΩ Differential Voltage (mV Rs = 40mΩ (Gain = 2) (Gain = 1) 00000 3.00 60 120 00001 3.25 65 130 00010 3.50 70 140 00011 3.75 75 150 00100 4.00 80 160 00101 4.25 85 170 00110 4.50 90 180 00111 4.75 95 190 01000 5.00 100 200 01001 5.25 105 210 01010 5.50 110 220 01011 5.75 115 230 01100 6.00 120 240 01101 6.25 125 250 01110 6.50 130 260 01111 6.75 135 270 10000 7.00 140 280 10001 7.25 145 290 10010 7.50 150 300 10011 7.75 155 310 DAC Command Bits<4,3,2,1,0> NOMI Current (A) Differential Voltage (mV Rs = 20mΩ Differential Voltage (mV Rs = 40mΩ (Gain = 2) (Gain = 1) 10100 8.00 160 320 10101 8.25 165 330 10110 8.50 170 340 10111 8.75 175 350 11000 9.00 180 360 11001 9.25 185 370 11010 9.50 190 380 11011 9.75 195 390 11100 10.00 200 400 11101 10.25 205 410 11110 10.50 210 420 11111 10.75 215 430 MAXI DAC BITS The MAXI control block provides a means to shut off all the ignition coil drivers if the current reaches a SPI programmable maximum level. Control is achieved by comparing the output of the current sense amplifier with a SPI programmed DAC value. The MAXI comparator disables all gate drivers configured as ignition drivers when the DAC MAXI setting is exceeded. When a MAXI event occurs, the MAXI bit in the fault status register is set and the MAXI pin is asserted (High). When using a 20mΩ resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 2, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =1. When using a 40mΩ resistor as the current sense resistor, the gain select of the differential amplifier connected to RSP and RSN, should be set to a gain of 1, via the SPI Command Message Spark Command (Command 0100, hex 4), Control bit 6 =0. This is also the default value. The MAXI fault bit in the SPI fault status register is cleared when the MAXI condition no longer exists and the SPI fault status register has been read by the MCU. In V10 Mode, the MAXI pin is configured as an input to receive the MAXI signal from a second MC33810 device in the system. In this mode a input MAXI signal has effectively the same control as an internal MAXI signal. Further information is provided in the V10 Mode application section of this specification. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES GENERAL PURPOSE GATE DRIVER MODE Table 12. Maximum Current DAC Select DAC Command Bit<b11,b10,b9,b8> Differential Differential MAXI Voltage (mV Voltage (mV Current (A) Rs = 20mΩ Rs = 40mΩ 0000 6.0 120 240 0001 7.0 140 280 0010 8.0 160 320 0011 9.0 180 360 0100 10.0 200 400 0101 11.0 220 440 0110 12.0 240 480 0111 13.0 260 520 1000 14.0 280 560 1001 15.0 300 600 1010 16.0 320 640 1011 17.0 340 680 1100 18.0 360 720 1101 19.0 380 760 1110 20.0 400 800 1111 21.0 420 840 Each gate driver can be individually configured as a General Purpose Gate Driver (GPGD) and controlled from the parallel GINx input pins, SPI Driver ON/OFF Command or may be programmed through the SPI for a specific frequency and duty cycle output (PWM). In General Purpose Gate Driver mode the gate drivers have the following features: • • • • Gate driver for discrete external MOSFET Off state open load detect On state short circuit protection Programmable drain threshold and duration timer for short fault detection • PWM frequency/duty cycle controller In GPGD Mode the GDx output is a current controlled output driver with slew rate control, gate to source clamp, passive pull-down resistor and a drain to gate clamp for switching inductive loads. Driver ON /OFF Command END OF SPARK FILTER BITS The ringing at the end of the Spark signatures waveform can cause erroneous detection of the End of Spark event. To eliminate the effect of this ringing, a low pass filter with variable time values can be selected. Four time values for the low pass filter have been provided with a zero value indicating that no low pass filtering is to be used. The End of Spark Filter bits specify a 0, 4µs, 16µs, or 32µs time interval to sample the spark ignition coil primary current to ignore the ringing at the end of spark. Table 13. End of Spark Filter Time Select End of Spark Filter Bits<11, 10, 9, 8> Filter Time 0000 0.0 0001 4.0 0010 16.0 0011 32.0 µs The Driver ON/OFF Command, bits 4 through 7 control gate drivers that have been Mode Select Command programmed as GPGD. A logic 1 in bits 4 through 7 will command the specific output ON. A logic 0 in the appropriate bit location commands the specific output Off. Also contained in the Driver ON/OFF Command are SPI control bits for the integrated LSD output drivers. Further information on LSD control is provided in the Low Side Injector Driver section of the data sheet. NOTE: Gate drivers programmed to IGNITION mode have parallel input control only, and cannot be turned off and on via SPI commands. GPGD Short Threshold Voltage Command Each GPGD driver is capable of detecting an open load in the off state and shorted load in the on state. All faults are reported through the SPI communication. For open load detection, a current source is placed between the FBx pin and ground of the IC. An open load fault is reported when the FBx voltage is less than the 2.5V threshold. Open load fault detect threshold is set internally to 2.5V and may not be programmed. A shorted load fault is reported when the FBx pin voltage is greater than the programmed short threshold voltage. The short to battery fault threshold voltage of the external MOSFET is programmed via the GPGD Short Threshold Voltage Command. Table 14 illustrates the bit pattern to select a particular threshold. Drain voltages less than the selected threshold are considered normal operation. Drain voltages greater than the selected threshold voltage are considered faulted. 33810 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES GPGD FLT Timer Bits Fault Timer Select 000 30µs Each gate driver is individually set to either, restore to the pre-fault state, or shutdown when a short fault is declared. By setting the Retry/Shutdown bit in the GPGD Fault Operation Command to logic 1 the specific output will try to go back to the pre-fault state when the fault is no longer declared, after a programmed “inhibit time”. The retry strategy will cause the output to try to return to the pre-fault state on a 1% duty cycle basis. For example: If the fault timer is set to 120µs and a fault is declared (drain voltage greater than the programmed threshold for greater than 120µs), the GDx output driver will be forced off for 12ms. After 12 ms has elapsed, if the inputs, GINx or SPI, have not tried to shut off the particular GDx output in the interim, the GDx output will try to set the external driver on again (the prefault state). A continued declared fault on the output would result in another 12ms shutdown period. By setting the Retry/Shutdown bit in the GPGD Fault Operation Command to logic 0 the specific output will shutdown and remain off when the short fault is declared. Only a reissue of the turn on command, via SPI or GINx, will force the output to try and turn on again. In the event that a GPGD is selected as a PWM controller and a short occurs on the output, the output retry strategy forces the output to a 1% duty cycle based on the fault timer setting. For example: If the fault timer is set to 120µs and a fault is detected (drain voltage greater than programmed threshold), the PWM output will be commanded off for 12ms and commanded ON again at the next PWM cycle. Care should be taken to select a fault timer that is shorter than the minimum duty cycle ON time of the PWM controller. Selecting a fault timer that is longer will allow the PWM controller to continue to drive the external MOSFET into a shorted load. 001 60µs PWM FREQUENCY/DUTY CYCLE COMMAND 010 120µs 011 240µs (default) 100 480µs 101 960µs 110 No Change 111 No Change The PWMx Freq & Duty Cycle command is use to program the GDx outputs with a frequency and duty cycle. Table 16 defines the user selectable output frequency. The frequency and duty cycle may be updated at any time using the PWM Freq&DC command, however the update will only begin on the next PWM rising edge time. Once the PWM Freq & DC registers are programmed and the PWM controller is enabled through the Mode Command the PWM outputs are turned ON and OFF via the GINx pin OR the SPI GPGD ON/OFF Command control bit. All Parallel and serial On and Off command updates to the PWM controller are synchronous with the rising edge of the previous PWM period. The truth table for GDx control in general purpose mode is provided in Table 8. Table 14. FBx Fault Threshold Select GPGD VDS FLT Bits FBx Fault Threshold Select 000 0.5V 001 1.0V 010 1.5V 011 2.0 (default) 100 2.5V 101 3.0V 110 No Change 111 No Change GPGD SHORT TIMER COMMAND The GPGD Short Timer Command allows the user to select the duration of time that the drain voltage is allowed to be greater than the programed threshold voltage without causing shutdown. External MOSFETS with drain voltages greater than the programed threshold for longer than the Fault Duration Timer are shutdown. Timer durations are listed in Table 15. Table 15. FBx Short Fault Timer Notes: Tolerance on this fault timer setting is ±10% after using the Calibration Command. GPGD FAULT OPERATION COMMAND The GPGD Fault Operation Command sets the operating parameters for the gate drivers under faulted conditions. A short fault is said to be “detected” when the drain source voltage, Vds, of the external MOSFET, exceeds the SPI programmed short threshold voltage. The short fault is said to be “declared” when the VDS over-voltage lasts longer than the SPI programmed “fault timer.” (short duration time > fault timer programmed value) The duty cycle of the PWM outputs is controlled by bits 06, inclusive. The duty cycle value is 1% per binary count from 1-100 with counts of 101-127 defaulting to 100%. For example, sending SPI command 101001000001100 would set GD1, PWM output to 10Hz and 12% duty cycle. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES V10 MODE . Table 16. Frequency Select PWM Freq&DC Command Bit<b9,b8,b7> Frequency Hz 000 10Hz (default) 001 20Hz 010 40Hz 011 80Hz 100 160Hz 101 320Hz 110 640Hz 111 1.28kHz Notes: Tolerance on selected frequency is ±10% after using the Calibration Command. Shorts to battery and open load faults will not be detected for frequency and duty cycle combinations inconsistent with fault timers. Table 17. Pre-driver GDx Output Control Mode Command IGN/GP Bit Driver On/OFF GPGD Bit PWMx Enable Bit GINx terminal GDx Output 1 0 X 0 OFF 1 0 0 1 ON 1 1 0 X ON 1 X 1 1 Freq/DC 1 1 1 X Freq/DC V10 Mode provides a method for monitoring 10 ignition events while using only two current sense resistors. This is achieved using three MC33810 devices. Two MC33810 devices are programmed as Normal Ignition mode outputs and one is programmed as a V10 ignition mode output. The ignition gate driver outputs are partitioned into two banks of five outputs each (See Figure 10). Each bank contains one or two driver(s) from the V10 device. Drivers in the V10 device are grouped in two’s (GD0&GD2, GD1&GD3). Current from each V10 mode IGBT group is monitored by the appropriate Normal Mode device (See Figure 10). The MAXI signal from one Normal Mode device is ported to the V10 Mode MAXI input pin. Likewise the MAXI signal from the second Normal Mode device is ported to the V10 Mode NOMI input pin. The V10 Mode NOMI/MAXI inputs are used as MAXI shutdown signals for the appropriate ignition gate drive group. V10 Mode contains the same features as Ignition Mode gate drivers with the following exceptions: • NOMI/MAXI configured as input pins • MAXI shutdown for GPGD disabled • NOMI/MAXI comparators disabled In V10 Mode, Spark Command bits 7 and 8 (Gain Select, Overlapping Dwell) are disabled. These two features are achieved through the Normal Mode devices. RSN and RSP must be grounded in V10 Mode. 33810 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Bank 1 IC 1 “Parent” IGBT1 (0-3) Gate Drive 0 IGBT14 GO1 GIN1 IGBT15 Gate Drive 1 GIN2 GIN1 GO3 GIN3 LOGIC LOGIC RSP1 VtNI RS1 NOMI Comparator Ign 1 VtMI Child Comparator Inputs Tied to GND VtNI NOMI GIN0 GO1 GIN1 GO2 GIN2 GO3 GIN3 IGBT27 4 GIN (0-3) LOGIC NOMI RSP2 NOMI disabled Ign 2 VtMI MAXI disabled MAXI Comparator Logic Buffer IGBT 2 (0-3) MAXI RSP GO0 IGBT26 GO3 Gate Drive 3 4 GIN (0-3) GIN (0-3) MAXI GIN0 Gate Drive 0 GO1 GO2 Gate Drive 3 4 NOMI GO0 Gate Drive 1 GO2 GIN2 Gate Drive 2 Gate Drive 2 GIN3 IC 2 “Parent” IC 3 “Child” GO0 GIN0 Bank 2 VtNI RS2 NOMI MAXI NOMI Comparator VtMI Logic Buffer Logic Buffer MAXI Comparator Logic Buffer Logic Buffer Logic Buffer MAXI MAXI MAXI NOMI NOMI NOMI1 to uP MAXI1 to uP MAXI2 to uP NOMI2 to uP Note: For “child” input NOMI is for channel 1&3, input MAXI is for channel 0&2 Figure 10. V10 Mode LOW SIDE INJECTOR DRIVER ON /OFF CONTROL COMMAND The four open drain low side injector drivers are designed to control various automotive loads such as injectors, solenoids, lamps, relays and unipolar stepper motors. Each driver includes off and on state open load detection, short circuit protection and diagnostics. The injector drivers are individually controlled through the ON/OFF SPI input command Table 20 or parallel input pins DIN0 to DIN3. Serial and parallel control of the output state is determined by the logical OR of the SPI serial bit and the DINx parallel input pins. All four outputs are disabled when the OUTEN input pin is high regardless of the state of the SPI control bit or the state of the DINx pin. All four injector drivers are not affected by the selection of the gate driver’s three modes of operation (Ignition Mode, General Purpose Mode, V10 mode). To program the individual output of the 33810 ON or OFF, a 16-bit serial stream of data is entered into the SI pin. The first 4 bits of the control word are used to identify the On / Off Command. Bit 0 through bit 3 of the ON/OFF Control Command turn ON or OFF the specific output driver. INJECTOR DRIVER FAULT COMMANDS Fault protection strategies for the injector drivers are programmed by the SPI LSD Fault Command. Bit 8 through 11 determine the type of short circuit protection to be used, bits 0 through 7 set the open load strategy. Short-circuit protection consists of three strategies. All strategies utilize current limiting as an active element to protect the output driver from failure.The TLIM and Timer options are used to enhance the short circuit protection strategy of the Injector drivers. The timer protection scheme uses a low duty cycle in the event of a short-circuit. The TLIM 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES protection circuit uses the junction temperature of the output driver to determine the fault. Both methods may be used together or individually. TIMER PROTECTION The first protection scheme uses a low ON to OFF duty cycle to protect the output driver. The low duty cycle allows the device to cool so that the maximum junction temperatures are not exceeded. During a short condition, the device enters current limit. The driver will shutdown for short conditions lasting longer than the current limit timer (~60µs) Table 18. Injector Driver (OUTx) Fault Operation Shutdn Retry Bit 11 TLIM Bit 10 Fault Timer Bit 9 Operation During Short Fault 1 0 X Timer only, Outputs will retry on period OUT0-OUT3 = 60 µs ON, ~10ms OFF 1 1 0 TLIM only, Outputs will retry on TLIM hysteresis. 1 1 1 Timer and TLIM, Outputs will retry on period and driver temperature below threshold. TEMPERATURE LIMIT (TLIM) The second scheme senses the temperature of the individual output driver. During a short event the device enters current limit and will remain in current limit until the output driver temperature limit is exceeded (TLIM). At this point, the device will shutdown until the junction temperature falls below the hysteresis temperature value. The TLIM hysteresis value is listed in the previous specification tables. The third method combines both protection schemes into one. During a short event the device will enter current limit. The output driver will shutdown for short conditions lasting longer than the current limit timer. In the event that the output driver temperature is higher than maximum specified temperature the output will shutdown. The Shutdown/Retry bit allows the user to determine how the drivers will respond to each short circuit strategy. Table 18 provides fault operation for all three strategies. Outputs may be used in parallel to drive higher current loads provided the turn-off energy of the load does not exceed the energy rating of a single output driver (100mJ maximum). OUT0-OUT3= 60 µs ON, ~10ms OFF 0 0 X Timer only, Outputs will not retry on period OUT0-OUT3 = 60 µs ON, OFF 0 1 0 TLIM only, Outputs will not retry on TLim hysteresis. 0 1 1 Timer and TLIM, Outputs will not retry on period or TLIM. OUT0-OUT3 = 60 µs ON, OFF OUTPUT DRIVER DIAGNOSTICS. Short to battery, Temperature Limit (TLIM) and open load faults are reported through the All Status Response message Table 21. OFF OPEN LOAD PULL-DOWN CURRENT ENABLE BITS An open load on the output driver is detected by the voltage level on the drain of the MOSFET in the off state. Internal to the device is a 75µA pull-down current sink. In the event of an open load the drain voltage is pulled low. When the voltage crosses the threshold, and open load is detected. The pull-down current source may be disabled by bit 0 through bit 3 in the LSD Fault Command. With the driver off and the Off Open Load bit disabled, the Off Open Load fault status bit will be logic 0. ON OPEN LOAD ENABLE BITS The On State Open Load enable bit allows the user to determine an On State Open Load. When the On State Open Load bit disabled, the On State Fault bit is always logic 0. On Open Load is determined by monitoring the current through the OUTx MOSFET. In the ON state, currents less than 20mA to 200mA are considered open. 33810 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 19. InjectorDriver Diagnostics Program State Fault temperature, calibration is required for an accurate time base. The calibration command should be used to update the device on a periodic basis. Fault Bits Off State Open Load Pull Dwn On State Open Load En Bit Driver On/Off Output STB STG OPEN OUTx Batt Short Fault OUTx OFF Open Fault 0 X Off STB 0 0 0 No Fault 0 X Off STG 0 0 0 No Fault 0 X Off OPEN 0 0 0 No Fault 1 X Off STB 0 0 0 No Fault 1 X Off STG 0 1 0 Open Load 1 X Off OPEN 0 1 0 Open Load X 0 On STB 1 0 0 Short to Batt X 0 On STG 0 0 0 No Fault X 0 On OPEN 0 0 0 No Fault X 1 On STB 1 0 0 Short to Batt X 1 On STG 0 0 1 Open Load X 1 On OPEN 0 0 1 Open Load OUTx ON Fault Reported Open Fault SPI COMMAND SUMMARY The SPI commands are defined as 16 bits with 4 address control bits and 12 command data bits. There are 12 separate commands that are used to set operational parameters of device. The operational parameters are stored internally in 16 bit registers. Table 20 defines the commands and default state of the internal registers at POR. SPI commands may be sent to the device at any time in NORMAL STATE. Messages sent are acted upon on the rising edge of the CS input. CLOCK CALIBRATION COMMAND In cases where an accurate time base is required, the user must calibrate the internal timers using the clock calibration command (refer to Table 20). After the 33810 device receives the calibration command, the device expects to receive a 32µs logic [0] calibration pulse on the CS pin. The pulse is used to calibrate the internal clock. Any SPI message may be sent during the 32µs calibration chip select. Because the oscillator frequency may shift up to 35% with . Table 20. SPI Command Message Set and Default State Command Control Address Bits Command Bits hex 15 14 13 12 11 10 9 8 Read Registers Command 0 0 0 0 0 1 0 1 0 All Status Command 0 0 0 0 0 1 0 1 0 0 0 0 SPI Check Command 0 0 0 0 0 1 1 1 1 0 0 Mode Select Command 1 0 0 0 1 <0000> IGN/GP Mode Select Set to IGN Mode 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X <0000> Internal Register Address <0> <0> V10 OVR/ En Undr Vtg Disab <0> <0> <0> <0> pwm3 pwm2 pwm1 pwm0 EN EN EN EN Disab Disab Disab Disab 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 20. SPI Command Message Set and Default State Command LSD Fault Command Control Address Bits hex 15 14 13 12 2 0 0 1 0 Command Bits 11 10 9 <10X> LSD Flt Operation shutdn,Tlim,Timer 8 X Retry on timer and No Tlim Driver ON/OFF Command 3 0 0 1 1 X X X 7 6 5 4 3 2 1 0 <1> <1> <1> <1> <1> <1> <1> <1> OUT3 OUT2 OUT1 OUT0 OUT3 OUT2 OUT1 OUT0 ON ON ON ON OFF OFF OFF OFF Open Open Open Open Open Open Open Open Load Load Load Load Load Load Load Load Enabl Enabl Enabl Enabl Enabl Enabl Enabl Enabl X <0000> GPGD OFF 0 = OFF, 1 = ON <0000> OUTx Driver OFF (ignored in Ignition Mode) Spark Command 4 0 1 0 0 <100> Max Dwell Timer MaxDwell Default=32ms (In Ignition Mode Only) <0> Max Dwell En Disab End Spark Filter 5 0 1 0 1 X DAC Command 6 0 1 1 0 <1000> MAXI DAC Threshold MAXI=14A X X X <0> <0> <0> <0> <11> Over Gain Soft Open Open lap Sel Shut 2ed Secondary Dwell Gain Dn En Clmp OSFLT Disab = 1 Disab Disab =100µs X X X X <100> X X <01> End Spark Threshold VPWR +5.5V <01> End Spark Thresh 4.0 µs <01010> NOMI DAC Threshold NOMI=5.5A Overlap Setting Overlap 50% GPGD Short Threshold Voltage Command 7 0 1 1 1 <011> Short to Batt VFB3 Vth = 2.0V <011> Short to Batt VFB2 Vth = 2.0V <011> Short to Batt VFB1 Vth = 2.0V <011> Short to Batt VFB0 Vth = 2.0V GPGD Short Duration Timer Command 8 1 0 0 0 <011> Short to Batt tFB3 Timer = 240µs <011> Short to Batt tFB2 Timer = 240µs <011> Short to Batt tFB1 Timer = 240µs <011> Short to Batt tFB0 Timer = 240µs GPGD Fault Operation Select Command 9 1 0 0 1 PWM0 to PWM3 Freq & DC Command A 1 0 1 0 <00> PWMx address PWM0 INVALID COMMAND B 1 0 1 1 X X X X X X X X X X X X INVALID COMMAND C 1 0 1 1 X X X X X X X X X X X X INVALID COMMAND D 1 1 0 1 X X X X X X X X X X X X Clock Calibration Command E 1 1 1 0 X X X X X X X X X X X X INVALID COMMAND F 1 1 1 1 X X X X X X X X X X X X <1111> Retry/Shutdown Bit Retry on Fault X X X <000> PWM Frequency 10Hz X <0000> Shutdown Drivers on MAXI Disabled <0000000> PWM Duty Cycle 0% Duty Cycle 33810 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SPI RESPONSE REGISTERS faults. Timing between two write words must be greater than the fault timer to allow adequate time to sense and report the proper fault status. . Fault reporting is accomplished through the SPI interface. All logic [1]s received by the MCU via the SO pin indicate faults. All logic [0]s received by the MCU via Pin indicate no Table 21. SPI Response Messages Next SO Response to: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0 SOR NMF 13 12 SOR NMF SPI Check Command Next SO Response to Reset COR HEX1 to HEX A Commands and Read All Status Command ALL STATUS RESPONSE Next SO Response to READ REGISTER COMMAND 15 14 IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0 Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault 11 10 9 8 7 6 5 4 3 2 1 0 Address <0000> All Status Register 0 = No Fault, 1 = Fault Reset COR Address <0001> OUT1, OUT0 Fault Register 0 = No Fault, 1 = Fault Reset COR OVER LOW Voltage Voltage 0 0 0 0 OUT1 OUT1 OUT1 OUT1 OUT0 OUT0 OUT0 OUT0 TLIM Batter OFF ON TLIM Batter OFF ON Fault y Open Open Fault y Open Open Short Fault Fault Short Fault Fault Fault Fault Address <0010> OUT3, OUT2 Fault Register 0 = No Fault, 1 = Fault Reset COR OVER LOW Voltage Voltage 0 0 0 0 OUT3 OUT3 OUT3 OUT3 OUT2 OUT2 OUT2 OUT2 TLIM Batter OFF ON TLIM Batter OFF ON Fault y Open Open Fault y Open Open Short Fault Fault Short Fault Fault Fault Fault Address <0011> GPGD Mode Fault Register 0 = No Fault, 1 = Fault Reset COR OVER LOW Voltage Voltage 0 0 0 0 GP3 Short Circuit Fault IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0 Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Address <0100> Reset COR OVER LOW IGN3 IGN3 IGN3 IGN2 IGN2 IGN Mode Fault Register Voltage Voltage MAXI Max Open MAXI Max 0 = No Fault, 1 = Fault Fault Dwell Secon Fault Dwell Fault d Fault Fault Address <0101> Reset COR OVER LOW Mode Command Register Voltage Voltage IGN/GP Mode Select V10 En GP3 Open Load Fault GP2 Short Circuit Fault GP2 Open Load Fault OVR Vtg X X Reset COR OVER LOW LSD Flt Operation Voltage Voltage shutdn,Tlim,Timer X OUT3 OUT2 OUT1 OUT0 ON ON ON ON Open Open Open Open Load Load Load Load Address <0111> Drvr ON/OFF Command Reg Reset COR OVER LOW Voltage Voltage X GPGD(19) Address <1000> Reset COR OVER LOW Spark Command Register Voltage Voltage X X Max Dwell Timer MaxDwell GP1 Open Load Fault GP0 Short Circuit Fault GP0 Open Load Fault IGN2 IGN1 IGN1 IGN1 IGN0 IGN0 IGN0 Open MAXI Max Open MAXI Max Open Secon Fault Dwell Secon Fault Dwell Secon d Fault d Fault d Fault Fault Fault Address <0110> LSD Fault Command Register X GP1 Short Circuit Fault Max Over Gain Soft Open Dwell lap Sel Shut 2ed En Dwell Dn En Clmp PWM PWM PWM PWM 3 2 1 0 EN EN EN EN OUT3 OFF Open Load OUT2 OFF Open Load OUT1 OFF Open Load OUT0 OFF Open Load OUTx Driver(19) Open Secondary End Spark Threshold Notes 19. These bits refer to command On or Off state in the command registers, not the state of the respective output lines. These bits are not to be confused with the ignition mode state which is controlled only by the parallel inputs and their state is not reflected in these bits. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 21. SPI Response Messages Address <0101> End Spark filter Register Reset COR OVER under Voltage voltage X X X X X X X X X X End spark Filter Address <1010> Reset COR OVER LOW DAC Command Register Voltage Voltage MAXI DAC Threshold Overlap Setting NOMI DAC Threshold Address <1011> Reset COR OVER LOW Short to Batt VFB3 GPGD FBx Short to Voltage Voltage Battery Threshold Voltage Register Short to Batt VFB2 Short to Batt VFB1 Short to Batt VFB0 Address <1100> GPGD FBx Short to Battery Threshold Timer Register Reset COR OVER LOW Voltage Voltage Short to Batt tFB2 Short to Batt tFB1 Short to Batt tFB0 Address <1101> GPGD Fault Operation Register Reset COR OVER LOW Voltage Voltage Address <1110> PWM Freq&DC Register (last channel programmed) Reset COR OVER LOW Voltage Voltage Address <1111> Revision ID, Trim, Clock Cal. Reset COR OVR LOW Vtg Voltage Short to Batt tFB3 Retry/Shutdown Bit PWMx address 3 X X X PWM Frequency REV ID 2 1 0 X X Shutdown Drivers on IMAX PWM Duty Cycle X CAL CAL Too Too HI LOW TRIM TRIM X X Parity Lock Error Out Legend COR = Command Out of Range SOR = Supply Out of Range NMF = Set When Faults Occur on V10 Mode MAXI and NOMI Inputs and V10 Mode Ignition Driver are OFF. 33810 30 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK (Pb-FREE) SUFFIX 32-PIN 98ARL10543D ISSUE B 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 31 PACKAGING PACKAGE DIMENSIONS . EK (Pb-FREE) SUFFIX 32-PIN 98ARL10543D ISSUE B 33810 32 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 3.0 10/2007 • Initial Release 4.0 2/2008 • Fixed several typos throughout document • Changed Static Electrical Characteristics, Table 3, Digital Interface, OUT_EN Leakage Current to VDD, maximum from 10 to 50µA. • Reworded not to Table 15. • Added Table 16 back (it was inadvertently deleted. • Added “Ignition &” to tile in Table 4. 33810 Analog Integrated Circuit Device Data Freescale Semiconductor 33 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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