FUJITSU SEMICONDUCTOR DATA SHEET DS04-27701-4E ASSP For Power Management Applications (Secondary battery) DC/DC Converter IC for Charging MB3832A ■ DESCRIPTION The MB3832A is a pulse width modulation (PWM) DC/DC converter IC, incorporating a current detector amplifier and error amplifiers (2 circuits) to control the output voltage and current independently. It is suitable for downconversion. With an on-chip reference voltage generator, the MB3832A is best suited for use in applications such as lithiumion battery (1-cell to 3-cell) chargers. ■ FEATURES • High precision reference voltage source: 2.5 V ± 0.5% (+25°C) : 2.5 V ± 1.0% (–10°C to +85°C) • High frequency operating capability: 500 kHz Max. • Wide operating supply voltage range: 3.6 V to 18 V • On-chip current detector amplifier with wide in-phase input voltage range: 0 V to VCC • On-chip standby function • On-chip triangular waveform oscillator capable of operating in external synchronization • On-chip, timer-latch short-circuit protection circuit • Internal totem-pole output stage supporting P-channel MOS FETs and PNP transistors ■ PACKAGE 20-pin plastic SSOP (FPT-20P-M03) MB3832A ■ PIN ASSIGNMENT (TOP VIEW) VREF : 1 20 : VE RT : 2 19 : OUT CT : 3 18 : VCC SYNC : 4 17 : CTL CSCP : 5 16 : DTC FB1 : 6 15 : FB2 −IN1 : 7 14 : −IN2 +IN1 : 8 13 : +IN2 −INC : 9 12 : COUT +INC : 10 11 : GND (FPT-20P-M03) 2 MB3832A ■ PIN DESCRIPTION Pin no. Pin name I/O Descriptions 1 VREF O Reference voltage output terminal 2 RT — Connection terminal for triangular wave frequency setting resistor 3 CT — Connection terminal for triangular wave frequency setting capacitor 4 SYNC I 5 CSCP — Connection terminal for time constant setting capacitor for timer-latch shortcircuit protection circuit 6 FBI O Error amplifier 1 output terminal 7 –IN1 I Error amplifier 1 inverted input terminal 8 +IN1 I Error amplifier 1 non-inverted input terminal 9 –INC I Current detector amplifier inverted input terminal 10 +INC I Current detector amplifier non-inverted input terminal 11 GND — Ground terminal 12 COUT O Current detector amplifier output terminal 13 +IN2 I Error amplifier 2 non-inverted input terminal 14 –IN2 I Error amplifier 2 inverted input terminal 15 FB2 O Error amplifier 2 output terminal 16 DTC I Connection terminal for dead time/soft start time setting resistor/capacitor 17 CTL I Power supply control input terminal “H” level: Active state “L” level: Standby state 18 VCC — Power supply terminal 19 OUT O Totem-pole output terminal 20 VE — Connector terminal for output sink current setting resistor External synchronous signal input terminal I: Input pin, O: Output pin 3 MB3832A ■ BLOCK DIAGRAM −INC +INC 9 10 COUT 12 FB2 15 −IN2 14 − +IN2 13 + FB1 6 −IN1 7 − +IN1 8 + Current Amp. − × 25 + Error Amp.2 + + + − Error Amp.1 Out 100 kΩ PWM Comp. 19 OUT 1V DTC 16 SCP Comp. 1 µA − − + − 2.1 V 1.1 V 18 VCC 20 VE DTC Comp. 1.9 V + 1.3 V bias bias VCC Ref CTL CSCP 5 S R Latch UVLO OSC 2.5 V 4 2 SYNC RT 4 3 CT 1 VREF 11 GND 17 CTL MB3832A ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Power supply voltage VCC Control input voltage Rating Unit Min Max — — 20 V VCTL — — 20 V Output current IO OUT terminal, DC — 50 mA Peak output current IO OUT terminal, Duty 5% — 600 mA Allowable dissipation PD Ta +25°C — 540* mW Storage temperature Tstg — –55 +125 °C *: When mounted on a 10 cm-square dual-sided epoxy base board WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Power supply voltage VCC Reference voltage output current IOR Input voltage VIN Value Unit Min Typ Max — 3.6 16 18 V — –1 — 0 mA +IN1, –IN1, +IN2, –IN2 terminal 0 — VCC – 0.9 V +INC, –INC terminal 0 — VCC V Control input voltage VCTL CTL terminal 0 — 18 V SYNC input voltage VSYNC SYNC terminal 0 — VCC V OUT terminal, DC — — 30 mA Output current IO Oscillator frequency fOSC — 10 200 500 kHz Timing capacitance CT — 100 390 2200 pF Timing resistance RT — 8.2 12 51 kΩ CSCP — — 0.1 1.0 µF Ta — –30 +25 +85 °C Short detection capacitance Operating temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB3832A ■ ELECTRICAL CHARACTERISTICS (VCC = 16 V, Ta = +25°C) Parameter Output voltage Reference voltage block Input stability (Ref) Load stability Short circuit output current Threshold voltage Under voltage lockout circuit block (UVLO) Hysteresis width Reset voltage Detection voltage Short Threshold voltage detection block Input standby voltage (SCP Comp, Input latch voltage S-R Latch) Input source current Oscillator frequency Triangular Frequency input stability wave oscillator block (OSC) SYNC input condition Input current Input offset voltage Symbol VREF Error amplifier (Error Amp.1, 2) Common mode rejection ratio 1 Condition Value Unit Min Typ Max Ta = +25°C 2.4875 2.50 2.5125 V Ta = –10°C to +85°C 2.475 2.50 2.525 V Ta = +25°C to +85°C 2.480 2.50 2.520 V Line 1 VCC = 3.6 V to 18 V — 1 10 mV Load 1 IREF = 0 mA to –1 mA — 3 10 mV IOS 1 VREF = 0 V –36 –16 –7 mA VTH 16 VCC terminal — 2.8 3.1 V VTL 16 VCC terminal 2.3 2.6 — V VH 16 VCC terminal 80 200 — mV VRST 19 VCC terminal 1.7 2.1 — V VTH 5 FB terminal 2.0 2.1 2.2 V VTH 5 CSCP terminal 0.65 0.70 0.75 V VSTB 5 CSCP terminal — 50 100 mV VI 5 CSCP terminal — 50 100 mV ICSCP 5 CSCP terminal –1.4 –1.0 –0.6 µA fOSC 19 CT = 330 pF, RT = 12 kΩ 190 200 210 kHz ∆f/f 19 VCC = 3.6 V to 18 V — 1 5 % VIH 19 Input “H” level 2.0 — — V VIL 19 Input “L” level 0 — 0.8 V ISYNC 4 VSYNC = 5 V — 50 100 µA VIO 8, 7, VFB = 1.6 V 13, 14 –3 — 3 mV IB 8, 7, VFB = 1.6 V 13, 14 –200 –50 — nA Input bias current Common mode input voltage range Pin no. VCM 8, 7, 13, 14 — 0 — VCC – 0.9 V CMRR 6, 15 — 60 100 — dB Voltage gain AV 6, 15 DC 60 100 — dB Frequency bandwidth BW 6, 15 AV = 0 dB — 750* — kHz Maximum output voltage width Output source current Output sink current OM+ 6, 15 — 2.5 2.7 — V OM– 6, 15 — — 0.8 1.0 V V V OM– 6, 15 VFB = 1.6 V — –120 –60 µA OM+ 6, 15 VFB = 1.6 V 0.6 2.0 — mA I I *: Standard design value (Continued) 6 MB3832A (Continued) (VCC = 16 V, Ta = +25°C) Parameter Symbol Pin no. VIO 10, 9 I+INC Unit Typ Max V+INC, V–INC = 2.4 V to 12.6 V –2 — 2 mV 10 V+INC = 12.7 V, V–INC = 12.6 V — 1 2 µA I–INC 9 V+INC = 0.1 V, V–INC = 0 V –2 –1 — µA VO1 12 V+INC = 12.7 V, V–INC = 12.6 V 2.25 2.5 2.75 V VO2 12 V+INC = 12.8 V, V–INC = 12.6 V 4.5 5.0 5.5 V VO3 12 V+INC = 0.1 V, V–INC = 0 V 2.25 2.5 2.75 V VO4 12 V+INC = 0.2 V, V–INC = 0 V 4.5 5.0 5.5 V VCM 10, 9 0 — VCC V CMRR 12 V+INC, V–INC = 2.4 V to 12.6 V 60 90 — dB Voltage gain AV 12 V–INC = 12.6 V 22.5 25 27.5 V/V Frequency bandwidth BW 12 AV = 0 dB — 500* — kHz Output resistance RO 12 f = 10 kHz — 20* — Ω Maximum output voltage width VOM+ 12 — VCC – 2.0 VCC – 1.6 — V VOM– 12 — — 50 200 mV OM– 12 VCOUT = 2.5 V — –7 –2 mA OM+ I 12 VCOUT = 2.5 V 60 170 — µA VT0 19 Duty cycle = 0 % 1.2 1.3 — V VT100 19 Duty cycle = 100 % — 1.9 2.0 V Input bias current IDTC 16 VDTC = 0.4 V –1.0 –0.2 — µA Latch mode input current IDTC 16 VDTC = 2.5 V 270 900 — µA Input latch voltage VDTC 16 IDTC = 100 µA — 0.15 0.3 V ON duty cycle Dtr 19 VDTC = VREF/1.56 43 48 53 % Input bias current Output voltage Common mode input voltage range Common mode rejection ratio Output source current Output sink current Threshold voltage PWM comparator block (PWM Comp.) Value Min Input offset voltage Current detector amplifier block (Current Amp.) Condition I — (Continued) 7 MB3832A (Continued) (VCC = 16 V, Ta = +25°C) Parameter Symbol Pin no. RON 19 IO Unit Typ Max IO = –50 mA — 5 8 Ω 19 RE = 33 Ω 18 30 42 mA VOH 19 IO = –300 mA 12.5 14 — V VOL 19 IO = 300 mA — 1.2 1.8 V ROUT1 19 VCTL = 0 V, VREF = 2.5 V, IO = –50 mA — 5 8 Ω ROUT2 19 VCTL = 0 V, VREF = 0 V, IO = –10 µA 70 100 130 kΩ VON 1 IC is active state 2.0 — 18 V VOFF 1 IC is standby state 0 — 0.8 V IIH 17 VCTL = 5 V — 100 200 µA IIL 17 VCTL = 0 V –1 0 — µA Standby current ICCS 18 VCTL = 0 V — — 10 µA Power supply current ICC 18 Output “H” — 4.6 7.0 mA Output sink current Output voltage Output block (OUT) Control-off output resistance CTL input condition Control block (CTL) Input current *: Standard design value 8 Value Min Output on resistance General Condition MB3832A ■ TYPICAL CHARACTERISTICS Reference voltage vs. VREF load current characteristics Reference voltage vs. power supply voltage characteristics 5 CTL = VCC Ta = +25 °C IREF = 0 mA 4 Reference voltage VREF (V) Reference voltage VREF (V) 5 3 2 1 0 VCC = 16 V CTL = 5 V Ta = +25 °C 4 3 2 1 0 0 5 10 15 Power supply voltage VCC (V) 20 0 10 20 30 40 VREF load current IREF (mA) Reference voltage vs. temperature characteristics Reference voltage ∆VREF (%) 2.0 VCC = 16 V CTL = 5 V 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −40 −20 0 20 40 60 80 100 Temperature Ta (°C) Reference voltage vs. control voltage characteristics 500 VCC = 16 V Ta = +25 °C IREF = 0 mA 4 Control current ICTL (µA) Reference voltage VREF (V) 5 Control current vs. control voltage characteristics 3 2 1 0 0 5 10 Control voltage VCTL (V) 15 20 VCC = 16 V Ta = +25 °C 400 300 200 100 0 0 5 10 15 20 Control voltage VCTL (V) (Continued) 9 MB3832A Triangular wave upper and down voltage (V) VCC = 16 V CTL = 5 V CT = 100 pF 100 k CT = 390 pF CT = 2200 pF 10 k 1k 1k 10 k 100 k Triangular wave oscillation frequency fOSC (Hz) 1M Triangular wave oscillation frequency vs. CT capacitance characteristics 1M VCC = 16 V CTL = 5 V RT = 12 kΩ 100 k 10 k 1k 10 p 100 p RT resistance (Ω) 1n CT capacitance (F) Triangular wave oscillation frequency regulation vs. power supply voltage characteristics Triangular wave oscillation frequency vs. temperature characteristics 3.0 CTL = VCC 2.0 1.0 RT = 12 kΩ, CT = 390 pF 0.0 −1.0 −2.0 −3.0 0 2 4 6 8 10 12 14 16 Power supply voltage VCC (V) 18 20 Triangular wave oscillation frequency fOSC (kHz) Triangular wave oscillation frequency regulation ∆fOSC (%) Triangular wave oscillation frequency fOSC (Hz) Triangular wave oscillation frequency vs. RT resistance characteristics 220 10 n VCC = 16 V CTL = 5 V 215 210 205 RT = 12 kΩ, CT = 390 pF 200 195 190 185 180 −40 −20 0 20 40 60 Temperature Ta (°C) 80 100 Triangular wave maximum/minimum voltages vs. triangular wave oscillation frequency characteristics 2.5 2.0 VCC = 16 V CTL = 5 V Upper 1.5 Lower 1.0 0.5 1k 10 k 100 k 1M 10 M Triangular wave oscillation frequency fOSC (Hz) (Continued) 10 MB3832A Error amp. gain, phase vs. frequency characteristics AV gain Av (dB) 30 20 10 0 0 −10 −45 −20 −90 −30 −135 −40 −180 100 1k 10 k 100 k 1M phase φ (deg.) 5V VCC = 16 V 180 CTL = 5 V Ta = +25 °C 135 90 φ 45 40 11 kΩ 240 kΩ 7 2.4 kΩ (14) 8 (13) − 1 µF IN 11 kΩ 2.5 V 6 (15) + Err Amp.1 (Err Amp.2) OUT 10 M Frequency f (Hz) Current detector amp. gain, phase vs. frequency characteristics 50 AV 135 20 90 10 45 0 0 −45 −10 −20 −90 φ −30 phase φ (deg.) 30 Gain Av (dB) Current Amp. 180 40 10 + ×2 IN 0.1 V 9 − + × 12.5 12 OUT − 12.6 V −135 −180 −40 −50 100 1k 10 k 100 k 1M 10 M Frequency f (Hz) Current detector amp. output voltage vs. input voltage characteristics VCC = 16 V V+INC = V−INC + 0.1 V Ta = +25 °C Output voltage VCOUT (V) 3.0 2.8 2.6 2.4 2.2 2.0 0 4 8 12 Inverting input voltage (V) 16 (Continued) 11 MB3832A (Continued) Allowable dissipation vs. ambient temperature characteristics Allowable dissipation PD (mW) 600 540 500 400 300 200 100 0 −40 −20 0 20 40 60 80 Ambient temperature Ta (°C) 12 100 120 MB3832A ■ FUNCTIONAL DESCRIPTION 1. Switching Regulator Functions (1) Reference voltage circuit (Ref) The reference voltage generator uses the voltage supplied from the VCC terminal (pin 18) to generate a temperature-compensated, stable voltage (about 2.50 V) as the reference supply voltage for the IC’s internal circuitry. The reference voltage can be output, up to 1 mA, to an external device through the VREF terminal (pin 1). (2) Triangular wave oscillator (OSC) The triangular wave oscillator generates a triangular waveform with a timing capacitor and a timing resistor respectively connected to the CT terminal (pin 3) and RT terminal (pin 2). The triangular wave is input to the PWM comparator in the IC while it can also be supplied to an external device through the CT terminal. In addition, the oscillator can be used for external synchronization, where it generates a triangular wave synchronous to the input signal from the SYNC terminal (pin 4). (3) Error amplifiers (Error Amp. 1, 2) The error amplifiers detect the output voltage from the switching regulator and outputs the PWM control signal. It supports a wide range of in-phase inputs from 0 V to “VCC – 0.9 V”. An arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the FB1 terminal (pin 6) [FB2 terminal (pin 15)] to the –IN1 terminal (pin 7) [–IN2 terminal (pin 14)] of the error amplifier, enabling stable phase compensation to the system. (4) Current detector amplifier (Current Amp.) The current detector amplifier provides 25 × amplification of the voltage drop between the two ends of the output sensor resistor (RS) in the switching regulator, that occurs due to the flow of the charging current. At the same time, the amplifier converts the voltage to the GND-reference voltage level and outputs it to the COUT terminal (pin 12). It can also control the charging current in combination with the error amplifier circuit. (5) Power control circuit (CTL) The power control circuit can control turning on and off the power supply through the CTL terminal (pin 17). (Supply current in standby mode: About 0 µA) Depending on the voltage level of the PWM Comp. input terminal, the OUT terminal (pin 19) may become “L” level during discharging of the VREF voltage after the CTL terminal is turned off with a capacitor connected to the VREF terminal. The power control circuit contains a function for fixing the OUT output terminal to the “H” level when CTL = “L” and VREF = “H”, preventing inadvertent “L” level output after turning the CTL terminal off. (6) PWM comparator circuit (PWM Comp.) The PWM comparator circuit is a voltage-pulse width converter for controlling the output duty of the error amplifiers (Error Amp. 1, 2) depending on their output voltage. The PWM comparator circuit turns on the external output transistor during the interval in which the triangular wave voltage level is lower than the voltage level at both of the error amplifier output terminals (FB1 terminal (pin 6), FB2 terminal (pin 15)) and the DTC terminal (pin 16). (7) Output circuit (Out) The output circuit uses a totem-pole configuration, capable of driving an external P-channel MOS FET and PNP transistor. It can also control the output sink current with a resistor connected between the VE terminal (pin 20) and the GND terminal (pin 11). 13 MB3832A 2. Protection Functions (1) Low input voltage malfunction preventive circuit (ULVO) The transient state or a momentary decrease in supply voltage, which occurs when the power supply is turned on, may cause errors in the control IC, resulting in breakdown or degradation of the system. The low input voltage malfunction preventive circuit detects the internal reference voltage level according to the supply voltage and turn off the external output transistor to make dead time 100%. The circuit restores voltage supply when the supply voltage reaches its threshold voltage. (2) Timer-latch short-circuit protection circuit (SCP Comp., SR Latch) The latch circuit detects the output voltage levels of the error amplifiers. When the output voltage levels of the two error amplifiers reach about 2.1 V at the same time, the timer circuit is actuated to start charging the external capacitor connected to the CSCP terminal (pin 5). If the error amplifier outputs are not restored to the normal voltage range before the capacitor voltage reaches about 0.7 V, the latch circuit is actuated to fix the output terminals (OUT) at the “H” level. To reset the actuated protection circuit, turn the power supply on back. 14 MB3832A ■ METHOD OF SETTING FOR EXTERNAL SYNCHRONOUS OSCILLATION For external synchronous oscillation, connect a timing capacitor (CT), a timing resistor (RT), and an external sync signal to the CT, RT, and SYNC terminals, respectively. In this case, select the CT and RT so that the oscillation frequency is 5% to 10% lower than the frequency of the external synchronous signal excluding the setting error of the oscillation frequency. The duty cycle (t1/ t) of the external sync signal must be set within a range from 10% to 90%. <Triangular wave oscillator (OSC) equivalent circuit> VREF Latch1 + S 2I* Q − 1.9 V R CT 3 − CT + 1.3 V “H” level: ON 3I* SYNC 4 1.4 V + Latch2 − S Q R <Free-run oscillation> <External synchronous oscillation> 1.9 V 1.9 V VCT VCT 1.3 V 1.3 V 5.0 V 5.0 V VSYNC VSYNC 0V 0V t t1 t t *: | = VRT/RT, VRT (pin voltage at pin 2) = 1.0 V (typical) 15 MB3832A ■ TREATMENT OF UNUSED CSCP PIN When the timer-latch short-circuit protection circuit is not used, connect the CSCP terminal (pin 5) to the GND at the shortest distance. Treatment of the CSCP terminal when not used 5 CSCP GND 11 ■ OSCILLATOR FREQUENCY SETTING The oscillator frequency can be set by connecting a timing capacitor (CT) to the CT terminal (pin 3) and a timing resistor (RT) to the RT terminal (pin 2). Oscillator frequency: fosc fosc (kHz) 16 936000 CT(pF) RT(kΩ) MB3832A ■ METHODS OF SETTING THE DEAD TIME When the device is set for step-up inverted output based on the flyback method, the output transistor is fixed to a full-ON state (ON duty = 100%) when the power supply is turned on. To prevent this problem, you may determine the voltage at the DTC terminal (pin 16) from the VREF voltage so you can set the output transistor’s dead time (maximum ON-duty period) as shown in Figure a below. When the voltage at the DTC terminal (pin 16) is higher than the triangular wave output voltage from the oscillator, the output transistor is turned off. The dead time calculation formula assuming that triangular wave amplitude .=. 0.6 V and triangular wave minimum voltage .=. 1.3 V is given below. R2 Vdt – 1.3 V Duty (ON) .=. × 100 [%], Vdt = × VREF 0.6 V R1 + R2 When the DTC terminal is not used, connect it directly to the VREF terminal. • Figure a Setting the dead time • Figure b Not setting the dead time 1 VREF 1 VREF 16 DTC 16 DTC R1 Vdt R2 17 MB3832A ■ METHODS OF SETTING THE SOFT START TIME To prevent surge currents when the IC is turned on, you can set a soft start using the DTC terminal (pin 16). When power is switched on, the current begins charging the capacitor (Cdt) connected the DTC terminal. The soft start process operates by comparing the soft start setting voltage, which is proportional to the DTC terminal voltage, with the triangular waveform, and varying the ON-duty of the OUT terminal (pin 19). The soft start time until the ON duty reaches 50 % is determined by the following equation: For figure c Soft start time (time until output ON duty = 50%) ts (s) = Cdt (F) × Rdt (Ω) × ln(1 − 1.6/2.5) =: 1.022 × Cdt (F) × Rdt (Ω) For figure d Soft start time (time until output ON duty = 50%) ts (s) = − Cdt (F) × R1 (Ω) × R2 (Ω) R1 (Ω) + R2 (Ω) • Figure c Setting a soft start × ln (1 − 1.6 (R1 (Ω) + R2 (Ω)) ) 2.5R2 (Ω) • Figure d Setting the dead time and a soft start 1 VREF 1 VREF Rdt R1 16 DTC Cdt 18 16 DTC Cdt R2 MB3832A ■ EQUIVALE CIRCUIT (CTL, SYNC terminal) • CTL terminal CTL 17 • SYNC terminal VCC SYNC 4 1.4 V 19 20 GND 5.1 kΩ 20.6 kΩ Vin FB1 DTC +IN1 0.22 µF +IN2 2.1 V − − + Error Amp.1 Error Amp.2 SCP Comp. + − + − S R Latch bias 1.1 V + − 10 kΩ c* 10 kΩ 10 kΩ b* a* UVLO DTC Comp. ×25 4 9 SYNC + − −INC PWM Comp. Current Amp. + + + − 12 COUT Charging current setting 5V Synchronous signal 0V 5 1 µA 16 8 7 6 13 CSCP 0.22 µF 470 kΩ 3.9 kΩ 0.033 µF −IN1 10 kΩ +IN2 14 FB2 15 0.1 µF −IN2 33 kΩ 5.1 kΩ 2 CT 1 11 CTL 0.1 µF VREF 2.5 V Ref VE 17 CTL 20 GND VCC OUT 19 18 100 kΩ VCC 1V 1.9 V 1.3 V bias 12kΩ 390pF RT 3 Out +INC OSC 10 2.2 µF 100 µF 5.1Ω GND (For load) 68 µF RS 0.033Ω VO (12.6 V) *: a: Set the charging current to 3 A. b: Set the charging current to 2 A. c: Set the charging current to 1 A. MTD20P03HDL: Made by Motorola Inc. MBRS130LT3: Made by Motorola Inc. 0.1 µF MBRS130 LT3 MTD20P03HDL 18 µH MB3832A ■ APPLICATION EXAMPLE (Step-down scheme) MB3832A ■ REFERENCE DATA Output voltage vs. output current characteristics Vin = 16 V Ta = +25°C 14 12 V+IN2 = VREF/3 (+IN2→c) V+IN2 = VREF∗2/3 (+IN2→b) V+IN2 = VREF (+IN2→a) Output voltage VO (V) 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Output current IO (A) Soft start operation waveforms Vin = 16 V CTL = 5 V RL = 5 Ω(2.52 A) 20 15 100 VO(V) 10 90 5 0 10 CTL(V) 5 10 0% 0 0 40 80 120 160 200 t(ms) 21 MB3832A ■ NOTES ON USE • Take account of common impedance when designing the earth line on a printed wiring board. • Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series. • Do not apply a negative voltage - Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. ■ ORDERING INFORMATION Part number MB3832APFV 22 Package 20-pin Plastic SSOP (FPT-20P-M03) Remarks MB3832A ■ PACKAGE DIMENSION Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 20-pin Plastic SSOP (FPT-20P-M03) *1 6.50±0.10(.256±.004) 0.17±0.03 (.007±.001) 20 11 *24.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part +0.20 1.25 –0.10 +.008 .049 –.004 LEAD No. 1 10 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.10(.004) C (Mounting height) 0.13(.005) M 0~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (Stand off) (.004±.004) 0.25(.010) 2003 FUJITSU LIMITED F20012S-c-4-6 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 23 MB3832A FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0308 FUJITSU LIMITED Printed in Japan