FUJITSU MB81F643242B-10FN-X

FUJITSU SEMICONDUCTOR
DATA SHEET
AE0.3E
MEMORY
CMOS
4 × 512 K × 32 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F643242B-10FN-X
CMOS 4-Bank × 524,288-Word × 32 Bit
Synchronous Dynamic Random Access Memory
■ DESCRIPTION
The Fujitsu MB81F643242B is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 32-bit format. The MB81F643242B features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F643242B SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F643242B is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
■ PRODUCT LINE & FEATURES
Parameter
CL - tRCD - [email protected] 66 MHz
Clock Frequency
Burst Mode Cycle Time
Access Time from Clock
Operating Current
Power Down Mode Current (ICC2P)
Self Refresh Current (ICC6)
•
•
•
•
•
CL = 3
CL = 3
CL = 3
Single +3.3 V Supply ±0.3 V tolerance
LVTTL compatible I/O interface
4 K refresh cycles every 16 ms
Four bank operation
Burst read/write operation and burst
read/single write operation capability
MB81F643242B-10FN-X
3 - 3 - 3 clk min.
100 MHz max.
10 ns min.
7 ns max.
105 mA max.
2 mA max.
2 mA max.
• Programmable burst type, burst length, and
CAS latency
• Auto-refresh (every 3.9 µs)
• CKE power down mode
• Output Enable and Input Data Mask
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ PACKAGE
86 pin plastic TSOP(II) Package
Marking side
(FPT-86P-M01)
(Normal Bend)
Package and Ordering Information
– 86-pin plastic (400 mil) TSOP-II, order as MB81F643242B-10FN-X
– 86-pin plastic (400 mil) TSOP-II with SCITT Function, order as MB81F643242B-10FN-X-S
2
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ PIN ASSIGNMENTS AND DESCRIPTIONS
86-Pin TSOP(II)
(TOP VIEW)
<Normal Bend: FPT-86P-M01>
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
N.C.
VCC
DQM0
WE
CAS
RAS
CS
N.C.
A12
A11
A10/AP
A0
A1
A2
DQM2
VCC
N.C.
DQ16
VSSQ
DQ17
DQ18
VCCQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VCCQ
DQ23
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
N.C.
VSS
DQM1
N.C.
N.C.
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
N.C.
DQ31
VCCQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VCCQ
DQ26
DQ25
VSSQ
DQ24
VSS
Pin Number
Symbol
Function
1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81
VCC, VCCQ
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36,
37, 39, 40, 42, 45, 47, 48, 50, 51, 53,
54, 56, 74, 76, 77, 79, 80, 82, 83, 85
DQ0 to DQ31
Data I/O
6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84,
86
VSS, VSSQ *
Ground
14, 21, 30, 57, 69, 70, 73
N.C.
No Connection
17
WE
Write Enable
18
CAS
Column Address Strobe
19
RAS
Row Address Strobe
20
CS
22, 23
A11 (BA1), A12 (BA0)
24
AP
24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66
A0 to A10
Address Input
67
CKE
Clock Enable
68
CLK
Clock Input
16, 28, 59, 71
DQM0 to DQM3
Supply Voltage
Chip Select
Bank Select (Bank Address)
Auto Precharge Enable
• Row: A0 to A10
• Column: A0 to A7
Input Mask/Output Enable
* : Those pins are connected internally in the chip.
3
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ BLOCK DIAGRAM
Fig. 1 – MB81F643242B BLOCK DIAGRAM
CLK
To each block
BANK-3
CLOCK
BUFFER
BANK-2
CKE
BANK-1
BANK-0
RAS
CS
RAS
CONTROL
SIGNAL
LATCH
CAS
COMMAND
DECODER
WE
CAS
WE
MODE
REGISTER
DRAM
CORE
(2,048 × 256 × 32)
A0 to A10,
A10/AP
ADDRESS
BUFFER/
REGISTER
ROW
ADDR.
A11 (BA1)
A12 (BA0)
DQM0
to
DQM3
COLUMN
ADDRESS
COUNTER
I/O DATA
BUFFER/
REGISTER
DQ0
to
DQ31
4
COL.
ADDR.
I/O
VCC
VCCQ
VSS/VSSQ
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ FUNCTIONAL TRUTH TABLE Note *1
COMMAND TRUTH TABLE
Note *2, *3, and *4
CKE
Function
Notes Symbol
CS RAS CAS WE
n-1
n
A12, A10 A9
A11
to
(BA) (AP) A8
A7
to
A0
Device Deselect
*5
DESL
H
X
H
X
X
X
X
X
X
X
No Operation
*5
NOP
H
X
L
H
H
H
X
X
X
X
BST
H
X
L
H
H
L
X
X
X
X
Burst Stop
Read
*6 READ
H
X
L
H
L
H
V
L
X
V
Read with Auto-precharge
*6 READA
H
X
L
H
L
H
V
H
X
V
Write
*6
H
X
L
H
L
L
V
L
X
V
Write with Auto-precharge
*6 WRITA
H
X
L
H
L
L
V
H
X
V
Bank Active
*7 ACTV
H
X
L
L
H
H
V
V
V
V
WRIT
Precharge Single Bank
PRE
H
X
L
L
H
L
V
L
X
X
Precharge All Banks
PALL
H
X
L
L
H
L
X
H
X
X
MRS
H
X
L
L
L
L
L
L
V
V
Mode Register Set
*8, *9
Notes: *1.
*2.
*3.
*4.
*5.
*6.
V = Valid, L = Logic Low, H = Logic High, X = either L or H.
All commands assumes no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of clock.
NOP and DESL commands have the same effect on the part.
READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7. ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
*8. Required after power up. Refer to POWER-UP INITIALIZATION in page 19.
*9. MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
5
MB81F643242B-10FN-X Advanced Info (AE0.3E)
DQM TRUTH TABLE
CKE
Function
Symbol
DQMi
n-1
n
Data Write/Output Enable
ENBi
H
X
L
Data Mask/Output Disable
MASKi
H
X
H
Notes: *1. i = 0, 1, 2, 3
*2. DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31,
CKE TRUTH TABLE
Current
State
CKE
Function
Notes Symbol
CS RAS CAS WE
n-1
n
A12, A10
A11
(BA) (AP)
A9
to
A0
Bank Active Clock Suspend Mode Entry
*1 CSUS
H
L
X
X
X
X
X
X
X
Any
Clock Suspend Continue
(Except Idle)
*1
L
L
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
Clock
Suspend
Clock Suspend Mode Exit
Idle
Auto-refresh Command
Idle
Self-refresh Entry
*2
REF
H
H
L
L
L
H
X
X
X
*2, *3
SELF
H
L
L
L
L
H
X
X
X
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
H
L
L
H
H
H
X
X
X
H
L
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
Self Refresh Self-refresh Exit
Idle
Power
Down
Power Down Entry
SELFX
*3
PD
Power Down Exit
Notes: *1. The CSUS command requires that at least one bank is active. Refer to STATE DIAGRAM.
NOP or DSEL commands should only be issued after CSUS and PRE(or PALL) commands asserted
at the same time.
*2. REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL
command). Refer to STATE DIAGRAM.
*3. SELF and PD commands should only be issued after the last read data have been appeared on DQ.
6
MB81F643242B-10FN-X Advanced Info (AE0.3E)
OPERATION COMMAND TABLE (Applicable to single bank) Note *1
Current
State
Idle
Bank Active
CS
RAS CAS WE
Addr
Command
Function
Notes
H
X
X
X
X
DESL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
NOP
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*2
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*2
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
NOP
L
L
L
H
X
REF/SELF
Auto-refresh or Self-refresh
*3, *6
L
L
L
L
MODE
MRS
Mode Register Set
(Idle after tRSC)
*3, *7
H
X
X
X
X
DESL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
NOP
L
H
L
H
BA, CA, AP
READ/READA
Begin Read; Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Begin Write; Determine AP
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
Precharge; Determine Precharge Type
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
Bank Active after tRCD
Illegal
*2
(Continued)
7
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Current
State
Read
Write
CS
RAS CAS WE
Addr
Command
Function
Notes
H
X
X
X
X
DESL
NOP (Continue Burst to End → Bank
Active)
L
H
H
H
X
NOP
NOP (Continue Burst to End → Bank
Active)
L
H
H
L
X
BST
Burst Stop → Bank Active
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, New Read;
Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, Start Write;
Determine AP
*4
L
L
H
H
BA, RA
ACTV
Illegal
*2
L
L
H
L
BA, AP
PRE/PALL
Terminate Burst, Precharge → Idle;
Determine Precharge Type
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Bank Active)
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Bank Active)
L
H
H
L
X
BST
Burst Stop → Bank Active
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, Start Read;
Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, New Write;
Determine AP
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
Terminate Burst, Precharge;
Determine Precharge Type
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
Illegal
*4
*2
(Continued)
8
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Current
State
Read with
Autoprecharge
Write with
Autoprecharge
CS
RAS CAS WE
Addr
Command
Function
Notes
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*2
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*2
L
L
H
H
BA, RA
ACTV
Illegal
*2
L
L
H
L
BA, AP
PRE/PALL
Illegal
*2
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*2
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*2
L
L
H
H
BA, RA
ACTV
Illegal
*2
L
L
H
L
BA, AP
PRE/PALL
Illegal
*2
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
(Continued)
9
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Current
State
Precharging
Bank
Activating
CS
RAS CAS WE
Addr
Command
Function
Notes
H
X
X
X
X
DESL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
X
BST
NOP (Idle after tRP)
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*2
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*2
L
L
H
H
BA, RA
ACTV
Illegal
*2
L
L
H
L
BA, AP
PRE/PALL
NOP (PALL may affect other
bank)
*5
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Bank Active after tRCD)
L
H
H
H
X
NOP
NOP (Bank Active after tRCD)
L
H
H
L
X
BST
NOP (Bank Active after tRCD)
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*2
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*2
L
L
H
H
BA, RA
ACTV
Illegal
*2
L
L
H
L
BA, AP
PRE/PALL
Illegal
*2
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
(Continued)
10
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Current
State
Refreshing
Mode
Register
Setting
CS
RAS
CAS
WE
Addr
Command
H
X
X
X
X
DESL
NOP (Idle after tRC)
L
H
H
X
X
NOP/BST
NOP (Idle after tRC)
L
H
L
X
X
L
L
H
X
X
ACTV/
PRE/PALL
Illegal
L
L
L
X
X
REF/SELF/
MRS
Illegal
H
X
X
X
X
DESL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
X
BST
Illegal
L
H
L
X
X
L
L
X
X
X
Function
Notes
READ/READA/
Illegal
WRIT/WRITA
READ/READA/
Illegal
WRIT/WRITA
ACTV/PRE/
PALL/REF/
SELF/MRS
Illegal
ABBREVIATIONS:
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
Notes: *1. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shout down.
*2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the
state of that bank.
*3. Illegal if any bank is not idle.
*4. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to TIMING DIAGRAM - 11 & - 12.
*5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
*6. SELF command should only be issued after the last read data have been appeared on DQ.
*7. MRS command should only be issued on condition that all DQ are in Hi-Z.
11
MB81F643242B-10FN-X Advanced Info (AE0.3E)
COMMAND TRUTH TABLE FOR CKE Note *1
Current
State
Selfrefresh
Selfrefresh
Recovery
CKE
n-1
CKE
n
CS
H
X
X
X
L
H
H
L
H
L
RAS CAS
WE
Addr
Function
Notes
X
X
X
Invalid
X
X
X
X
Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
L
H
H
H
X
Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
H
L
H
H
L
X
Illegal
L
H
L
H
L
X
X
Illegal
L
H
L
L
X
X
X
Illegal
L
L
X
X
X
X
X
NOP (Maintain Self-refresh)
L
X
X
X
X
X
X
Invalid
H
H
H
X
X
X
X
Idle after tRC
H
H
L
H
H
H
X
Idle after tRC
H
H
L
H
H
L
X
Illegal
H
H
L
H
L
X
X
Illegal
H
H
L
L
X
X
X
Illegal
H
H
X
X
X
X
X
Illegal
H
L
X
X
X
X
X
Illegal
*2
(Continued)
12
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Current
State
Power
Down
All
Banks
Idle
CKE
n-1
CKE
n
CS
H
X
X
X
L
H
H
L
H
L
RAS CAS
WE
Addr
Function
Notes
X
X
X
X
X
X
X
L
H
H
H
X
L
X
X
X
X
X
NOP (Maintain Power Down Mode)
L
H
L
L
X
X
X
Illegal
L
H
L
H
L
X
X
Illegal
H
H
H
X
X
X
MODE
Refer to the Operation Command
Table.
H
H
L
H
X
X
MODE
Refer to the Operation Command
Table.
H
H
L
L
H
X
MODE
Refer to the Operation Command
Table.
H
H
L
L
L
H
X
H
H
L
L
L
L
MODE
H
L
H
X
X
X
X
Power Down
H
L
L
H
H
H
X
Power Down
H
L
L
H
H
L
X
Illegal
H
L
L
H
L
X
X
Illegal
H
L
L
L
H
X
X
Illegal
H
L
L
L
L
H
X
Self-refresh
H
L
L
L
L
L
X
Illegal
L
X
X
X
X
X
X
Invalid
Invalid
Exit Power Down Mode → Idle
Auto-refresh
Refer to the Operation Command
Table.
*3
(Continued)
13
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Current
State
Bank Active
Bank
Activating
Read/Write
Clock
Suspend
Any State
Other Than
Listed
Above
CKE
n-1
CKE
n
CS
H
H
X
X
H
L
X
L
X
H
RAS CAS
WE
Addr
Function
Notes
X
X
X
Refer to the Operation Command
Table.
X
X
X
X
Begin Clock Suspend next cycle
X
X
X
X
X
Invalid
X
X
X
X
X
X
Invalid
L
H
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to the Operation Command
Table.
H
L
X
X
X
X
X
Illegal
Notes: *1. All entries in COMMAND TRUTH TABLE FOR CKE are specified at CKE(n) state and CKE input
from CKE(n–1) to CKE(n) state must satisfy corresponding set up and hold time for CKE.
*2. CKE should be held High for tRC period.
*3. SELF command should only be issued after the last data have been appeared on DQ.
14
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode,
and mode register.
The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization,
where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each
operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined
by commands and all operations are referenced to a positive clock edge. Fig. 2 shows the basic timing diagram
differences between SDRAMs and DRAMs.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column address
counter.
The mode register is to justify the SDRAM operation and function into desired system conditions. MODE
REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and
internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the
CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the
next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode
(standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are
negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS can be
tied to ground level.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address
strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge
of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5.
ADDRESS INPUT (A0 to A10)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of twenty
one address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order
to reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially
latched and the remainder of eight Column addresses are then latched by a Column address strobe command of
either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (A12, A11)
This SDRAM has four banks and each bank is organized as 512 K words by 32-bit.
Bank selection by A12, A11 occurs at Bank Active command (ACTV) followed by read (READ or READA), write
(WRIT or WRITA), and precharge command (PRE).
15
MB81F643242B-10FN-X Advanced Info (AE0.3E)
DATA INPUT AND OUTPUT (DQ0 to DQ31)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input:
tRAC ; from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.)
tAC ; from the clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked at
the second clock later while internal burst counter will increment by one or will go to the next stage depending on
burst type. DQM0, DQM1, DQM2, DQM3, controls DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, DQ24 to DQ31, respectively.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address
and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK,
respectively. The internal column address counter operation is determined by a mode register which defines burst
type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst
mode to the next stage while the remaining burst count is more than 1, the following combinations will be required:
Current Stage
Next Stage
Burst Read
Burst Read
Burst Read
Burst Write
Method (Assert the following command)
Read Command
1st Step
Mask Command (Normally 3 clock cycles)
2nd Step
Write Command after lOWD
Burst Write
Burst Write
Write Command
Burst Write
Burst Read
Read Command
Burst Read
Precharge
Precharge Command
Burst Write
Precharge
Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode
is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to
the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant
address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
(Continued)
16
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write
operation.
The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the
full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be
determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary
address and then wraps round to least significant address (= 0).
Burst
Length
2
4
8
Starting Column
Address
A2 A1 A0
Sequential Mode
Interleave
X X 0
0–1
0–1
X X 1
1–0
1–0
X 0 0
0–1–2–3
0–1–2– 3
X 0 1
1–2–3–0
1–0–3–2
X 1 0
2–3–0–1
2–3–0–1
X 1 1
3–0–1–2
3–2–1–0
0 0 0
0–1–2–3–4–5–6–7
0–1–2–3–4–5–6–7
0 0 1
1–2–3–4–5–6–7–0
1–0–3–2–5–4–7–6
0 1 0
2–3–4–5–6–7–0–1
2–3–0–1–6–7–4–5
0 1 1
3–4–5–6–7–0–1–2
3–2–1–0–7–6–5–4
1 0 0
4–5–6–7–0–1–2–3
4–5–6–7–0–1–2–3
1 0 1
5–6–7–0–1–2–3–4
5–4–7–6–1–0–3–2
1 1 0
6–7–0–1–2–3–4–5
6–7–4–5–2–3–0–1
1 1 1
7–0–1–2–3–4–5–6
7–6–5–4–3–2–1–0
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column
burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps
round to first column address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT),
precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full
column burst operation except write command at BURST READ & SINGLE WRITE mode.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst
mode, its operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
For the detail rule, please refer to TIMING DIAGRAM – 8.
When write mode is interrupted by BST command, the data to be applied at the same time with BST command will
be ignored.
BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
17
MB81F643242B-10FN-X Advanced Info (AE0.3E)
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge
rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE).
With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP).
The precharged bank is selected by combination of AP and A11, A12 when Precharge command is asserted. If AP
= High, all banks are precharged regardless of A11, A12 (PALL). If AP = Low, a bank to be selected by A11, A12 is
precharged (PRE).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to FUNCTIONAL
TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command.
The Auto-refresh command should also be asserted every 3.9 µs or a total 4096 refresh commands within a 16 ms
period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the
refresh function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once
SDRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level
state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ
Notes:
When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP)
or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one
tRC period after tCKSP. Refer to Timing Diagram-16 for the detail.
It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period.
Notes:
When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted after the self-refresh exit.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE in page 33.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address
line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another
MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM. Refer to POWER-UP INITIALIZATION below.
18
MB81F643242B-10FN-X Advanced Info (AE0.3E)
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On
Sequence to execute read or write operation.
1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4. Assert minimum of 2 Auto-refresh command (REF).
5. Program the mode register by Mode Register Set command (MRS).
In addition, it is recommended DQM and CKE to track VCC to insure that output is High-Z state. The Mode Register
Set command (MRS) can be set before 2 Auto-refresh command (REF).
19
MB81F643242B-10FN-X Advanced Info (AE0.3E)
Fig. 2 – BASIC TIMING FOR CONVENTIONAL DRAM VS SYNCHRONOUS DRAM
<SDRAM>
Active
Read/Write
Precharge
CLK
CKE
H
H
tSI
H
tHI
CS
RAS
CAS
H : Read
WE
L : Write
Address
BA (A11, A12)
RA
BA (A11, A12)
CA
CAS Latency = 2
BA (A11, A12)
AP (A10)
DQ
Burst Length = 4
<Conventional DRAM>
Row Address Select
RAS
CAS
DQ
20
Column Address Select
Precharge
MB81F643242B-10FN-X Advanced Info (AE0.3E)
Fig. 3 – STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
MRS
SELF
MODE
REGISTER
SET
SELF
REFRESH
SELFX
IDLE
REF
CKE\(PD)
CKE
AUTO
REFRESH
ACTV
POWER
DOWN
CKE\(CSUS)
BANK
ACTIVE
SUSPEND
BANK
ACTIVE
CKE
BST
BST
READ
WRIT
READ
WRIT
WRITA
CKE\(CSUS)
READ
WRITE
CKE
READA
CKE\(CSUS) WRITE WITH
AUTO
CKE\
PRECHARGE
PRE or
PALL
POWER
ON
POWER
APPLIED
CKE\(CSUS)
READ
CKE
WRIT
WRITA
WRITE
SUSPEND
READA
PRE or PALL
WRITA
PRE or
PALL
WRITE
SUSPEND
READ
SUSPEND
READA
READ WITH
AUTO
PRECHARGE
CKE\(CSUS)
CKE
READ
SUSPEND
PRE or
PALL
PRECHARGE
DEFINITION OF ALLOWS
Manual
Input
Automatic
Sequence
Note: CKE\ means CKE goes Low-level from High-level.
21
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ 1 BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION
*5
1
READ
1
1
BST
tRCD
SELF
WRITA
WRIT
tRCD
REF
tRCD
PALL
tRCD
ACTV
READA
tRSC
READ
tRSC
*4
PRE
MRS
ACTV
First
command
*4
MRS
Second
command
(same
bank)
tRSC
tRSC
tRSC
tRSC
tRSC
tRAS
tRAS
*5
1
*4
1
*1,*2
READA
BL
+
tRP
*4
1
*4
BL
+
tRP
BL
+
tRP
tWR
1
1
tDPL
*2
WRITA
BL-1
+
tDAL
*4
tRP
BL-1
+
tDAL
1
*4
BL-1
+
tDAL
*2
BL-1
+
tDAL
*4
tRP
1
*2,*7
BL
+
tRP
*4
*2,*3
PRE
*2
BL
+
tRP
tDPL
*4
BL-1
+
tDAL
1
BL
+
tRP
*4
tWR
WRIT
1
1
*2
tRP
*2
BL-1
+
tDAL
*2,*6
tRP
*3
*6
PALL
tRP
tRP
1
1
tRP
tRP
1
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
tRC
tRC
tRC
tRC
Notes: *1. If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
*2.
*3.
*4.
*5.
*6.
*7.
Assume all banks are in Idle state.
Assume output is in High-Z state.
Assume tRAS(min.) is satisfied.
Assume no I/O conflict.
Assume after the last data have been appeared on DQ.
If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
Illegal Command
22
1
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ MULTI BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
*2
ACTV
tRRD
READ
1
*7
*7
*7
*1,*2
BL+
tRP
READA
1
1
1
1
1
1
1
*6,*10
*6,*10
1
1
*10
*2,*4
1
*7
1
*2,*4
*9
*6
1
*6
1
PALL
REF
SELF
BST
*5,*6
WRITA
*5
WRIT
tRSC
READA
READ
tRSC
*5,*6
PRE
MRS
ACTV
First
command
*5
MRS
Second
command
(other
bank)
tRSC
tRSC
tRSC
tRSC
tRSC
*6,*7
1
*10
1
*9
*2
BL-1
+
tDAL
WRITA
*6
*2,*3
tRP
PRE
*5
1
*6
1
*2,*4
1
1
*6
1
*7
1
1
*6
*6
1
*6
1
*7
1
1
1
*7
*6
1
1
*2
BL+
tRP
*2,*9
BL+
tRP
*6
tDPL
*6
1
*7
1
BL+
tRP
1
*6
1
1
*6
*2,*4
1
tRAS
1
*2,*4
WRIT
*7
1
*6
BL-1
+
tDAL
*6,*7
*2
BL-1
+
tDAL
*7
*2
*2
BL-1
+
tDAL
*2,*8
1
1
tRP
tRP
*3
1
*8
PALL
tRP
tRP
1
1
tRP
tRP
1
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
tRC
tRC
Notes:
*1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
Assume bank of the object is in Idle sate.
Assume output is in High-Z sate.
tRRD(min.) of other bank (second command will be asserted) is satisfied.
Assume other bank is in active, read or write state.
Assume tRAS(min.) is satisfied.
Assume other banks are not in READA/WRITA state.
Assume after the last data have been appeared on DQ.
If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
Assume no I/O conflict.
Illegal Command
23
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ MODE REGISTER TABLE
MODE REGISTER SET
A12
A11
A10
A9
A8
A7
0
0
0
A9
0
1
Opcode
0
A6
0
A6
A5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
A5
A4
A3
A2
A1
A0
ADDRESS
*3
*3
CL
A4
CAS Latency
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Op-code
Burst Read & Burst Write
Burst Read & Single Write *1
BT
MODE
REGISTER
BL
Burst Length
A2
A1
A0
BT = 0
0
0
0
0
1
1
1
1
A3
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
Reserved
Reserved
Reserved
Full Column
Burst Type
Sequential (Wrap round, Binary-up)
Interleave (Wrap round, Binary-up)
Notes: *1. When A9 = 1, burst length at Write is always one regardless of BL value.
*2. BL = 1 and Full Column are not applicable to the interleave mode.
*3. A7 = 1 and A8 = 1 is reserved for vender test.
24
BT = 1 *2
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Symbol
Value
Unit
Voltage of VCC Supply Relative to VSS
VCC, VCCQ
–0.5 to +4.6
V
Voltage at Any Pin Relative to VSS
VIN, VOUT
–0.5 to +4.6
V
Short Circuit Output Current
IOUT
±50
mA
Power Dissipation
PD
1.3
W
TSTG
–55 to +125
°C
Storage Temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
VCC, VCCQ
3.0
3.3
3.6
V
VSS, VSSQ
0
0
0
V
Supply Voltage
Input High Voltage
*1
VIH
2.0
—
VCC + 0.5
V
Input Low Voltage
*2
VIL
–0.5
—
0.8
V
TA
–40
—
85
°C
Ambient Temperature
Notes:
VIH
4.6V
50% of pulse amplitude
VIH
VIHmin
Pulse width ≤ 5 ns
VILmax
VIL
50% of pulse amplitude
Pulse width ≤ 5 ns
VIL
-1.5V
*1. Overshoot limit: VIH (max)
= 4.6V for pulse width <= 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
*2. Undershoot limit: VIL (min)
= VCC -1.5V for pulse width <= 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
■ CAPACITANCE
Parameter
(TA = 25°C, f = 1 MHz)
Symbol
Min.
Typ.
Max.
Unit
Input Capacitance, Except for CLK
CIN1
2.5
—
5.0
pF
Input Capacitance for CLK
CIN2
2.5
—
4.0
pF
I/O Capacitance
CI/O
4.0
—
6.5
pF
25
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, *2, and *3
Parameter
Output High Voltage
Output Low Voltage
Symbol
Condition
VOH(DC)
VOL(DC)
IOH = –2 mA
IOL = 2 mA
0 V ≤ VIN ≤ VCC;
All other pins not under
test = 0 V
0 V ≤ VIN ≤ VCC;
Data out disabled
Burst: Length = 1
tRC = min, tCK = min
One bank active
Output pin open
Addresses changed up to
1-time during tRC (min)
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL
All banks idle
tCK = min
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL
All banks idle
CLK = VIH or VIL
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
All banks idle, tCK = 15 ns
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
All banks idle
CLK = VIH or VIL
Input signal are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
Input Leakage Current (Any Input)
ILI
Output Leakage Current
ILO
Operating Current
(Average Power Supply Current)
ICC1
ICC2P
ICC2PS
Precharge Standby Current
(Power Supply Current)
ICC2N
ICC2NS
Value
Min.
Max.
2.4
—
—
0.4
Unit
V
V
–5
5
µA
–5
5
µA
—
135
mA
—
2
mA
—
1
mA
—
12
mA
—
2
mA
(Continued)
26
MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Parameter
Symbol
ICC3P
ICC3PS
Active Standby Current (Power Supply Current)
ICC3N
ICC3NS
Burst mode Current
(Average Power Supply Current)
ICC4
Refresh Current #1
(Average Power Supply Current)
ICC5
Refresh Current #2
(Average Power Supply Current)
ICC6
Condition
CKE = VIL
Any bank active
tCK = min
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL
Any bank active
CLK = VIH or VIL
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
Any bank active
tCK = 15 ns
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
Any bank idle
CLK = VIH or VIL
Input signals are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
tCK = min
Burst Length = 4
Output pin open
All banks active
Gapless data
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Auto-refresh;
tCK = min
tRC = min
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Self-refresh;
tCK = min
CKE ≤ 0.2 V
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Value
Min.
Max.
Unit
—
2
mA
—
1
mA
—
25
mA
—
2
mA
—
200
mA
—
180
mA
—
2
mA
Notes: *1. All voltages are referred to VSS.
*2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*3. ICC depends on the output termination or load condition, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open and no termination register.
27
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, *2, and *3
MB81F643242B-10FN-X
Parameter
Notes
Clock Period
Symbol
CL = 3
Max.
tCK3
10
—
ns
Clock High Time
*5
tCH
3
—
ns
Clock Low Time
*5
tCL
3
—
ns
Input Setup Time
*5
tSI
3
—
ns
Input Hold Time
*5
tHI
1
—
ns
tAC3
—
7
ns
tLZ
0
—
ns
tHZ3
2.5
7
ns
2.5
—
ns
tREFI
—
3.9
µs
tREF
—
16
ms
tT
0.5
10
ns
tCKSP
3
—
ns
Access Time from Clock
(tCK = min)
*5,*6,*7
CL = 3
Output in Low-Z
*5
Output in High-Z
*5,*8
CL = 3
Output Hold Time
*5,*8
CL = 3
Time between Auto-Refresh command interval
*4
Time between Refresh
Transition Time
CKE Setup Time for Power Down Exit Time
28
Unit
Min.
*5
MB81F643242B-10FN-X Advanced Info (AE0.3E)
BASE VALUES FOR CLOCK COUNT/LATENCY
MB81F643242B-10FN-X
Parameter
Notes
Symbol
Unit
Min.
Max.
tRC
100
—
ns
RAS Precharge Time
tRP
30
—
ns
RAS Active Time
tRAS
60
110000
ns
RAS to CAS Delay Time
tRCD
30
—
ns
Write Recovery Time
tWR
15
—
ns
RAS to RAS Bank Active Delay Time
tRRD
30
—
ns
Data-in to Precharge Lead Time
tDPL
15
—
ns
tDAL3
2 cyc + tRP
—
ns
tRSC
30
—
ns
RAS Cycle Time
*9
Data-in to Active/Refresh Command
Period
CL=3
Mode Resister Set Cycle Time
CLOCK COUNT FORMULA
Clock ≥
Note *10
Base Value
Clock Period
(Round off a whole number)
29
MB81F643242B-10FN-X Advanced Info (AE0.3E)
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Parameter
Notes
Symbol
MB81F643242B-10FN-X
Unit
CKE to Clock Disable
lCKE
1
cycle
DQM to Output in High-Z
lDQZ
2
cycle
DQM to Input Data Delay
lDQD
0
cycle
Last Output to Write Command Delay
lOWD
2
cycle
Write Command to Input Data Delay
lDWD
0
cycle
Precharge to Outputin High-Z Delay
CL = 3
lROH3
3
cycle
Burst Stop Command to Output in High-Z Delay
CL = 3
lBSH3
3
cycle
CAS to CAS Delay (min)
lCCD
1
cycle
CAS Bank Delay (min)
lCBD
1
cycle
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*2. AC characteristics assume tT = 1 ns and 50 Ω of terminated load.
*3. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured
between VIH (min) and VIL (max).
*4. This value is for reference only.
*5. If input signal transition time (tT) is longer than 1 ns; [(tT/2) – 0.5] ns should be added to tAC (max),
tHZ (max), and tCKSP (min) spec values, [(tT/2) – 0.5] ns should be subtracted from tLZ (min), tHZ (min),
and tOH (min) spec values, and (tT – 1.0) ns should be added to tCH (min), tCL (min), tSI (min), and
tHI (min) spec values.
*6. tAC also specifies the access time at burst mode.
*7. tAC and tOH are the spec value under AC test load circuit shown in Fig. 4.
*8. Specified where output buffer is no longer driven.
*9. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP).
*10. All base values are measured from the clock edge at the command input to the clock edge for the
next command input. All clock counts are calculated by a simple formula: clock count equals
base value divided by clock period (round off to a whole number).
30
MB81F643242B-10FN-X Advanced Info (AE0.3E)
Fig. 4 – EXAMPLE OF AC TEST LOAD CIRCUIT
R1 = 50 Ω
Output
1.4 V
CL = 30 pF
LVTTL
Note: By adding appropriate correlation factors to the test conditions, tAC and tOH measured when the Output is coupled to
the Output Load Circuit are within specifications.
31
MB81F643242B-10FN-X Advanced Info (AE0.3E)
Fig. 5 – TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME
tCK
tCH
tCL
2.4 V
1.4 V
CLK
0.4 V
tSI
tHI
2.4 V
Input
(Control,
Addr. & Data)
1.4 V
0.4 V
tAC
tHZ
tOH
tLZ
2.4 V
Output
1.4 V
0.4 V
Note: Reference level of input signal is 1.4 V for LVTTL.
Access time is measured at 1.4 V for LVTTL.
Fig. 6 – TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT
CLK
Don’t Care
tCKSP (min)
1 clock (min)
CKE
Command
32
Don’t Care
NOP
NOP
ACTV
MB81F643242B-10FN-X Advanced Info (AE0.3E)
Fig. 7 – TIMING DIAGRAM, PULSE WIDTH
CLK
Input
(Control)
tRC, tRP, tRAS, tRCD, tWR, tREF,
tDPL, tDAL, tRSC, tRRD, tCKSP
COMMAND
COMMAND
Note: These parameters are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the
latency value from the rising edge of CKE.
Measurement reference voltage is 1.4 V.
Fig. 8 – TIMING DIAGRAM, ACCESS TIME
CLK
Command
READ
tAC
tAC
tAC
(CAS Latency – 1) × tCK
DQ
(Output)
Q(Valid)
Q(Valid)
Q(Valid)
33
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ TIMING DIAGRAMS
TIMING DIAGRAM – 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE
*1
ICKE (1 clock)*1
ICKE (1 clock)
CLK
(Internal)
*2
DQ
(Read)
Q1
DQ
(Write)
D1
Q2
*2
*2
(NO CHANGE)
NOT *3
WRITTEN
D2
*2
Q3
(NO CHANGE)
NOT *3
WRITTEN
D3
Q4
D4
Notes: *1. The latency of CKE (lCKE) is one clock.
*2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output
data remain the same data.
*3. During the write mode, data at the next clock of CSUS command is ignored.
TIMING DIAGRAM – 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
CLK
tCKSP
1 clock
(min)
(min)
CKE
Command
NOP
*1
PD(NOP)
*2
DON’T CARE
NOP
*3
NOP
*3
ACTV
tREF (max)
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2. Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ.
*3. It is recommended to apply NOP command in conjunction with CKE.
*4. The ACTV command can be latched after tCKSP (min) + 1 clock (min).
34
*4
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
ICCD
(1 clock)
tRCD (min)
ICCD
ICCD
ICCD
CAS
Address
COLUMN
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Note: CAS to CAS delay can be one or more clock period.
TIMING DIAGRAM – 4 : DIFFERENT BANK ADDRESS INPUT DELAY
CLK
tRRD (min)
RAS
ICBD
(1 clock)
tRCD (min) or more
ICBD
CAS
tRCD (min)
Address
A11, A12(BA)
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Bank 0
Bank 3
Bank 0
Bank 3
Bank 0
Bank 3
Note: CAS Bank delay can be one or more clock period.
35
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 5 : DQM0 - DQM3 - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM0-DQM3
(@ Read)
IDQZ (2 clocks)
DQ
(@ Read)
Q1
Q2
Hi-Z
Q4
End of burst
DQM0-DQM3
(@ Write)
IDQD (same clock)
DQ
(@ Write)
D1
MASKED
D3
D4
End of burst
TIMING DIAGRAM – 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
tRAS (min)
Command
ACTV
Note: PRECHARGE means ’ PRE’ or ’PALL’.
36
PRECHARGE
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
PRECHARGE
IROH (2 clocks)
DQ
Command
Q1
Hi-Z
PRECHARGE
IROH (2 clocks)
DQ
Q1
Command
Q2
Hi-Z
PRECHARGE
IROH (2 clocks)
DQ
Q1
Q2
Command
Hi-Z
Q3
PRECHARGE
No effect (end of burst)
DQ
Q1
Q2
Q3
Q4
Note: In case of CL = 2, the lROH is 2 clocks.
In case of CL = 3, the lROH is 3 clocks.
PRECHARGE means ’ PRE’ or ’PALL’.
37
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column)
CLK
Command
(CL = 2)
BST
lBSH (2 clocks)
DQ
Qn–2
Qn–1
Command
(CL = 3)
Qn
Qn+1
Hi-Z
BST
lBSH (3 clocks)
Hi-Z
DQ
Qn-2
Qn-1
Qn
Qn+1
Qn+2
TIMING DIAGRAM – 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ CL = 2)
CLK
Command
DQ
38
BST
LAST
DATA-IN
Masked
by BST
COMMAND
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
CLK
Command
ACTV
PRECHARGE
tDPL (min)
DQ
DATA-
LAST
DATA-IN
tRP (min)
MASKED
by Precharge
Note: The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
PRECHARGE means ’ PRE’ or ’PALL’.
TIMING DIAGRAM – 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
CLK
IOWD (2 clocks)
Command
DQM
(DQM0-DQM3)
DQ
WRIT
READ
*1
*2
*3
IDQZ (2 clocks)
IDWD (same clock)
D1
Q1
D2
Masked
Notes: *1. First DQM makes high-impedance state High-Z between last output and first input data.
*2. Second DQM makes internal output data mask to avoid bus contention.
*3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the
second clock of burst write, this third DQM is required to avoid internal bus contention.
39
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
CLK
tWR (min)
Command
WRIT
READ
DQM
DQM0-DQM3
(CL-1) × tCK
DQ
D1
D2
tAC (max)
D3
Q1
Masked
by READ
Q2
Note: Read command should be issued after tWR of final data input is satisfied.
TIMING DIAGRAM – 13 : READ WITH AUTO-PRECHARGE
(EXAPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
tRAS (min)
Command
ACTV
tRP (min)
READA
NOP or DESL
2 clocks *1
(same value as BL)
ACTV
BL+tRP (min) *2
DQM
(DQM0-DQM3)
DQ
Q1
Q2
Notes: *1. Precharge at Read with Auto-precharge command (READA) is started from number of clocks that is the same as
Burst Length (BL) after the READA command is asserted.
*2. Next ACTV command should be issued after BL+tRP (min) from READA command.
40
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 14 : WRITE WITH AUTO-PRECHARGE *1, *2, and *3
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
tRAS (min)
CLK
CL – 1 *4
tDAL (min)
BL+tRP (min) *5
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM
(DQM0-DQM3)
DQ
D1
D2
Notes: *1. Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
*2. Once auto precharge command is asserted, no new command within the same bank can be issued.
*3. Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single Write.
*4. Precharge at write with Auto-precharge is started after CL – 1 from the end of burst.
*5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command.
TIMING DIAGRAM – 15 : AUTO-REFRESH TIMING
CLK
Command
REF *1
NOP *3
NOP
*3
NOP
*3
REF
NOP
tRC (min)
DON’T CARE
Command *4
tRC (min)
*2
A11, A12(BA)
*3
*2
DON’T CARE
BA
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF).
*2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter.
*3. Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode.
*4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the
last REF command.
41
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 16 : SELF-REFRESH ENTRY AND EXIT TIMING
CLK
tCKSP (min)
tSI (min)
CKE
tRC (min) *4
Command
NOP *1
SELF
DON’T CARE
NOP
*2
SELFX
NOP
*3
Command
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF).
*2. The Self-refresh Exit command (SELFX) is latched after tCKSP (min). It is recommended to apply NOP command in
conjunction with CKE.
*3. Either NOP or DESL command can be used during tRC period.
*4. CKE should be held high within one tRC period after tCKSP.
TIMING DIAGRAM – 17 : MODE REGISTER SET TIMING
CLK
tRSC (min)
Command
Address
MRS
MODE
NOP or DESL
ACTV
ROW
ADDRESS
Notes: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
42
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ SCITT TEST MODE
ABOUT SCITT
µC
Boundary
Scan
ASIC
SDRAM Controller
SCITT (Static Component Interconnection Test Technology) is a XNOR circuit based test technology that is used
for testing interconnection between SDRAM and SDRAM controller on the printed circuit boards. SCITT provides
inexpensive board level test mode in combination with boundary-scan. The basic idea is simple, consider all output
of SDRAM as output of XNOR circuit and each output pin has a unique mapping on the input of SDRAM. The ideal
schematic block diagram is as shown below.
TEST
Control
xAddress
Bus
SDRAM
CORE
XNOR
Data Bus
TEST Control : CAS, CS, CKE
xAddress Bus : A0 - Axx, RAS, DQM0 - DQMx, CLK, WE
Data Bus
: DQ0 - DQxx
It is static and provides easy test pattern that result in a high diagnostic resolution for detecting all single stuck-at
and bridging fault.
The MB81F643242B adopt SCITT mode as optional function. See Package and Ordering Information in page 2.
43
MB81F643242B-10FN-X Advanced Info (AE0.3E)
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge
command in POWER-UP INITIALIZATION. Once Precharge command is issued to SDRAM, it never get back to
SCITT Test Mode during regular operation for the purpose of a fail-safe way in get in and out of test mode.
1. Apply power. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power for a minimum of 100us.
3. Enter SCITT test mode.
4. Execute SCITT test.
5. Exit from SCITT mode.
It is required to follow Power On Sequence to execute read or write operation.
6. Start clock. Attempt to maintain either NOP or DESL command at the input.
7. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
8. Assert minimum of 2 Auto-Refresh command (REF).
9. Program the mode register by Mode Register Set command (MRS).
The 3,4,5 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to POWERUP INITIALIZATION).
COMMAND TRUTH TABLE
Control
Input
Output
CAS
CS
CKE
WE
RAS
A0
to
A12
DQM0
to
DQM3
CLK
DQ0
to
DQ31
SCITT mode entry
H→L *2
L
L
X
X
X
X
X
X
SCITT mode exit
L→H *3
H *5
L *5
X
X
X
X
X
X
SCITT mode
output enable *4
L
L
H
V
V
V
V
V
V
Notes: *1. L = Logic Low, H = Logic High, V = Valid, X = either L or H
*2. The SCITT mode entry command assumes the first CAS falling edge with CS and CKE = L after power
on.
*3. The SCITT mode exit command assumes the first CAS rising edge after the test mode entry.
*4. Refer the test code table.
*5. CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
44
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TEST CODE TABLE
DQ0 to DQ31 output data is static and is determined by following logic during the SCITT mode operation.
DQ0 = RAS xnor A0
DQ1 = RAS xnor A1
DQ2 = RAS xnor A2
DQ3 = RAS xnor A3
DQ4 = RAS xnor A4
DQ5 = RAS xnor A5
DQ6 = RAS xnor A6
DQ7 = RAS xnor A7
DQ8 = RAS xnor A8
DQ9 = RAS xnor A9
DQ10 = RAS xnor A10
DQ11 = RAS xnor A11
DQ12 = RAS xnor A12
DQ13 = RAS xnor DQM0
DQ14 = RAS xnor DQM1
DQ15 = RAS xnor DQM2
DQ16 = RAS xnor DQM3
DQ17 = RAS xnor CLK
DQ18 = RAS xnor WE
DQ19 = A0 xnor A1
DQ20 = A0 xnor A2
DQ21 = A0 xnor A3
DQ22 = A0 xnor A4
DQ23 = A0 xnor A5
DQ24 = A0 xnor A6
DQ25 = A0 xnor A7
DQ26 = A0 xnor A8
DQ27 = A0 xnor A9
DQ28 = A0 xnor A10
DQ29 = A0 xnor A11
DQ30 = A0 xnor A12
DQ31 = A0 xnor DQM0
• EXAMPLE OF TEST CODE TABLE
Output bus
RAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
DQM0
DQM1
DQM2
DQM3
CLK
WE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Input bus
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0 0 0 0 0 H H H H H H H H H H H H H H H H H H H H
0 0 0 0 0 L L L L L L L L L L L L L L L L L L L H
0 0 0 0 0 L H H H H H H H H H H H H H H H H H H L
0 0 0 0 0 H L H H H H H H H H H H H H H H H H H L
0 0 0 0 0 H H L H H H H H H H H H H H H H H H H H
0 0 0 0 0 H H H L H H H H H H H H H H H H H H H H
0 0 0 0 0 H H H H L H H H H H H H H H H H H H H H
0 0 0 0 0 H H H H H L H H H H H H H H H H H H H H
0 0 0 0 0 H H H H H H L H H H H H H H H H H H H H
0 0 0 0 0 H H H H H H H L H H H H H H H H H H H H
0 0 0 0 0 H H H H H H H H L H H H H H H H H H H H
0 0 0 0 0 H H H H H H H H H L H H H H H H H H H H
0 0 0 0 0 H H H H H H H H H H L H H H H H H H H H
0 0 0 0 0 H H H H H H H H H H H L H H H H H H H H
0 0 0 0 0 H H H H H H H H H H H H L H H H H H H H
0 0 0 0 0 H H H H H H H H H H H H H L H H H H H H
1 0 0 0 0 H H H H H H H H H H H H H H L H H H H H
0 1 0 0 0 H H H H H H H H H H H H H H H L H H H H
0 0 1 0 0 H H H H H H H H H H H H H H H H L H H H
0 0 0 1 0 H H H H H H H H H H H H H H H H H L H H
0 0 0 0 1 H H H H H H H H H H H H H H H H H H L H
1 1 1 1 1 L L L L L L L L L L L L L L L L L L L H
1 1 1 1 1 L H H H H H H H H H H H H H H H H H H L
1 1 1 1 1 H L H H H H H H H H H H H H H H H H H L
1 1 1 1 1 H H L H H H H H H H H H H H H H H H H H
1 1 1 1 1 H H H L H H H H H H H H H H H H H H H H
1 1 1 1 1 H H H H L H H H H H H H H H H H H H H H
1 1 1 1 1 H H H H H L H H H H H H H H H H H H H H
1 1 1 1 1 H H H H H H L H H H H H H H H H H H H H
1 1 1 1 1 H H H H H H H L H H H H H H H H H H H H
1 1 1 1 1 H H H H H H H H L H H H H H H H H H H H
1 1 1 1 1 H H H H H H H H H L H H H H H H H H H H
1 1 1 1 1 H H H H H H H H H H L H H H H H H H H H
1 1 1 1 1 H H H H H H H H H H H L H H H H H H H H
1 1 1 1 1 H H H H H H H H H H H H L H H H H H H H
1 1 1 1 1 H H H H H H H H H H H H H L H H H H H H
0 1 1 1 1 H H H H H H H H H H H H H H L H H H H H
1 0 1 1 1 H H H H H H H H H H H H H H H L H H H H
1 1 0 1 1 H H H H H H H H H H H H H H H H L H H H
1 1 1 0 1 H H H H H H H H H H H H H H H H H L H H
1 1 1 1 0 H H H H H H H H H H H H H H H H H H L H
1 1 1 1 1 H H H H H H H H H H H H H H H H H H H H
0 = input Low, 1 = input High, L = output Low, H = output High
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
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H
H
H
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L
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L
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H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
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H
H
L
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H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
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L
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H
H
H
45
MB81F643242B-10FN-X Advanced Info (AE0.3E)
AC SPECIFICATION
Parameter
Description
Minimum
Maximum
Units
tTS
Test mode entry set up time
10
—
ns
tTH
Test mode entry hold time
10
—
ns
tEPD
Test mode exit to power on sequence delay time
10
—
ns
tTLZ
Test mode output in Low-Z time
0
—
ns
tTHZ
Test mode output in High-Z time
0
20
ns
tTCA
Test mode access time from control signals
(output enable & chip select)
—
40
ns
tTIA
Test mode Input access time
—
20
ns
tTOH
Test mode Output Hold time
0
—
ns
tETD
Test mode entry to test delay time
10
—
ns
tTIH
Test mode input hold time
30
—
ns
TIMING DIAGRAMS
TIMING DIAGRAM – 1 : POWER-UP TIMING DIAGRAM
*2
VDD
100us Pause Time
Test Mode Entry Point
CS
CKE
*3
CAS
*1
Notes: *1. SCITT is enabled if CS = L, CKE = L, CAS = L at just power on.
*2. All output buffers maintains in High-Z state regardless of the state of control signals as long as
the above timing is maintained.
*3. CAS must not be brought from High to Low.
46
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence
and normal operation
VCC
Pause 100us
tTS
tTH
Test Mode
tEPD
H→L
CAS
CS
L
CKE
L
*3
*2
Entry
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, CKE pins will have some problems.
*2. PRE or PALL commands must not be asserted. Test mode is disable by those commands.
*3. Outputs must be disabled by CS = H or CKE = L before Exit.
47
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 3 : OUTPUT CONTROL (1)
VDD
Entry
CAS must not brought from High to Low
CAS
DQ turn to Low-Z at CS=L and CKE=H
DQ turn to High-Z at CS=H
CS
CKE
High-Z
DQ
Memory device
output buffer status
tTLZ
High-Z
Time (a)
Low-Z
tTHZ
Time (b)
High-Z
Time (c)
This is not bus line level
TIMING DIAGRAM – 4 : OUTPUT CONTROL (2)
VDD
Entry
CAS must not brought from High to Low
CAS
DQ turn to Low-Z at CS=L and CKE=H
CS
DQ turn to High-Z at CKE=L
CKE
High-Z
DQ
Memory device
output buffer status
High-Z
Time (a)
This is not bus line level
48
tTLZ
Low-Z
Time (b)
tTHZ
High-Z
Time (c)
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 5 : TEST TIMING (1)
Test mode
Entry Command
Test mode
Entry
tETD
Under test
CAS
CS
CKE
DQ becomes Low-Z at CS=L and CKE=H
A0
tTCA
Under
Check
Pins
A1
tTIA
tTIA
tTIA
A2
tTOH
Valid
DQ0 - DQn
tTOH
Valid
Valid
tTLZ
49
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 6 : TEST TIMING (2)
Test mode
Entry
CAS
L
CS-#1
L
Test mode
Exit
UnderTest
Changed under test devices
H
CS-#2
Tested #1 device
Tested #2 device
CKE
tTIH
tTIH
tTIH
tTCA
A0
tTLZ
Under
Check
Pins
tTHZ
A1
tTIA
tTIA
tTIA
tTIA
tTIA
A2
tTOH
DQ0 - DQn
(Bus)
50
Valid
tTOH
Valid
tTOH
Valid
Valid
Valid
MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 7 : TEST TIMING (3)
Test mode
Entry
CAS
L
CS-#1
L
Test mode
Exit
UnderTest
Changed under test devices
H
CS-#2
Tested #1 device
Tested #2 device
CKE
tTIH
tTHZ
tTIH
tTIH
A0
Under
Check
Pins
tTCA
A1
tTIA
tTIA
tTLZ
tTIA
tTIA
tTIA
A2
tTOH
DQ0 - DQn
(Bus)
Valid
tTOH
Valid
tTOH
Valid
Valid
Valid
51
MB81F643242B-10FN-X Advanced Info (AE0.3E)
■ PACKAGE DIMENSION
86-pin plastic TSOP(II)
(FPT-86P-M01)
*: Resin protrusion. (Each side: 0.15 (.006) MAX)
86
44
Details of "A" part
0.25(.010)
INDEX
0~8˚
LEAD No.
43
1
11.76±0.20(.463±.008)
* 22.22±0.10(.875±.004)
+0.05
0.22 −0.04
+.002
.009 −.002
0.10(.004)
0.50(.020)TYP
1.20(.047)MAX
M
52
1996 FUJITSU LIMITED F86001S-1C-1
10.16±0.10(.400±.004)
0.10(.004)
0.10±0.05
(.004±.002)
(STAND OFF)
+0.05
0.145 −0.03
+.002
.006 −.001
(Mounting height)
21.00(.827)REF
C
0.45/0.75
(.018/.030)
"A"
Dimensions in MM (inches)
MB81F643242B-10FN-X Advanced Info (AE0.3E)
MEMO
53
MB81F643242B-10FN-X Advanced Info (AE0.3E)
MEMO
54
MB81F643242B-10FN-X Advanced Info (AE0.3E)
MEMO
55
MB81F643242B-10FN-X Advanced Info (AE0.3E)
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9911
 FUJITSU LIMITED Printed in Japan
56
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
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arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
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CAUTION:
Customers considering the use of our products in special
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Any semiconductor devices have an inhereut chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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