SSI 32F8030 Programmable Electronic Filter A TDK Group Company April 1995 DESCRIPTION FEATURES The SSI 32F8030 Programmable Electronic Filter provides an electronically controlled low–pass filter with a separate differentiated low–pass output. A seven– pole, 0.05° Equiripple-type linear phase, low–pass filter is provided along with a single-pole, single-zero differentiator. Both outputs have matched delays. The delay matching is unaffected by any amount of programmed high frequency peaking (boost) or bandwidth. This programability, combined with low group delay variation makes the SSI 32F8030 ideal for use in many applications. Double differentiation high frequency boost is accomplished by a two–pole, low– pass with a two–pole, high–pass feed forward section to provide complementary real axis zeros. A variable attenuator is used to program the zero locations, which controls the amount of boost. • Ideal for: - constant density recording applications - magnetic tape recording The SSI 32F8030 programmable boost and bandwidth characteristics can be controlled by external DACs or DACs provided in the SSI 32D4661 Time Base Generator. Fixed characteristics are easily accomplished with three external resistors. In addition, boost can be switched in or out by a logic signal. • Programmable filter cutoff frequency (ƒc = 250 kHz to 2.5 MHz) • Programmable high frequency peaking (0 to 9 dB boost at the filter cutoff frequency) • Matched normal and differentiated low-pass outputs • • Differential filter input and outputs • • • • Total harmonic distortion less than 1% ±3.0% group delay variation from 0.2 ƒc to 1.75 ƒc, 0.25 MHz ≤ ƒc ≤ 2.5 MHz +5V only operation 16-Lead SON, and SOL packages 5 mW idle mode The SSI 32F8030 requires only a +5V supply and is available in 16-Lead SON, and SOL packages. BLOCK DIAGRAM VIN+ VIN- Low Pass Filter High Pass Filter Summer PIN DIAGRAM Low Pass Filter High Pass Filter Variable Atten. VO_NORM+ VO_NORM- VO_DIFF+ VO_DIFF- VBP IFP VREF VR BIAS PWRON GND1 1 16 VO_DIFF+ VO_NORM- 2 15 VO_DIFF- VO_NORM+ 3 14 PWRON VCC1 4 13 VR VIN- 5 12 VCC2 VIN+ 6 11 IFP VBP 7 10 VFP FBST 8 9 GND2 Filter Control VFP FBST GND1 GND2 VCC1 VCC2 CAUTION: Use handling procedures necessary for a static sensitive component. 04/14/95 - rev. 1 SSI 32F8030 Programmable Electronic Filter FUNCTIONAL DESCRIPTION SLIMMER HIGH FREQUENCY BOOST PROGRAMMING The SSI 32F8030, a high performance programmable electronic filter, provides a low pass 0.05° Equirippletype linear phase seven pole filter with matched normal and differentiated outputs. The device has been optimized for usage with several Silicon Systems products, including the SSI 32D4661 Time Base Generator, the SSI 32P54x family of Pulse Detectors, and the SSI 32P4720 Combo device (Data Separator and Pulse Detector). The amplitude of the output signal at frequencies near the cutoff frequency can be increased using this feature. Applying an external voltage to pin VBP which is proportional to reference output voltage VR (provided by the VR pin) will set the amount of boost. A fixed amount of boost can be set by an external resistor divider network connected from pin VBP to pins VR and GND. No boost is applied if pin FBST, frequency boost enable, is at a low logic level. CUTOFF FREQUENCY PROGRAMMING The amount of boost FB at the cutoff frequency Fc is related to the voltage VBP by the formula The SSI 32F8030 programmable electronic filter can be set to a filter cutoff frequency from 250 kHz to 2.5 MHz (with no boost). FB (ideal, in dB) = 20 log10[1.884(VBP/VR)+1], where 0<VBP<VR. Cutoff frequency programming can be established using either a current source fed into the IFP pin, whose output current is proportional to the SSI 32F8030 output reference voltage VR, or by means of an external resistor tied from the output voltage reference pin VR to pin VFP. The former method is optimized using the SSI 32D4661 Time Base Generator, since the current source into pin IFP is available at the DAC F output of the 32D4661. Furthermore, the voltage reference input is supplied to pin VR3 of the 32D4661 by the reference voltage VR from the VR pin of the 32F8030. This reference voltage is an internally generated bandgap reference, which typically varies less than 1 % over voltage supply and temperature variation. (For the calculations below IVFP = current into IFP or VFP pins). The cutoff frequency, determined by the -3dB point relative to a very low frequency value (< 10kHz), is related to the current IVFP injected into pin IFP by the formula Fc (ideal, in MHz) = 3.125•IFP = 3.125•IVFP•2.2/VR, where IFP and IVFP are in mA, 0.08<IFP<0.8 mA, and VR is in volts. If a current source is used to inject current into pin IFP, pin VFP should be left open. If the 32F8030 cutoff frequency is set using voltage VR to bias up a resistor tied to pin VFP, the cutoff frequency is related to the resistor value by the formula Fc (ideal, in MHz) = 3.125•IFP = 3.125•2.2/(3•Rx) where Rx is in kΩ, & 0.917 kΩ <Rx<9.17 kΩ. If pin VFP is used to program cutoff frequency, pin IFP should be left open. 2 SSI 32F8030 Programmable Electronic Filter PIN DESCRIPTION NAME TYPE DESCRIPTION VIN+, VIN- I DIFFERENTIAL SIGNAL INPUTS. The input signals must be AC coupled to these pins. VO_NORM+, O DIFFERENTIAL NORMAL OUTPUTS. The output signals must be AC coupled. VO_NORM- O VO_DIFF+, VO_DIFF- O DIFFERENTIAL DIFFERENTIATED OUTPUTS. For minimum time skew, these outputs should be AC coupled to the pulse detector. IFP I FREQUENCY PROGRAM INPUT. The filter cutoff frequency FC, is set by an external current IFP, injected into this pin. IFP must be proportional to voltage VR. This current can be set with an external current generator such as a DAC. VFP should be left open when using this pin. VFP I FREQUENCY PROGRAM INPUT. The filter cutoff frequency can be set by programming a current through a resistor from VR to this pin. IFP should be left open when using this pin. VBP I FREQUENCY BOOST PROGRAM INPUT. The high frequency boost is set by an external voltage applied to this pin. VBP must be proportional to voltage VR. A fixed amount of boost can be set by an external resistor divider network connected from VBP to VR and GND. No boost is applied if the FBST pin is grounded, or at logic low. FBST I FREQUENCY BOOST. A high logic level or open input enables the frequency boost circuitry. PWRON I POWER ON. A high logic level enables the chip. A low level puts the chip in a low power state. VR – REFERENCE VOLTAGE. Internally generated reference voltage. VCC1, VCC2 I +5 VOLT SUPPLY. GND1, GND2 – GROUND 3 SSI 32F8030 Programmable Electronic Filter ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation above maximum ratings may damage the device. PARAMETER RATING Storage Temperature -65 to +150°C Junction Operating Temperature, Tj +130°C Supply Voltage, VCC1, VCC2 -0.5 to 7V Voltage Applied to Inputs -0.5 to VCC + 0.5V IFP, VFP Inputs Maximum Current ≤1.2 mA RECOMMENDED OPERATING CONDITIONS Supply voltage, VCC1, VCC2 4.5 < VCC1,2 < 5.50V Ambient Temperature 0 < Ta < 70°C 4 SSI 32F8030 Programmable Electronic Filter Power Supply Characteristics Unless otherwise specified, recommended operating conditions apply. PARAMETER CONDITIONS MIN ICC Power Supply Current PWRON ≤ 0.8V ICC Power Supply Current PWRON ≥ 2.0V PD Power Dissipation PWRON ≥ 2.0V PD Power Dissipation PWRON ≤ 0.8V NOM MAX UNIT 0.5 mA 28 42 mA 140 231 mW 3 mW 2.0 VCC+0.3 V -0.3 0.8 V 20 µA DC Characteristics VIH High Level Input Voltage TTL input VIL Low Level Input Voltage IIH High Level Input Current VIH = 2.7V IIL Low Level Input Current VIL = 0.4V –1.5 mA Filter Characteristics ƒc = 1.25 MHz unless otherwise stated FCA Filter ƒc Accuracy using IFP pin: IFP = 0.4 mA or using VFP pin: Rx = 1.84 kΩ 1.125 1.375 MHz 1.20 V/V 1.1AO V/V 10.4 dB AO VO_NORM Diff Gain F = 0.67 ƒc, FB = 0 dB 0.8 AD VO_DIFF Diff Gain F = 0.67 ƒc, FB = 0 dB 0.9AO FBA Frequency Boost Accuracy VBP = VR 8.0 TGD0 Group Delay Variation Without Boost* 0.25 MHz ≤ ƒc ≤ 2.5 MHz F = 0.2 ƒc to 1.75 ƒc –3 +3 % Group Delay Variation With Boost* 0.25 MHz ≤ ƒc ≤ 2.5 MHz VBP = VR, F = 0.2 ƒc to 1.75 ƒc –3 +3 % TGDB 9.2 VIF Filter Input Dynamic Range THD = 1% max, F = 0.67 ƒc (no boost, 1000 pF capacitor across Rx) 1.0 Vpp VOF Filter Normal Output Dynamic Range THD = 1% max, F = 0.67 ƒc VBP = 0 (1000 pF capacitor across Rx) 1.0 Vpp VOF Filter Normal Output Dynamic Range THD = 1% max, F = 0.67 ƒc VBP = VR (1000 pF capacitor across Rx) 1.0 Vpp VOF Filter Differentiated Output Dynamic Range THD = 1% max, F = 0.67 ƒc VBP = 0 (1000 pF capacitor across Rx) 1.0 Vpp VOF Filter Differentiated Output Dynamic Range THD = 1% max, F = 0.67 ƒc VBP = VR (1000 pF capacitor across Rx) 1.0 Vpp 5 SSI 32F8030 Programmable Electronic Filter Filter Characteristics (continued) PARAMETER CONDITIONS RIN Filter Diff Input Resistance CIN MIN NOM MAX UNIT 3.0 4.0 5.0 kΩ 3.0 Filter Diff Input Capacitance* pF EOUT Output Noise Voltage* Differentiated Output BW = 100 MHz, Rs = 50Ω, Iƒp = 0.8 mA, VBP = 0.0V 2.7 3.2 mVRms EOUT Output Noise Voltage* Normal Output BW = 100 MHz, Rs = 50Ω Iƒp = 0.8 mA, VBP = 0.0V 1.6 2.0 mVRms EOUT Output Noise Voltage* Differentiated Output BW = 100 MHz, Rs = 50Ω Iƒp = 0.8 mA, VBP = VR 3.1 3.8 mVRms EOUT Output Noise Voltage* Normal Output BW = 100 MHz, Rs = 50Ω Iƒp = 0.8 mA, VBP = VR 1.8 2.2 mVRms EOUT Output Noise Voltage* Differentiated Output BW = 10 MHz, Rs = 50Ω, Iƒp = 0.08 mA, VBP = 0.0V 1.8 2.1 mVRms EOUT Output Noise Voltage* Normal Output BW = 10 MHz, Rs = 50Ω Iƒp = 0.08 mA, VBP = 0.0V 1.0 1.2 mVRms EOUT Output Noise Voltage* Differentiated Output BW = 10 MHz, Rs = 50Ω Iƒp = 0.08 mA, VBP = VR 2.0 2.5 mVRms EOUT Output Noise Voltage* Normal Output BW = 10 MHz, Rs = 50Ω Iƒp = 0.08 mA, VBP = VR 1.1 1.5 mVRms IO- Filter Output Sink Current 1.0 mA IO+ Filter Output Source Current 2.0 mA RO Filter Output Resistance** Sinking 1 mA from pin 70 Ω 2.40 V 2.0 mA * Not directly testable in production, design characteristic. ** Single ended Filter Control Characteristics VR IVR Reference Voltage Output 2.0 Reference Output Source Current 6 SSI 32F8030 Programmable Electronic Filter 2 1 1.8 1 ifp = 80 µA 2 ifp = 224 µA 3 ifp = 368 µA 4 ifp = 512 µA 5 ifp = 656 µA 6 ifp = 800 µA 1.6 1.4 (ƒc = 250 kHz) (ƒc = 700 kHz) (ƒc = 1.15 MHz) (ƒc = 1.6 MHz) (ƒc = 2.05 MHz) (ƒc = 2.5 MHz) Delay (µs) 1.2 1.0 2 0.8 0.6 3 0.4 4 0.2 0.0 100k 300k 200k 400k 500k 700k 1meg 2meg 3meg FIGURE 1: Typical Normal/Differentiated Output Group Delay Response GND1 VO_NORMVO_NORM+ 1 16 2 15 3 14 VCC1 (+5V) VINVIN+ VBP FBST 4 13 5 12 6 11 7 10 8 9 VO_DIFF+ VO_DIFFPWR_ON VR VCC2 (+5V) IFP Cx VFP GND2 Rx RBP1 RBP2 FIGURE 1: 32F8030 Applications Setup 16-Pin SO VR = 2.2V IVfp = .33VR/Rx VFP = .667 VR IVfp range: 0.08 mA to 0.8 mA (0.25 MHz to 2.5 MHz) Cx = 1000 pF needed for THD at low ƒc VFP is used when programming current is set with a resistor from VR. When VFP is used IFP must be left open. 7 6 4meg 5meg Frequency (Hz) 32F8030 5 Rx ƒc Control SUM IFP IR Cx VR Boost Control VO_DIFF- VR3 VBP DACS Serial Control 7-bit DAC Ref FOUT To Data Sync Phase Lock Loop 7-bit DAC 7-bit DAC DACI To Data Sync 7-bit DAC DACM To Data Sync 32F8030 32D4661 2k CIN– CIN+ VO_NORM- VO_DIFF+ HP DIN– DIN+ OUT– OUT+ VIN- LP VO_NORM+ HP VIN+ LP DACF Ref to µController SCLK SDEN SDATA SSI 32F8030 Programmable Electronic Filter Active Differentiator IN+ IN– DFF BYP Charge Pump FWR AGC LEVEL OS RD To Data Sync 32P54X HYS IOF = DACF output current F = DAC setting: 0-127 IOF = (0.98F•VR)/127Rx Full scale, F = 127 Rx = (0.98F•VR)/127IOF For range of Max ƒc = 2.5 MHz then IFP = 0.8 mA Rx = current reference setting resistor Therefore, for Max programming current range to 0.8 mA: VR = Voltage Reference = 2.2V Rx = (0.98)(2.2/0.8) = 2.7 kΩ Please note that in setups such as this where IFP is used for cutoff frequency programming VFP must be left open. FIGURE 2: Applications Setup, Constant Density Recording 32F8030, 32P54X, 32D4661 + +1.31703 INPUT 2 S + S 1.68495 + 1.31703 2.95139 S + S 1.54203 + 2.95139 ∑ 2 5.37034 S + S 1.14558 + 5.37034 2 NORM 0.86133 S + 0.86133 AN S S + 0.86133 AD NORM + –KS 2 2 S + S 1.68495 + 1.31703 Normalized for ωc = (2π) ƒc = 1 AN and AD are adjusted for unity gain (0 dB) at F = 0.67 ƒc Denormalize the frequency by substituting S → (S/2πƒc) Eq for ƒc = 2.5 MHz, S = S / [(2π) (2.5 • 10 6)] = S / (1.57080 • 10 7) FIGURE 3: 32F8030 Normalized Block Diagram 8 DIFF SSI 32F8030 Programmable Electronic Filter TABLE 1: 32F8030 Frequency Boost Calculations - K = 1.31703 (10BOOST (dB) / 20 -1) Assuming 9.2 dB boost for VBP = VR ( ( ) ) FB/20 −1 VBP 10 ≅ VR 1.884 Boost K VBP/VR Boost K VBP/VR 1 dB 2 dB 3 dB 4 dB 5 dB 0.16 0.34 0.54 0.77 1.03 0.065 0.137 0.219 0.310 0.413 6 dB 7 dB 8 dB 9 dB 1.31 1.63 1.99 2.40 0.528 0.657 0.802 0.965 VBP/VR Boost VBP/VR 0.1 0.2 0.3 0.4 0.5 1.499 dB 2.777 dB 3.891 dB 4.879 dB 5.765 dB 0.6 0.7 0.8 0.9 1.0 or, VBP boost in dB = 20log 1.884 +1 VR Boost 6.569 7.305 7.984 8.613 9.200 dB dB dB dB dB TABLE 2: Calculations Typical change in ƒ-3 dB point with boost Boost (dB) Gain @ ƒc(dB) Gain @ peak(dB) ƒpeak/ƒc f-3 dB/ƒc 0 1 2 3 4 5 6 7 8 9 -3 -2 -1 0 1 2 3 4 5 6 0.00 0.00 0.00 0.15 0.99 2.15 3.41 4.68 5.94 7.18 no peak no peak no peak 0.70 1.05 1.23 1.33 1.38 1.43 1.46 1.00 1.21 1.51 1.80 2.04 2.20 2.33 2.43 2.51 2.59 Notes: 1. ƒc is the original programmed cutoff frequency with no boost 2. ƒ-3 dB is the new -3 dB value with boost implemented 3. ƒpeak is the frequency where the magnitude peaks with boost implemented i.e., ƒc = 2.5 MHz when boost = 0 dB if boost is programmed to 5 dB then f-3 dB = 5.5 MHz ƒpeak = 3.075 MHz 9 SSI 32F8030 Programmable Electronic Filter PACKAGE PIN DESIGNATIONS (Top View) Thermal Characteristics: θjA GND1 1 16 VO_DIFF+ VO_NORM- 2 15 VO_DIFF- 16-lead SON (150 mil) 105° C/W VO_NORM+ 3 14 PWRON 16-lead SOL (300 mil) 100° C/W VCC1 4 13 VR VIN- 5 12 VCC2 VIN+ 6 11 IFP VBP 7 10 VFP FBST 8 9 GND2 16-Lead SON, SOL CAUTION: Use handling procedures necessary for a static sensitive component. ORDERING INFORMATION PART DESCRIPTION ORDER NUMBER PACKAGE MARK 16-lead SON (150 mil) 32F8030-CN 32F8030-CN 16-lead SOL (300 mil) 32F8030-CL 32F8030-CN No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914 04/14/95 - rev. 10 ©1991 Silicon Systems, Inc. Protection by the following patents: 5182477, 5235540