SEMTECH SC2450

SC2450
BI-Phase/Dual Controller
POWER MANAGEMENT
Description
The SC2450 can be configured as a dual converter or a
bi-phase converter for high current applications. The part
is designed for point of use power supplies with 10-30V
nominal backplane power sources. Multiple supplies can
be synchronized together to prevent low frequency harmonics on the backplane. The power dissipation is controlled using a novel low voltage supply technique, allowing high speed and integration, with the high drive currents to ensure low MOSFET switching loss.
The use of high speed switching circuits allows very narrow PWM outputs down to 15:1 voltage ratios. Single
pin compensation for each channel simplifies development as well as reducing external pin count.
Capable of driving MOSFETs via external driver transistors for phase currents beyond 20A.
Features
K
K
K
K
K
K
K
K
K
Selectable dual output or bi-phase operation
Direct drive for N-channel MOSFETs
Undervoltage lockout
Synchronization to external clock
Multi-converter synchronization
Soft start
Fast transient response
Max duty cycle 45%
Output over voltage protection
Applications
K Power supplies for advanced telecoms/datacoms
K SO IP, Ethernet and PABX power supplies
Typical Application Circuit
Revision 2, August 2001
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SC2450
POWER MANAGEMENT
Absolute Maximum Ratings
Parameter
Supply Voltage
Voltage on BST Pins
Oscillator Frequency
Symbol
Maximum
Units
VIN
34
V
V BST
42
V
2
MHz
8
V
(1)
VC C
Thermal Resistance Junction to Case
θJC
25
°C/W
Thermal Resistance Junction to Ambient
θJ A
80
°C/W
Operating Temperature Range
TA
-40 to +85
°C
Storage Temperature Range
TSTG
-55 to +150
°C
Lead Temperature (Soldering) 10 seconds
TLEAD
300
°C
Note:
(1) Maximum frequency and maximum supply voltage could cause excessive power dissipation in the part.
Electrical Characteristics
Unless specified VIN = 24V, TA = 25°C
PARAMETER
Supply Voltage, VIN
CONDITIONS
Supply Current
ENABLE = 0
MIN
10
TYP
MAX
30
UNITS
V
30
40
mA
Under Voltage Lockout
5.8
V
UVLO Hysteresis
Voltage Regulator
400
mV
Pre Regulator Voltage
Bgout Voltage
6
CREF = 4.7nF
0.99
Bgout Impedance
REGDRV Pin Sink Current
IREGDRV
1
7
V
1.01
V
3
KΩ
5
mA
10
mV
Error Amp
Input Offset Voltage
Input Impedance
5
Linear Transconductance
KΩ
.002
A/V
Internal Oscillator
Frequency
RREF = 30K
1
MHz
Frequency
RREF = 60K
500
kHz
Ramp Valley to Peak
VIN = 12V
1.5
V
Ramp Valley to Peak
VIN = 24V
3
V
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SC2450
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified VIN = 24V, TA = 25°C
PARAMETER
External Clock
Detect Time
CONDITIONS
MIN
TYP
Rise Time < 50ns
MAX
UNITS
2
µs
Unlock Time
10
50
µs
Frequency Range
High Side Gate Drive
0.3
1
MHz
Max Duty Cycle
45
%
Peak Source
CLOAD = 10nF
1
A
Peak Sink
CLOAD = 10nF
1
A
Peak Source
CLOAD = 10nF
2
A
Peak Sink
CLOAD = 10nF
2
A
50
ns
Low Side Gate Drive
Sync Drive Timing
Min Non-overlap
PWM Match
CLOAD = 1nF Fet Drive < 1V
20
50% Duty Cycle, FOSC = 1MHz
-1
1
%
VIN = 0 - 5V
-10
10
µA
Logic Input Pins
Input Bias Current
Logic Threshold
FB2 Disable Threshold
0.8
V
VCC - 0.7V
V
Over Current Protection
OCP Threshold
103
127
mV
700
µA
50
µA
OVP Threshold
120
%
Thermal Shutdown
150
°C
OC+ I/P Bias Current
VIN = 24V
115
OC- I/P Bias Current
Over Voltage Protection
Note:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC2450
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number(1)
Top View
SC2450ISWTR
S C 2450E V B
PACKAGE
TAMB (TA)
SO-28
-40 - +85°C
SC2450 Evaluation Board
Note:
(1) Only available in tape and reel packaging. A reel contains 1000 devices.
(28-Pin SOIC)
Block Diagram
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SC2450
POWER MANAGEMENT
Pin Descriptions
Pin
Pin Name
1
FB1
2
COMP1
3
NC
No connection.
4
BG
1V reference for error amplifiers, 3K source impedance.
5
FB2
Feedback for channel 2.
6
COMP2
7
REGDRV
Regulator drive for external pass transistor.
8
ENABLE
Enable threshold is 2.05 V, connect to ground to disable.
9
PHASE2
Phase node input for channel 2.
10
DRVH2
Gate drive for high side channel 2.
11
BSTH2
Bootstrap input for high side channel 2.
12
DRVL2
Gate drive for low side channel 2.
13
BSTL2
Supply for low side channel 2.
14
VCC
Pre-regulated IC power supply.
15
BSTL1
Supply for low side channel 1.
16
DRVL1
Gate drive for low side channel 1.
17
BSTH1
Bootstrap input for high side channel 1.
18
DRVH1
Gate drive for high side channel 1.
19
PHASE1
Phase node input for high side channel 1.
20
PGND
21
OC+
Overcurrent comparator inverting input.
22
OC-2
Overcurrent comparator non-inverting input for channel 2.
23
OC-1
Overcurrent comparator non-inverting input for channel 1.
24
EXTCLK
External clock, converter locks to this input when a valid signal is present.
25
CLKOUT
Clock out, logic level drive to provide synchronizing signal for other converters.
26
NC
No connection.
27
AGND
Analog ground.
28
RREF
External reference resistor for internal oscillator and ramp generator.
 2001 Semtech Corp.
Pin Function
Feedback for channel 1.
Compensation for channel 1.
Compensation for channel 2.
Power ground.
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SC2450
POWER MANAGEMENT
Typical Application
Schematic for Two Channel Operation
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SC2450
POWER MANAGEMENT
Typical Application (Cont.)
Bill of Material for Two Channel Operation
Item
Qty Reference
Part Number/Value
Manufacturer
1
8
C1 - C8
0.47µF, 50V, Cer.
Any
2
3
C9,C24,C25
0.33µF, Cer., 1206
Any
3
2
C10,C11
22nF, Cer., 1206
Any
4
1
C12
0.1µF, Cer., 1206
Any
5
2
C13,C14
10nF, Cer., 1206
Any
6
1
C15
47pF, Cer., 1206
Any
7
6
C16,C19,C20,C21,C22,C23
22µF, 35V, Tant.
Any
8
2
C17,C18
680µF, 35V, Alum.
Any
9
2
C26,C27
2.2nF, Cer., 1206
Any
10
3
C28,C29,C50
1.0nF, Cer., 1206
Any
11
1
C30
1.0µF, Cer., 1206
Any
12
11
C31,C32,C33,C36,C37,C40,C41,C42,C43,C44,C45
10µF, Cer., 1206
Any
13
4
C34,C35,C38,C39
1500µF, 6.3V, Alum.
Any
14
4
D1,D2,D5,D6
1A, 40V, Schottky, MELF,
1N5819M
Any
15
2
D3,D4
3A, 40V, Schottky, 30BQ040
Any
16
2
L1,L2
Inductor, 9 turns
Magnetics:
Kool Mu
P/N: 77206-A7
17
4
M1,M2,M3,M4
N-Channel MOSFET, TO263AB
Fairchild
P/N: FDB7030BL
18
1
Q1
80V, 1A, NPN, Med. Pwr.
SOT-223
BCP56CT
19
2
R1,R3
2.2, 5%, 1206
Any
20
2
R4,R6
4.7, 5%, 1206
Any
21
4
R2,R5,R7,R11
1.0, 5%, 1206
Any
22
1
R8
56k, 5%, 1206
Any
23
2
R9,R10
2.2k, 5%, 1206
Any
24
1
R12
Chip resistor,
0.005, 1W, 1%, 2512
Any
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SC2450
POWER MANAGEMENT
Typical Application (Cont.)
Bill of Material for Two Channel Operation (Cont.)
Item
Qty Reference
Part Number/Value
Manufacturer
25
4
R13,R14,R15,R16
2.2, 1/4W, 5%, 1210
Any
26
1
R17*,R19,R31*
Chip resistor, 0, 1206
Any
27
2
R20,R21
1.00k, 1%, 1206
Any
28
1
R22
2.32k, 1%, 1206
Any
29
1
R23
4.02k, 1%, 1206
Any
30
2
R26,R27
20, 5%, 1206
Any
31
1
R28
10, 5%, 1206
Any
32
1
R29
51, 5%, 1206
Any
33
1
R34
15k, 5%, 1206
Any
34
1
R36
68.1k, 1%, 1206
Any
35
1
R37
10.0k, 1%, 1206
Any
36
0
Roc1*,Roc2*
TBD, 1%, 1206
Any
37
1
SC2450
Bi-Phase/Dual Controller,
SO-28W
Semtech Corp.
P/N: SC2450ISW
805-498-2111
Notes:
1. * Indicates optional parts.
2. Some parts are selected due to availability or lead time, and are not optimized.
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SC2450
POWER MANAGEMENT
Typical Application (Cont.)
Schematic for Bi-Phase Operation
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SC2450
POWER MANAGEMENT
Electrical Characteristic Curves
Two Channel Operation
Efficiency in Two-Channel Application Circuit (5V/12A, 3.3V/18A)
Overall System Efficiency vs. Overall Load (W ) of the 5V and 3.3V channels
95.00%
90.00%
Efficiency
85.00%
80.00%
Efficiency
75.00%
70.00%
65.00%
60.00%
0
20
40
60
80
100
120
Output Power (W )
Phase Node Waveform of Two-Channel Application Circuit (Vin = 24V, Load Current = 12A for
5V, Load Current = 18A for 3.3V)
ch1: Vphase5V; ch2: Vphase3.3V
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SC2450
POWER MANAGEMENT
Electrical Characteristic Curves (Cont.)
3.3V Channel Gate Waveform (Vin = 24V, Load Current = 18A)
ch1: VgateH; ch2: VgateL
5.0V Channel Gate Waveform (Vin = 24V, Load Current = 12A)
ch1: VgateH; ch2: VgateL
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SC2450
POWER MANAGEMENT
Electrical Characteristic Curves (Cont.)
Start-up (Vin = 24V, Vout1 = 5.0V/12A, Vout2 = 3.3V /18A)
ch1: Vout5.0V; ch2: Vout3.3V
Bi-Phase Operation (Vout = 3.3V, Max. Load Current = 20A)
Efficiency in Bi-Phase Application Circuit (3.3V/20A)
Overall System Efficiency vs. iLoad
90.00%
85.00%
Efficiency
80.00%
75.00%
Overall Efficiency
70.00%
65.00%
60.00%
0
5
10
15
20
Load Current (A)
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SC2450
POWER MANAGEMENT
Electrical Characteristic Curves (Cont.)
Phase Node Waveform (Vin = 24V, Vout = 3.3V, Load Current = 20A)
ch1: Vphase1; ch2: Vphase2
Gate Waveform (Vin = 24V, Vout = 3.3V, Load Current = 10A/phase)
ch1: VgateL; ch2: VgateH
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SC2450
POWER MANAGEMENT
Electrical Characteristic Curves (Cont.)
Start-up (Vin = 24V, Vout = 3.3V, Load Current = 5A/phase)
ch1: Vout
Theory of Operation
The SC2450 employs a voltage mode control with feed forward
to provide fast output response to load and line transients.
The SC2450 has two outputs, which can be used to generate
two separate supply voltages or can be combined in bi-phase
operation to generate one single supply voltage. The internal
reference is trimmed to 1 V with +/-1% accuracy, and the outputs voltages can be adjusted by two external resistors. In biphase operation, the dual switching regulators are operated
180° out of phase. Load current sharing between phases is
normally required, and this can be achieved by using precise
feedback voltage divider resistors (typically 0.1%) to match
individual phase output voltage. In addition, small drooping resistors ( could be PCB traces) are employed at the output of
each phase to enhance phase current balance.
PWM Control
Changes on the output voltages are fed to the inverting input of
the Error Amplifiers, by the FB1 and FB2 pins, and compared
with the internal 1 V reference. The compensation to the
transconductance amplifier is achieved by connecting a capacitor in series with a resistor from the COMP1 and COMP2
pins to AGND respectively. The error signal from the error amplifier is compared to the saw tooth waveform by the PWM
comparator, and matched timing signal is generated to control
the upper and lower gate drives of the two phases.
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A single Ramp signal is used to generate the control signals
for both of phases, hence the maximum duty cycle is less
than 50%.
Oscillator Frequency Selection
The sawtooth signal is generated by charging an internal capacitor with a current source. The charge current is set by an
external resistor connected from the RREF pin to AGND. The
oscillator frequency and the external resistance follow an inversely proportional relationship.
Feed Forward
The SC2450 incorporates a voltage feed forward scheme to
improve line transient immunity when changes of the input voltage occur. As the input voltage changes, the ramp valley to
peak voltage of the internal oscillator follows this change instantly. As a result the output voltage will have minimum disturbance due to the input line change.
Synchronized Operation
The internal oscillator can be synchronized to an external clock
operating in the range of 300 kHz to 1 MHz. The switching
frequency of each channel is one half of the oscillator frequency.
The oscillator clock is also available externally through the
CLKOUT pin and can be used to provide synchronization for
other converters.
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SC2450
POWER MANAGEMENT
Theory of Operation (Cont.)
Bias Generation
Over Current Protection
A 6-7 Volt supply voltage is required to power up the SC2450.
This voltage could be provided by an external power supply or
derived from VIN through an external pass transistor. REGDRV
is the control signal to the base of the pass transistor that will
regulate VCC. The voltage at the VCC pin is compared to the
internal voltage reference, and the REGDRV pin can sink up to
5 mA current to regulate the voltage at the VCC pin.
The SC2450 current limit provides protection during an over
current condition. A sense resistor or PCB trace can be used
to sense the input supply current.
Enable
If the ENABLE pin is connected to logic high, the SC2450 is
enabled, while connecting it to ground will put the device into
disabled mode. The ENABLE pin can also be configured as
input UVLO through input voltage divider resistors. The controller will be enabled when the ENABLE pin voltage reaches 2.05
V, and will be disabled with 400 mV hysteresis.
Under Voltage Lockout
Under Voltage lockout (UVLO) circuitry senses VCC through a
voltage divider. If this signal falls below 5.8 V, with a typical
hysteresis of 400 mV, the BG pin is pulled low by an internal
transistor causing the lower MOSFET gate to be on and the
upper MOSFET gate off for both phases.
Over Voltage Protection
The SC2450 provides OVP protection for each output individually. Once the converter output voltage exceeds 120% nominal
output voltage, the lower MOSFET gates are latched on and
the upper MOSFET gates are latched off. The latch is then
reset once the OVP condition is removed.
Soft Start
An external capacitor at the BG pin is used to set up the Soft
Start duration. The capacitor value, in conjunction with the
internal 3K resistor at the BG pin, control the duration to bring
up the bandgap to its final level. As the BG capacitor is being
charged through the internal resistor, the PWM pulse opens
accordingly until the bandgap is charged completely. This
controlled start up of the PWM prevents output voltage overshoot, unnecessary component stress, and noise generation
during start up.
 2001 Semtech Corp.
The over current protection trip point is determined by the voltage drop across the sense resistor. Once this voltage drop
exceeds 115 mV, OCP protection circuit will be triggered. Due
to component and layout parasitics, filtering might be necessary across the OC+ and OC- pins. It is recommended to use
20 Ohm resistor and 10 nF capacitor for filtering. The OCP
accuracy may be affected by non-ideal PCB layout and
MOSFET variations. To accommodate these variations, the OCP
threshold can be externally adjusted by a voltage divider across
the sense resistor to attenuate the voltage drop across the
sense resistor, so that increase the OCP threshold accordingly. See application circuits.
Once an over current condition occurs, the lower MOSFET
gates are latched on and the upper MOSFET gates are latched
off. The latch is then reset at the beginning of the next clock
cycle. The cycle is repeated indefinitely until the over current
condition removed.
Thermal Shutdown
In addition to current limit, the SC2450 monitors over temperature condition. The over temperature detect will shut down the
part if the SC2450 die temperature exceeds 150°C, and will
auto reset once the die temperature is dropped down.
Gate Drive
The SC2450 integrates high current gate drivers for fast switching of large MOSFETs. The high-side gates can be switched
with peak currents of 1 Amp, while the larger low-side gates
can be switched with peak currents of 2 Amps. A cross conduction prevention circuitry ensures a non-overlapping operation between the Upper and Lower MOSFETs. This prevents
false current limit tripping and provides high efficiency.
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SC2450
POWER MANAGEMENT
Control Loop Design
R2
R1
The task here is to properly choose the compensation network
for a nicely shaped loop-gain Bode plot. The following design
procedures are recommended to accomplish the goal:
0
Gpwm
Error-Amp
Verror
-
L
Duty
(1) Calculate the corner frequency of the output filter:
+
R
Rc
+
1
+
C
0
Co
-
0
0
0
Fig. 1. SC2450 control model.
The control model of SC2450 can be depicted in Fig. 1. This
model can also be used in Spice kind of simulator to generate
loop gain Bode plots. The bandgap reference is 1 V and
trimmed to +/-1% accuracy. The desired output voltage can
be achieved by setting the resistive divider network, R1 and
R2.
The error amplifier is transconductance type with fixed gain of:
.. ..
A
.
G error . 0.002 ⋅
V
The compensation network includes a resistor and a capacitor
in series, which terminates from the output of the error amplifier to the ground.
This device uses voltage mode control with input voltage feed
forward. The peak-to-peak ramp voltage is proportional to the
input voltage, which results in an excellent performance to reject input voltage variation. The PWM gain is inversion of the
ramp amplitude, and this gain is given by:
G pwm
1
F e sr
2 . π. R
F e r s<
F sw
5
If this condition is not met, the compensation structure may
not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the
output filter corner frequency and the ESR zero frequency. In
some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended
to use only high frequency multi-layer ceramic capacitors for
output filter.
(4) Choose the loop gain cross over frequency (0 dB frequency).
It is recommended that the crossover frequency is always less
than one fifth of the switching frequency or the output ripple
frequency in bi-phase mode operation:
Fx_over
The total control loop-gain can then be derived as follows:
1 s. R c. C o
1 s. R. C .
T( s) T o.
s. R. C
Rc
L
2
1 s. R c. C o
s . L. C o. 1
Ro
Ro
where
F sw
5
If the transient specification is not stringent, it is better to choose
a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the
compensation network can then be calculated as:
R
1
G pwm. V in. G error
.
F esr
2
.
F x_over
Fo
F esr
.
Vo
V bg
when:
F o < F esr< F x_o ver
R2
R1
.
c C o
(3) Check that the ESR zero frequency is not too high.
V ramp
.. ..
T o G error.V in.G pwm .R .
2 .π. L .C o
(2) Calculate the ESR zero frequency of the output filter capacitor:
1
where the ramp amplitude (peak-to-peak) is 3 volts when input
voltage is 24 volts.
 2001 Semtech Corp.
Fo
Ro
Vin
Vbg
R2
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SC2450
POWER MANAGEMENT
Control Loop Design (Cont.)
Step 1. Output filter corner frequency
or
R
1
.
Fo
2
G pwm. V in. G error F esr
.
F x_over
Fo
.
Vo
F
V bg
o
= 1.453 KHz
Step 2. ESR zero frequency:
when
F esr< F o < F x_over
(5) The compensation capacitor is determined by choosing the
compensator zero to be about one fifth of the output filter corner frequency:
Fo
F zero
C
F
Step 3. Check the following condition:
F ers<
F sw
5
Which is satisfied in this case.
Step 4. Choose crossover frequency and calculate compensator R:
zero
F
(6) The final step is to generate the Bode plot, either by using
the simulation model in Fig. 1 or using the equations provided
here with Mathcad. The phase margin can then be checked
using the Bode plot. Usually, this design procedure ensures a
healthy phase margin.
An example is given below to demonstrate the procedure introduced above. The parameters of the power supply are given
as:
V
V
I
in
o
o
:= 24 V
x_over
= 30 KHz
R = 2.95 KΩ
Step 5. Calculate the compensator C:
C = 186 nF
Step 6. Generate Bode plot and check the phase margin. In
this case, the phase margin is about 85°C that ensures the
loop stability. Fig. 2 shows the bode plot of the loop.
:= 2.5 V
:= 20 A
:= 150 KHz
sw
L := 4 µH
C
o
R
R
R
 2001 Semtech Corp.
= 2.653 KHz
5
1
2 . π. R . F
F
esr
:= 3000 µF
c
:= 0.02 Ω
1
:= 1.5 KΩ
2
:= 1.0 KΩ
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SC2450
POWER MANAGEMENT
Control Loop Design (Cont.)
L o o p G ain M ag ( dB)
10 0
ma g ( i )
50
0
50
10
10 0
3
1 10
F
4
1 10
5
1 10
6
1 10
i
L o o p G ain P h ase ( D egr ee)
0
45
p h a s e( i )
90
13 5
18 0
10
10 0
3
1 10
F
4
1 10
5
1 10
6
1 10
i
Fig. 2. Bode plot of the loop
Layout Guidelines
Good layout is necessary for successful implementation
of the SC2450 bi-phase/dual controller. Important layout
guidelines are listed below.
1). The high power parts should be laid out first. The parasitic inductance of the pulsating power current loop (start
from positive end of the input capacitor, to top MOSFET,
then to bottom MOSFET back to power ground) must be
minimized. The high frequency input capacitors and top
MOSFETs should be close to each other. The freewheeling Schottky diode, the bottom MOSFET snubber, and
the bottom MOSFET should be placed close to each other.
The MOSFET gate drive and current sense loop areas
should be minimized. The gate drive trace should be
short and wide.
2). The layout of the two phases should be made as symmetrical as possible. The SC2450 controller should be
placed in the center of the two phases. Please see evaluation board layout as an example.
be provided. Power current should avoid running over the
analog ground plane. The AGND is star connected to the
PGND at the converter output to provide best possible
ground sense. Refer to the application schematics, certain components should be connected directly to the AGND.
4). If a multi-layer PCB is used, power layer and ground
layer are recommended to be adjacent to each other.
Typically the power layer is on the top, followed by the
ground layer. This results in the least parasitic inductance
in the MOSFET-capacitor power loop, and reduces the
ringing on the phase node. The rest of the layers could
be used to run DC supply traces and signal traces.
An example of a two-layer PCB layout is given below to
illustrate these layout principles.
3). Separate ground planes for analog and power should
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SC2450
POWER MANAGEMENT
Layout Guidelines (Cont.)
Component Side (TOP)
Copper (TOP)
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SC2450
POWER MANAGEMENT
Layout Guidelines (Cont.)
PGND
A GN D
Copper (BOTTOM)
Outline Drawing - SO-28W
Contact Information
Semtech Corporation
Power Management Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
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