EMIF06-1502M12 IPAD™ 6 line low capacitance EMI filter and ESD protection in Micro QFN package Main product characteristics 12 1 Where EMI filtering in ESD sensitive equipment is required: 11 2 ■ LCD & CAMERA for Mobile phones 9 Computers and printers 8 5 7 6 ■ ■ Communication systems ■ MCU Boards 10 3 GND GND 4 Micro QFN 2.5 mm x 1.5 mm (bottom view) Description The EMIF06-1502M12 is a 6 line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. Pin configuration (top view) This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input pins. Benefits ■ EMI asymmetrical (I/O) low-pass filter ■ High efficiency in EMI filtering ■ Very low PCB space consuming: 2.5 mm x 1.5 mm ■ Very thin package: 0.6 mm max ■ High efficiency in ESD suppression on inputs pins (IEC 61000-4-2 level 4). ■ High reliability offered by monolithic integration ■ High reducing of parasitic elements through integration and wafer level packaging. ■ Lead free package Output 12 2 Input Output 11 3 Input Output 10 4 Input Output 9 5 Input Output 8 6 Input Output 7 Basic cell configuration 170 Ω Input Output Typical line capacitance = 14 pF @ 2.5 V Complies with following standards: Order code IEC 61000-4-2 level 4 input pins 1 Input 15kV (air discharge) Part number Marking EMIF06-1502M12 E 8kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3 (all pins) July 2006 TM: IPAD is a trademark of STMicroelectronics Rev 2 1/9 www.st.com Characteristics EMIF06-1502M12 1 Characteristics Table 1. Absolute ratings (limiting values at Tamb = 25° C unless otherwise specified) Symbol VPP Tj Parameter Value Unit ESD discharge IEC 61000-4-2 air discharge on input pins ESD discharge IEC 61000-4-2 contact discharge on input pins 15 8 kV Junction temperature 125 °C Top Operating temperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C Table 2. Electrical characteristics (Tamb = 25° C) Symbol Parameter I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage IF VBR VCL Dynamic resistance IPP Peak pulse current RI/O Series resistance between Input & Output Cline Input capacitance per line Symbol IPP Test conditions VBR IR = 1 mA IRM VRM = 3 V per line RI/O Tolerance ± 10% Cline VR= 2.5 V DC, VOSC = 30 mV, F = 1 MHz 0.00 V IRM IR Rd Figure 1. VF VRM Min. Typ. Max. Unit 6 8 10 V 100 nA 187 Ω 153 S21(dB) attenuation measurement 170 14 Figure 2. pF Analog cross talk measurements dB dB 0.00 -10.00 -20.00 -30.00 -15.00 -40.00 -50.00 -60.00 -30.00 -70.00 -80.00 F (Hz) -45.00 100.0k 2/9 1.0M 10.0M F (Hz) -90.00 100.0M 1.0G -100.00 100.0k 1.0M 10.0M 100.0M 1.0G EMIF06-1502M12 Figure 3. Ordering information scheme ESD response to IEC 61000-4-2 Figure 4. (+15 kV air discharge) on one input (Vin) and on one output (Vout) ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input (Vin) and on one output (Vout) Vin C1 = 10 V/d C1 = 10 V/d Vin Vout C2 = 5 V/d 100 ns/d C2 = 5 V/d Vout 100 ns/d Figure 5. Line capacitance versus reverse voltage applied (typical value) CLINE(pF) 24 22 20 18 16 14 12 10 8 6 4 2 0 VLINE(V) 0.0 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Ordering information scheme EMIF yy - xxx z Mx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package Mx = Micro QFN x leads 3/9 Package information 3 EMIF06-1502M12 Package information Table 3. QFN 2.5 x 1.5 package dimensions Dimensions Ref Millimeters MIN TYP MAX MIN TYP MAX A 0.50 0.55 0.60 0.20 0.22 0.24 A1 0.00 0.02 0.05 0.00 0.01 0.02 b 0.15 0.18 0.25 0.06 0.07 0.10 D D2 2.50 1.70 E E2 Footprint 1.80 0.98 1.90 0.30 0.40 0.50 0.12 0.40 k 0.20 L 0.25 Figure 7. 0.71 0.75 0.59 0.16 0.24 0.16 0.08 0.30 0.35 0.10 0.12 Marking Dot: Pin 1 Identification X = Marking YWW= Data code (Y=year WW= week 4/9 0.67 1.50 e Figure 6. inches XY ww 0.14 EMIF06-1502M12 Package information Figure 8. Tape and reel specification f 1.5 +/- 0.1 3.5 +/- 0.05 2.70 8.1 +/- 0.1 0.75 4.00+/-0.1 1.75 +/- 0.1 2.0+/-0.05 XY ww XY ww 1.70 XY ww 4.00 User direction of unreeling In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5/9 Recommendation on PCB assembly EMIF06-1502M12 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil Opening Dimensions: L (Length), W (Width), T (Thickness). L T b) W General Design Rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L× W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. Example: Stencil opening L = 1224 µm, W = 300 µm, Footprint (see Figure 6.) L = 1800 µm, W = 400 µm. c) Stencil opening for leads: Opening to footprint ratio is 90%. Example: Stencil opening L = 570 µm, W = 190 µm, Footprint (see Figure 6.) L = 600 µm, W = 200 µm. 4.2 4.3 6/9 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. Standard tolerance of ± 0.05 mm is recommended. EMIF06-1502M12 4.4 4.5 Recommendation on PCB assembly 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Temp. Peak Temp. Liquidus Temp. time Pre-heating zone Soaking zone Reflow Cool Down zone zone Tin-lead Alloy Lead-Free Alloy [SnPb - SnPbAg] [SnAgCu] ≤2.5° C/s ≤2.5° C/s 120-180° C 140-180° C Parameters Pre-heating rate Soaking temp. Soaking time 80-120 s 80-180 s 210-240° C 245-260° C Reflow time above liquidus 40-80 s 40-140 s Cool down rate < 6° C/s < 6° C/s Peak temperature Note: Minimize air convection currents in the reflow oven to avoid component movement. 7/9 Ordering information 5 6 8/9 EMIF06-1502M12 Ordering information Part number Marking Package Weight Base qty Delivery mode EMIF06-1502M12 E Micro QFN 6 mg 3000 Tape and reel (7”) Revision history Date Revision Changes 12-Dec-2005 1 Initial release. 3-Jul-2006 2 Reformatted to current standard. Changed Figure 1 to show improved results. EMIF06-1502M12 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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