STMICROELECTRONICS ESDALC6V1-1BM2

ESDALC6V1-1BM2
Single line low capacitance Transil™ for ESD protection
Features
■
Single line low capacitance Transil diode
■
Bidirectional ESD protection
■
ESD protection > 30 kV (IEC 61000-4-2 contact
discharge)
■
Breakdown Voltage VBR = 6.1 V min.
■
Low diode capacitance (22 pF typ. at 0 V)
■
Low leakage current: < 100 nA at 3 V
■
Very small PCB area: 0.6 mm2
■
Leadfree package
Benefits
■
High ESD protection level
■
High integration
■
Suitable for high density boards
SOD882
Figure 1.
Functional diagram
I/O1
Complies with the following standards
■
■
IEC 61000-4-2 level 4
– 15 kV (air discharge)
– 8 kV (contact discharge)
I/O2
MIL STD 883G - Method 3015-7: class 3B
– Human body model
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
■
Computers
■
Printers
■
Communication systems
■
Cellular phone handsets and accessories
■
Video equipment
Description
The ESDALC6V1-1BM2 is a bidirectional single
line TVS diode designed to protect the datalines
or other I/O ports against ESD transients.
The device is ideal for applications where both
reduced line capacitance and board space saving
are required.
TM: Transil is a trademark of STMicroelectronics
April 2008
Rev 2
1/10
www.st.com
Characteristics
1
ESDALC6V1-1BM2
Characteristics
Table 1.
Absolute maximum ratings (Tamb = 25 °C)
Symbol
Value
Unit
Peak pulse voltage (IEC 61000-4-2 contact discharge)
± 30
kV
PPP(1)
Peak pulse power dissipation (8/20 µs)
140
W
IPP
Repetitive peak pulse current (8/20 µs)
9
A
Tj
Junction temperature
125
°C
- 55 to + 150
°C
260
°C
- 40 to + 125
°C
VPP(1)
Tstg
TL
TOP
Parameter
Tj initial = Tamb
Storage temperature range
Maximum lead temperature for soldering during 10 s
Operating temperature range
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Table 2.
Electrical characteristics (Tamb = 25 °C)
Symbol
Parameter
VRM
Stand-of voltage
VBR
Breakdown voltage
VCL
Clamping voltage
IRM
Leakage current @ VRM
IPP
Peak pulse current
VF
Forward voltage drop
I
VBR
ESDALC6V1-1BM2
2/10
IR
IRM
V
IRM
IR
VBR @ IR
Order code
VRM
IRM @ VRM
max.
VRM
VBR
Rd
αT
C@0 V
Bias
typ.
max.
typ.
min.
max.
V
V
mA
nA
V
Ω
10-4/°C
pF
6.1
8.0
1
100
3
0.65
2.5
22
ESDALC6V1-1BM2
Figure 2.
Characteristics
Relative variation of peak pulse
power versus initial junction
temperature
Figure 3.
PPP[Tj initial] / PPP[Tj initial=25°C)
Peak pulse power versus
exponential pulse duration
PPP(W)
1.1
1000
Tj initial=25°C
1.0
0.9
0.8
0.7
0.6
100
0.5
0.4
0.3
0.2
0.1
Tj(°C)
tp(µs)
0.0
10
0
25
Figure 4.
50
75
100
125
150
Clamping voltage versus peak
pulse current (typical values)
1
Figure 5.
IPP(A)
10
100
Junction capacitance versus
reverse voltage applied (typical
values)
C(pF)
100.0
25
F=1MHz
VOSC=30mVRMS
Tj=25°C
Tj initial=25°C
20
10.0
15
10
1.0
5
VLINE(V)
VCL(V)
0
0.1
0
Figure 6.
5
10
15
20
25
30
35
40
Relative variation of leakage
current versus junction
temperature (typical values)
0
Figure 7.
1
2
3
4
5
ESD response to IEC 61000-4-2
(+15 kV air discharge) on each
channel
IR[Tj] / IR[Tj=25°C]
100
VR=3V
10
Tj(°C)
1
25
50
75
100
125
150
3/10
Ordering information scheme
Figure 8.
ESD response to IEC 61000-4-2
(-15 kV air discharge) on each
channel
ESDALC6V1-1BM2
Figure 9.
S21 attenuation measurement
result
dB
0.00
-3 dB
- 10.00
- 20.00
- 30.00
F (Hz)
- 40.00
100.0k
2
1.0M
10.0M
100.0M
Ordering information scheme
Figure 10. Ordering information scheme
ESDA LC 6V1 - 1 B M2
ESD Array
Low Capacitance
Breakdown Voltage
6V1 = 6.1 Volts min
Number of lines
Directional
B = Bi-directional
Package
M2 = SOD882
4/10
1.0G
ESDALC6V1-1BM2
3
Package information
Package information
●
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Table 3.
SOD882 dimensions
Dimensions
TOP VIEW
D
Ref.
INDEX AREA
(D/2 x E/2)
A
A1
Inches
Min.
Typ.
Max.
A
0.40
0.47
0.50 0.016 0.019 0.020
A1
0.00
b1
0.20
0.25
0.30 0.008 0.010 0.012
b2
0.20
0.25
0.30 0.008 0.010 0.012
E
SIDE VIEW
Millimeters
Min.
Typ.
0.05 0.000
Max.
0.002
BOTTOM VIEW
b1
b2
INDEX AREA
(D/2 x E/2)
L1
L2
OPTIONAL
PIN # 1 ID
Note:
e
D
1.00
0.039
E
0.60
0.024
e
0.65
0.026
L1
0.45
0.50
0.55 0.018 0.020 0.022
L2
0.45
0.50
0.55 0.018 0.020 0.022
Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin 1
mark is to be used for this purpose.
Figure 11. Footprint (dimensions in mm) Figure 12. Marking
0.55
0.55
0.50
Pin1
P
Pin 2
0.40
5/10
Package information
ESDALC6V1-1BM2
Figure 13. Tape and reel specifications
Ø 1.55 ± 0.05
4.0 ± 0.1
0.20 ± 0.05
3.5 ±- 0.05
1.10 ± 0.05
2.0 ± 0.1
0.55 ± 0.1 (3M)
All dimensions in mm
6/10
User direction of unreeling
P
P
P
0.68 ± 0.05
P
P
P
P
8.0 ± 0.3
0.66 ± 0.05 (C-PAK)
1.75 ± 0.1
2.0 ± 0.05
ESDALC6V1-1BM2
Recommendation on PCB assembly
4
Recommendation on PCB assembly
4.1
Stencil opening design
1.
General recommendation on stencil opening design
a)
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 14. Stencil opening dimensions
L
T
b)
W
General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio = ----- ≥ 1.5
T
L×W
Aspect Area = ---------------------------- ≥ 0.66
2T ( L + W )
2.
Reference design
a)
Stencil opening thickness: 100 µm
b)
Stencil opening for leads: Opening to footprint ratio - between 60% and 65%.
Figure 15. Recommended stencil windows position
Package footprint
Lead footprint on PCB
Lead footprint on PCB
Stencil window
position
0.39 mm
Stencil window
position
0.45 mm
0.05 mm
4.2
0.05 mm
Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed
4.
Solder paste with fine particles: powder particle size is 20-45 µm.
7/10
Recommendation on PCB assembly
4.3
4.4
4.5
ESDALC6V1-1BM2
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 16. ST ECOPACK recommended soldering reflow profile for PCB mounting
Temperature (°C)
260°C max
255°C
220°C
180°C
125 °C
2°C/s recommended
2°C/s recommended
6°C/s max
6°C/s max
3°C/s max
3°C/s max
0
0
1
2
3
4
5
10-30 sec
90 to 150 sec
Note:
8/10
6
7
Time (min)
90 sec max
Minimize air convection currents in the reflow oven to avoid component movement.
ESDALC6V1-1BM2
5
Ordering information
Ordering information
Table 4.
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
ESDALC6V1-1BM2
P(1)
SOD882
0.89 mg
3000
Tape and reel
1. The marking can be rotated by 90° to diferentiate assembly location
6
Revision history
Table 5.
Document revision history
Date
Revision
Changes
11-Jan-2007
1
Initial release.
1-Apr-2007
2
Reformatted to currrent standards. Added Figure 12.: Marking.
Updated Figure 13.: Tape and reel specifications. Added Section 4:
Recommendation on PCB assembly.
9/10
ESDALC6V1-1BM2
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10/10