STE40NK90ZD N-channel 900V - 0.14Ω - 40A ISOTOP Super FREDmesh™ MOSFET General features Type VDSS RDS(on) ID Pw STE40NK90ZD 900V <0.18Ω 40A 600W ■ Extremely high dv/dt capability ■ 100% avalanche tested ■ Very low intrinsic capacitances ■ Very good manufacturing repeatibility ISOTOP Description The SuperFREDMesh™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STE40NK90ZD E40NK90ZD ISOTOP TUBE July 2006 Rev 5 1/13 www.st.com 13 Contents STE40NK90ZD Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Protection features of gate-to-source zener diodes . . . . . . . . . . . . . . . . . . 5 2.2 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 ................................................ 9 STE40NK90ZD 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol VDS VDGR VGS Parameter Value Unit Drain-source voltage (VGS = 0) 900 V Drain-gate voltage (RGS = 20 kΩ) 900 V Gate- source voltage ± 30 V ID Drain current (continuous) at TC = 25°C 40 A ID Drain current (continuous) at TC = 100°C 25 A IDM(1) Drain current (pulsed) 160 A PTOT Total dissipation at TC = 25°C 600 W 5 W/°C 7 KV 8 V/ns 2500 V - 65 to 150 °C Rthj-case Thermal resistance junction-case max 0.2 °C/W Rthj-amb 40 °C/W Max. Value Unit Derating factor VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) dv/dt (2) Peak diode recovery voltage slope VISO Insulation withstand voltage (AC-RMS) from all four terminals to external heatsink Tj Tstg Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area 2. ISD ≤40A, di/dt ≤500 A/µs, VDD ≤V(BR)DSS Table 2. Table 3. Symbol Thermal data Thermal resistance junction-ambient max Avalanche characteristics Parameter IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 40 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 1.2 J 3/13 Electrical characteristics 2 STE40NK90ZD Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = max rating VDS = max rating, TC = 125 °C 10 100 µA µA IGSS Gate-body leakage current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 150µA 3.75 4.5 V RDS(on) Static drain-source on resistance VGS = 10V, ID = 20A 0.14 0.18 Ω Typ. Max. Unit Table 5. Symbol Test conditions Min. Typ. Max. Unit 900 2.5 V Dynamic Parameter Test conditions Min. gfs (1) Forward transconductance Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V, f = 1 MHz, VGS = 0 Coss eq. (2) Equivalent output capacitance VGS = 0V, VDS = 0V to 720V 720 pF td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 450V, ID = 18A RG = 4.7Ω , VGS = 10V (Figure 14) 92 102 450 200 ns ns ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 720 V, ID = 36A, VGS = 10V 590 89 323 VDS = 15V, ID = 20A 35 S pF pF pF 25000 1450 280 826 nC nC nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 4/13 STE40NK90ZD Electrical characteristics Table 6. Symbol Source drain diode Parameter ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD trr Qrr IRRM trr Qrr IRRM Test conditions Min. Typ. ISD = 40A, VGS = 0 Max. Unit 40 160 A A 1.6 V Reverse recovery time ISD = 36A, di/dt = 100A/µs Reverse recovery charge VDD = 50V, Tj = 25°C Reverse recovery current (see Figure 16) 450 3.6 16.2 ns µC A Reverse recovery time ISD = 36A, di/dt = 100A/µs Reverse recovery charge VDD = 50V, Tj = 150°C Reverse recovery current (see Figure 16) 930 12 26 ns µC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Table 7. Symbol BVGSO 2.1 Gate-source zener diode Parameter Test conditions Gate-source breakdown Igs=± 1mA (open voltage drain) Min. Typ. 30 Max. Unit V Protection features of gate-to-source zener diodes The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 5/13 Electrical characteristics STE40NK90ZD 2.2 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/13 STE40NK90ZD Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized BVDSS vs temperature 7/13 Electrical characteristics Figure 13. Avalanche energy vs starting Tj 8/13 STE40NK90ZD STE40NK90ZD 3 Test circuit Test circuit Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped Inductive load test switching and diode recovery times circuit Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform 9/13 Package mechanical data 4 STE40NK90ZD Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/13 STE40NK90ZD Package mechanical data ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 11.8 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.157 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 N 4 O 7.8 0.157 8.2 0.307 0.322 A G B O F E H D N J K C L M 11/13 Revision history 5 STE40NK90ZD Revision history Table 8. 12/13 Revision history Date Revision Changes 24-May-2005 1 First Release 10-Jun-2005 2 Inserted new row in Table 6.: Switching times 28-Sep-2005 3 Complete version 14-Oct-2005 4 Modified Figure 3, Figure 6 12-Jul-2006 5 New template, no content change STE40NK90ZD Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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