STY30NK90Z N-channel 900V - 0.21Ω - 26A - Max247 Zener-protected SuperMESH™ Power MOSFET General features Type VDSS RDS(on) ID pW STY30NK90Z 900V <0.26Ω 28A 500W ■ Extremely high dv/dt capability ■ 100% avalanche tested ■ Gate charge minimized ■ Very low intrinsic capacitances ■ Very good manufacturing repeatibility 2 3 1 Max247 Description The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STY30NK90Z Y30NK90Z Max247 Tube October 2006 Rev 4 1/14 www.st.com 14 Contents STY30NK90Z Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 2 Protection features of gate-to-source zener diodes . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Electrical characteristics (curves) ............................. 7 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 ................................................ 9 STY30NK90Z 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (VGS = 0) 900 V VGS Gate- source voltage ± 30 V ID Drain current (continuous) at TC = 25°C 26 A ID Drain current (continuous) at TC = 100°C 16 A Drain current (pulsed) 104 A Total dissipation at TC = 25°C 450 W Derating Factor 3.57 W/°C Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6000 V 4.5 V/ns -65 to 150 °C IDM (1) Ptot VESD(G-S) dv/dt (2) Tstg Tj Peak diode recovery voltage slope Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area. 2. ISD ≤26A, di/dt ≤400A/µs, VDD ≤V(BR)DSS, Tj ≤TJMAX. Table 2. Thermal data Rthj-case Thermal resistance junction-case max Rthj-amb TJ Table 3. 0.277 °C/W Thermal resistance junction-ambient max 30 °C/W Maximum lead temperature for soldering purpose 300 °C Avalanche characteristics Symbol Parameter Max value Unit IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 26 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 500 mJ Table 4. Symbol BVGSO Gate-source zener diode Parameter Gate-source breakdown voltage Test conditions Igs=± 1mA (open drain) Min. 30 Typ. Max. Unit V 3/14 Electrical ratings 1.1 STY30NK90Z Protection features of gate-to-source zener diodes The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 4/14 STY30NK90Z 2 Electrical characteristics Electrical characteristics (TCASE=25°C unless otherwise specified) Table 5. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage ID = 1mA, VGS =0 IDSS Zero gate voltage drain current (VGS = 0) VDS = max rating VDS = max rating, TC = 125°C 10 100 µA µA IGSS Gate-body leakage current (VDS = 0) VGS = ± 20V ±100 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 150µA 3.75 4.5 V RDS(on) Static drain-source on resistance VGS = 10V, ID = 14A 0.21 0.26 Ω Typ. Max. Unit Table 6. Symbol Test conditions Min. Typ. Max. 900 3 Unit V Dynamic Parameter Test conditions gfs (1) Forward transconductance VDS = 15V, ID = 14A Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V, f = 1MHz, VGS = 0 Coss eq(2) Equivalent output capacitance td(on) tr td(off) tf Qg Qgs Qgd Min. 26 S 12000 852 166 pF pF pF VGS = 0V, VDS = 0V to 720V 377 pF Turn-on delay time Rise time Turn-off delay time Fall time VDD = 450V, ID = 13A RG = 4.7Ω VGS = 10V (see Figure 13) 67 59 250 72 ns ns ns ns Total gate charge Gate-source charge Gate-drain charge VDD = 720V, ID = 26A, VGS = 10V, RG = 4.7Ω (see Figure 14) 350 51 190 490 nC nC nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 5/14 Electrical characteristics Table 7. Symbol STY30NK90Z Source drain diode Parameter ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD trr Qrr IRRM trr Qrr IRRM Test conditions Typ. ISD = 28A, VGS = 0 Max. Unit 28 112 A A 2 V Reverse recovery time ISD = 26A, di/dt = 100A/µs, Reverse recovery charge VDD = 100V, Tj = 25°C Reverse recovery current (see Figure 15) 1 18.9 36.6 µs µC A Reverse recovery time ISD = 26A, di/dt = 100A/µs, Reverse recovery charge VDD = 100V, Tj = 150°C Reverse recovery current (see Figure 15) 1.33 25.2 37.8 µs µC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 6/14 Min. STY30NK90Z Electrical characteristics 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 7/14 Electrical characteristics STY30NK90Z Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics 8/14 Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized breakdown voltage vs temperature STY30NK90Z 3 Test circuit Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit 9/14 Test circuit Figure 17. Unclamped inductive waveform 10/14 STY30NK90Z Figure 18. Switching time waveform STY30NK90Z 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/14 Package mechanical data STY30NK90Z Max247 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. A 4.70 A1 2.20 2.60 b 1.00 1.40 b1 2.00 2.40 b2 3.00 3.40 c 0.40 0.80 D 19.70 20.30 e 5.35 5.55 E 15.30 15.90 L 14.20 15.20 L1 3.70 4.30 MIN. TYP. MAX. 5.30 P025Q 12/14 STY30NK90Z 5 Revision history Revision history Table 8. Revision history Date Revision Changes 16-Jul-2004 1 First release 23-Mar-2004 2 New ECOPACK label inserted 21-Jan-2005 3 Complete document with curves 16-Oct-2006 4 New template, no content change 13/14 STY30NK90Z Please Read Carefully: Information in this document is provided solely in connection with ST products. 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