STW11NK90Z N-channel 900V - 0.82Ω - 9.2A - TO-247 Zener-protected SuperMESH™ Power MOSFET General features Type VDSS RDS(on) ID Pw STW11NK90Z 900V <0.98Ω 9.2A 200W ■ 100% avalanche tested ■ Extremely high dv/dt capability ■ Gate charge minimized ■ Very low intrinsic capacitances ■ Very good manufacturing repeability TO-247 Description The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage Power MOSFETs including revolutionary MDmesh™ products Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STW11NK90Z W11NK90Z TO-247 Tube July 2006 Rev 2 1/12 www.st.com 12 Contents STW11NK90Z Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 5 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 .............................................. 8 STW11NK90Z 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Drain-source voltage (VGS = 0) 900 V Drain-gate voltage (RGS = 20KΩ) 900 V Gate-source voltage ± 30 V ID Drain current (continuous) at TC = 25°C 9.2 A ID Drain current (continuous) at TC=100°C 5.8 A Drain current (pulsed) 36.8 A Total dissipation at TC = 25°C 200 W Derating factor 1.51 W/°C Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6000 V 4.5 V/ns -55 to 150 °C Value Unit 0.66 °C/W Thermal resistance junction-ambient Max 50 °C/W Maximum lead temperature for soldering purpose 300 °C Value Unit VDS VDGR VGS IDM (1) PTOT VESD(G-D) dv/dt (2) TJ Tstg Parameter Peak diode recovery voltage slope Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area 2. ISD < 9.2A, di/dt < 200A/µs, VDD =80%V(BR)DSS Table 2. Thermal resistance Symbol Rthj-case Rthj-a Tl Table 3. Symbol Parameter Thermal resistance junction-case Max Avalanche data Parameter IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) 9.2 A EAS Single pulse avalanche energy (starting Tj=25°C, Id=Iar, Vdd=50V) 400 mJ 3/12 Electrical characteristics 2 STW11NK90Z Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test conditions ID = 1mA, VGS= 0 Min. Typ. Max. 900 Unit V VDS = Max rating, VDS = Max rating @125°C 1 50 µA µA Gate body leakage current (VDS = 0) VGS = ±20V ±10 µA VGS(th) Gate threshold voltage VDS= VGS, ID = 100µA 3.75 4.5 V RDS(on) Static drain-source on resistance VGS= 10V, ID= 4.6A 0.82 0.98 Ω Typ. Max. Unit IDSS Zero gate voltage drain current (VGS = 0) IGSS Table 5. Symbol gfs (1) Ciss Coss Crss Dynamic Parameter Qg Qgd Test conditions Forward transconductance VDS =15V, ID = 4.6A Input capacitance Output capacitance Reverse transfer capacitance VDS =25V, f=1 MHz, VGS=0 Coss eq(2). Equivalent output capacitance Qgs 3 Total gate charge Gate-source charge Gate-drain charge Min. 11 S 3000 240 48 pF pF pF VGS=0, VDS =0V to 720V 83 pF VDD=720V, ID = 9.2A 95 14 49 VGS =10V (see Figure 14) 115 nC nC nC 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS inceases from 0 to 80% VDSS Table 6. Symbol td(on) tr td(off) tf 4/12 Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=450 V, ID= 4.6A, RG=4.7Ω, VGS=10V (see Figure 13) Min. Typ. 30 19 76 50 Max. Unit ns ns ns ns STW11NK90Z Electrical characteristics Table 7. Symbol Source drain diode Max. Unit Source-drain current 9.2 A ISDM(1) Source-drain current (pulsed) 36.8 A VSD(2) Forward on voltage 1.6 V ISD trr Qrr IRRM trr Qrr IRRM Parameter Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current Test conditions Min. Typ. ISD=9.2A, VGS=0 ISD=9.2A, di/dt = 100A/µs, VDD=50V, Tj=25°C (see Figure 18) ISD=9.2A, di/dt = 100A/µs, VDD=50V, Tj=150°C (see Figure 18) 584 6 21 ns µC A 790 8.7 22 ns µC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% Table 8. Symbol BVGSO(1) 1. Gate-source zener diode Parameter Gate-source breakdown voltage Test conditions Igs=±1mA (open drain) Min. Typ. Max. Unit 30 V The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 5/12 Electrical characteristics STW11NK90Z 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Normalized BVDSS vs temperature Figure 6. Static drain-source on resistance 6/12 STW11NK90Z Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Maximum avalanche energy vs temperature 7/12 Test circuits 3 STW11NK90Z Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/12 Figure 18. Switching time waveform STW11NK90Z 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com 9/12 Package mechanical data STW11NK90Z TO-247 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 0.134 b2 3.0 3.40 0.118 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 e 5.45 0.620 0.214 L 14.20 14.80 0.560 L1 3.70 4.30 0.14 L2 18.50 0.582 0.17 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S 10/12 TYP 5.50 0.216 STW11NK90Z 5 Revision history Revision history Table 9. Revision history Date Revision Changes 30-Mar-2006 1 First release 25-Jul-2006 2 Modified value on Avalanche data 11/12 STW11NK90Z Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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