TI BQ29410DCT3R

bq29410, bq29411, bq29412
www.ti.com
SLUS669B – AUGUST 2005 – REVISED DECEMBER 2005
VOLTAGE PROTECTION FOR 2-, 3-, OR 4-CELL Li-Ion BATTERIES
(2nd-LEVEL PROTECTION)
FEATURES
•
•
•
•
•
•
FUNCTION
2-, 3-, or 4-Cell Secondary Protection
Low Power Consumption ICC < 2 µA
[VCELL(ALL) < V(PROTECT)]
Fixed High Accuracy Overvoltage Protection
Threshold
– bq29410 = 4.35 V
– bq29411 = 4.40 V
– bq29412 = 4.45 V
Programmable Delay Time of Detection
High Power Supply Ripple Rejection
Stable During Pulse Charge Operation
Each cell in a multiple-cell pack is compared to an
internal reference voltage. If one cell reaches an
overvoltage condition, the protection sequence
begins. The bq2941x device starts charging an
external capacitor through the CD pin. When the CD
pin voltage reaches 1.2 V, the OUT pin changes from
a low level to a high level.
DCT PACKAGE
(TOP VIEW)
APPLICATIONS
•
OUT
VDD
CD
1
8
2
7
3
6
VC1
VC2
VC3
VC4
4
5
GND
nd
2 -Level Overvoltage Protection in Li-Ion
Battery Packs in:
– Notebook Computers
– Portable Instrumentation
– Portable Equipment
PW PACKAGE
(TOP VIEW)
VC1
VC2
VC3
GND
DESCRIPTION
1
2
3
4
8
7
6
5
OUT
VDD
CD
VC4
The bq2941x is a secondary overvoltage protection
IC for 2-, 3-, or 4-cell lithium-ion battery packs that
incorporates a high-accuracy precision overvoltage
detection circuit. It includes a programmable delay
circuit for overvoltage detection time.
ORDERING INFORMATION (1)
TA
–40°C to 110°C
(1)
(2)
(3)
V(PROTECT) (2)
PACKAGE (3)
MSOP (DCT3)
SYMBOL
4.35 V
bq29410DCT3R
CJG
bq29410PW
PW
bq29410PWR
4.40 V
bq29411DCT3R
CJH
bq29411PW
bq29411PWR
4.45 V
bq29412DCT3R
CJJ
bq29412PW
bq29412PWR
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Contact your local Texas Instruments representative or sales office for alternative overvoltage threshold options.
The "R" suffix indicates tape-and-reel packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
bq29410, bq29411, bq29412
www.ti.com
SLUS669B – AUGUST 2005 – REVISED DECEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1) (2)
UNIT
Supply voltage range
Input voltage range
Output voltage range
VDD
–0.3 V to 28 V
VC1, VC2, VC3, VC4
–0.3 V to 28 V
VC1 TO VC2, VC2 TO VC3, VC3 TO VC4, VC4 TO GND
–0.3 V to 8 V
OUT
–0.3 V to 28 V
CD
–0.3 V to 28 V
Continuous total power dissipation
See Dissipation Rating Table
Storage temperature range, Tstg
–65°C to 150°C
Lead temperature (soldering, 10 s)
(1)
300°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground of this device except the differential voltage of VC1-VC2, VC2-VC3, VC3-VC4, and VC4-GND.
(2)
PACKAGE DISSIPATION RATINGS
PACKAGE
TA = 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DCT
412 mW
3.3 mW/°C
264 mW
214 mW
PW
525 mW
4.2 mW/°C
336 mW
273 mW
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Supply voltage
NOM
MAX
4
25
VC1, VC2, VC3, VC4
0
VDD
VCn – VC (n=1), (n=1, 2, 3), VC4 – GND
0
5
UNIT
V
VI
Input voltage range
td(CD)
Delay time capacitance
0.22
µF
RIN
Voltage-monitor filter resistance
100
1k
Ω
CIN
Voltage-monitor filter capacitance
0.01
0.1
RVD
Supply-voltage filter resistance
CVD
Supply-voltage filter capacitance
TA
Operating ambient temperature range
2
0
µF
1
0.1
–40
V
kΩ
µF
110
°C
bq29410, bq29411, bq29412
www.ti.com
SLUS669B – AUGUST 2005 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, TA = 25°C (unless otherwise noted)
PARAMETER
V(OA)
Overvoltage detection
accuracy
TEST CONDITION
MIN
NOM MAX
TA = 25°C
25
35
TA = –20°C to 85°C
25
50
TA = –40°C to 110°C
4.35
bq29411
4.40
bq29412
4.45
Overvoltage
detection voltage (1)
Vhys
Overvoltage detection
hysteresis (1)
IIN
Input current
V2, V3 , VC4 input ,VDD = VC1
VC1 = VC2 = VC3 = VC4 = 3.5 V (see Figure 1)
tD1
Overvoltage detection delay
time
VDD = VC1, CD = 0.22 µF
1
1.5
I(CD_dis)
CD GND clamp current
VDD = VC1, CD = 1 V
5
12
Supply current
mV
80
bq29410
V(PROTECT)
ICC
UNIT
V
300
VDD = VC1,
VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 3.5 V (see
Figure 1)
2
VDD = VC1,
VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 2.3 V (see
Figure 1)
1.5
mV
0.3
µA
2
S
µA
3
µA
2.5
IOH
High-level output current
OUT = 3 V, VDD = VC1,
VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 4.5 V
–1
mA
IOL
Low-level output current
OUT = 0.1 V, VDD = VC1,
VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 3.5 V
5
µA
(1)
Levels of the overvoltage detection and the hysteresis can be adjusted. For assistance, contact a Texas Instruments sales
representative.
3
bq29410, bq29411, bq29412
www.ti.com
SLUS669B – AUGUST 2005 – REVISED DECEMBER 2005
1 OUT
VC1
VC1 8
2 VDD
VC2
VC2 8
7
3 CD
VC3
VC3 6
4 VC4
GND
GND 5
Figure 1. ICC, IIN Measurement (DCT Package)
Terminal Functions
TERMINAL
4
DESCRIPTION
MSOP
(DCT)
TSSOP
(PW)
NAME
8
1
VC1
Sense voltage input for most positive cell
7
2
VC2
Sense voltage input for second most positive cell
6
3
VC3
Sense voltage input for third most positive cell
5
4
GND
Ground pin
4
5
VC4
Sense voltage input for least positive cell
3
6
CD
An external capacitor is connected to determine the programmable delay time
2
7
VDD
Power supply
1
8
OUT
Output
bq29410, bq29411, bq29412
www.ti.com
SLUS669B – AUGUST 2005 – REVISED DECEMBER 2005
FUNCTIONAL BLOCK DIAGRAM
RVD
CVD
VDD
VC1
RIN
ICD = 0.2 A (TYP)
CIN
RIN
VC2
CIN
VC3
OUT
RIN
CIN
VC4
1.2 V (TYP)
RIN
CIN
GND
CD
C(DELAY)
OVERVOLTAGE PROTECTION
When one of the cell voltages exceeds V(PROTECT), an internal current source begins to charge the capacitor,
C(DELAY), connected to the CD pin. If the voltage at the CD pin, VCD, reaches 1.2 V, the OUT pin is activated and
transitions high. An externally connected NCH FET is activiated and blows the external fuse in the positive
battery rail; see the functional block diagram.
If all cell voltages fall below V(PROTECT) before the voltage at pin CD reaches 1.2 V, the delay time does not run
out. An internal switch clamps the CD pin to GND and discharges the capacitor, C(DELAY), and secures the full
delay time for the next occurring overvoltage event.
Once the pin OUT is activated, it transitions back from high to low after all battery cells reach V(PROTECT)– Vhys.
DELAY TIME CALCULATION
The delay time is calculated as follows:
t d
C
1.2 V C(DELAY)
(DELAY)
I
CD
td ICD
1.2 V
Where I(CD) = CD current source = 0.18 µA
5
bq29410, bq29411, bq29412
www.ti.com
SLUS669B – AUGUST 2005 – REVISED DECEMBER 2005
V(PROTECT)
V(PROTECT) - Vhys
Cell Voltage
(VCn - VC(n-1),
VC4 - GND)
1.2 V
CD
tDELAY
OUT
td = (1.2 V x CDELAY)/ICD
Figure 2. Timing for Overvoltage Sensing
APPLICATION INFORMATION
BATTERY CONNECTIONS
The following diagrams show the DCT package device in different cell configurations.
1 OUT
VC1 8
1 OUT
VC1 8
2 VDD
VC2 8
7
2 VDD
7
VC2 8
3 CD
VC3 6
3 CD
2
VC3 6
4 VC4
GND 5
4 VC4
2
GND 5
Figure 3. 4-Series Cell Configuration
6
Figure 4. 3-Series Cell Configuration
(Connect together VC1 and VC2)
bq29410, bq29411, bq29412
www.ti.com
SLUS669B – AUGUST 2005 – REVISED DECEMBER 2005
APPLICATION INFORMATION (continued)
1 OUT
VC1 8
2 VDD
VC2 77
36 CD
VC3 6
4 VC4
GND 5
Figure 5. 2-Series Cell Configuration
CELL CONNECTIONS
To prevent incorrect output activation, the following connection sequences must be used.
4-Series Cell Configuration
• VC1(=VDD) → VC2 → VC3 → VC4 → GND or
• GND → VC4 → VC3 → VC2 → VC1(=VDD)
3-Series Cell Configuration
• VC1(=VC2=VDD) → VC3 → VC4 → GND or
• GND → VC4 → VC3 → VC1(=VC2=VDD)
2-Series Cell Configuration
• VC1(=VC2=VC3=VDD) → VC4 → GND or
• GND → VC4 → VC1(=VC2=VC3=VDD)
7
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
BQ29412DCT3R
ACTIVE
SM8
DCT
Pins Package Eco Plan (2)
Qty
8
3000
Pb-Free
(RoHS)
Lead/Ball Finish
CU SNBI
MSL Peak Temp (3)
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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