STMICROELECTRONICS STL17N3LLH6

STL17N3LLH6
N-channel 30 V, 0.0038 Ω, 17 A PowerFLAT™(3.3x3.3)
STripFET™ VI DeepGATE™ Power MOSFET
Features
Order code
VDSS
RDS(on)
max.
ID
STL17N3LLH6
30 V
0.0045 Ω
17 A (1)
1. The value is rated according Rthj-pcb
■
RDS(on) * Qg industry benchmark
■
Extremely low on-resistance RDS(on)
■
High avalanche ruggedness
■
Low gate drive power losses
■
Very low switching gate charge
PowerFLAT™ (3.3 x 3.3)
Application
Figure 1.
Switching applications
Pin-out configuration
1
2
3
4
S
S
S
G
Description
This product utilizes the 6th generation of design
rules of ST’s proprietary STripFET™ technology,
with a new gate structure. The resulting Power
MOSFET exhibits the lowest RDS(on) in a standard
package, that makes it suitable for the most
demanding DC-DC converter applications, where
high power density has to be achieved.
D
D
D
D
8
7
6
5
BOTTOM VIEW
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL17N3LLH6
17N3L
PowerFLAT™ (3.3 x 3.3)
Tape and reel
November 2010
Doc ID 15535 Rev 3
1/13
www.st.com
13
Contents
STL17N3LLH6
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
.............................................. 8
Doc ID 15535 Rev 3
STL17N3LLH6
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
30
V
± 20
V
Drain current (continuous) at TC = 25 °C
17
A
Drain current (continuous) at TC = 100 °C
11
A
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
ID
(1)
ID (1)
(2)
Drain current (pulsed)
68
A
PTOT
(3)
Total dissipation at TC = 25 °C
50
W
PTOT
(1)
Total dissipation at TC = 25 °C
2
W
0.03
W/°C
-55 to 150
°C
IDM
Derating factor
TJ
Operating junction temperature
Storage temperature
Tstg
1. The value is rated according Rthj-pcb
2. Pulse width limited by safe operating area
3. The value is rated according Rthj-c
Table 3.
Thermal resistance
Symbol
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case (drain) (steady state)
2.5
°C/W
(1)
Thermal resistance junction-pcb
42.8
°C/W
Rthj-pcb(2)
Thermal resistance junction-pcb
63.5
°C/W
Rthj-pcb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
2. Steady state
Doc ID 15535 Rev 3
3/13
Electrical characteristics
2
STL17N3LLH6
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4.
Symbol
Parameter
Test conditions
Drain-source breakdown
voltage
ID = 250 µA, VGS = 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating @125 °C
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS = 10 V, ID = 8.5 A
VGS = 4.5 V, ID = 8.5 A
V(BR)DSS
Table 5.
Symbol
Min.
Typ.
Max.
30
Unit
V
1
10
µA
µA
±100
nA
1
V
Ω
Ω
0.0038
0.0057
0.0045
0.0073
Min.
Typ.
Max.
Unit
-
pF
pF
pF
Dynamic
Parameter
Test conditions
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f=1 MHz,
VGS=0
-
1690
290
176
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 15 V, ID = 17 A
VGS = 4.5 V
(see Figure 14)
-
17
8
6
-
nC
nC
nC
Gate input resistance
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
-
1.7
-
Ω
RG
Table 6.
Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
4/13
On/off states
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
VDD= 15V, ID = 8.5A,
RG = 4.7Ω, VGS = 10V
(see Figure 13)
Doc ID 15535 Rev 3
Min.
Typ.
-
9.5
30
37
12
Max.
Unit
-
ns
ns
ns
ns
STL17N3LLH6
Electrical characteristics
Table 7.
Symbol
ISD
Source drain diode
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
17
A
ISDM(1)
Source-drain current (pulsed)
-
68
A
VSD(2)
Forward on voltage
ISD = 17 A, VGS = 0
-
1.1
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 17 A,
di/dt = 100 A/µs,
VDD= 25 V
-
trr
Qrr
IRRM
24
16.8
1.4
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Doc ID 15535 Rev 3
5/13
Electrical characteristics
STL17N3LLH6
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Thermal impedance
AM08217v1
ID
(A)
100
Figure 3.
Zth_powerflat_3.3x3.3
K
δ=0.5
Tj=150°C
Tc=25°C
Single pulse
a is
are n)
this DS(o
n in ax R
tio
m
era d by
p
O
ite
Lim
0.2
0.1
-1
10
0.05
10
10ms
0.02
1
100ms
1s
-2
0.01
10
0.1
Single pulse
-3
0.01
0.1
Figure 4.
10
1
10 -3
10
VDS(V)
Output characteristics
Figure 5.
AM08218v1
ID
(A)
VGS=10V
-2
0
-1
10
2
1
10
10
tp (s)
10
10
Transfer characteristics
AM08219v1
ID
(A)
6V
250
200
5V
200
150
150
4V
100
100
50
50
3V
0
0
Figure 6.
1
2
3
4
5
Normalized BVDSS vs temperature
AM08220v1
BVDSS
(norm)
1.06
1.04
0
0
VDS(V)
Figure 7.
1
2
3
4
VGS(V)
5
Static drain-source on resistance
AM08221v1
RDS(on)
(Ω)
4.8
ID=1mA
VGS=10V
4.6
1.02
1.00
4.4
0.98
4.2
0.96
4.0
0.94
0.92
-50 -25
6/13
0
25
50
75 100 125
TJ(°C)
3.8
0
Doc ID 15535 Rev 3
5
10
15
20
25
30
35
ID(A)
STL17N3LLH6
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM08222v1
VGS
(V)
VDD=15V
ID=17A
12
Capacitance variations
AM08223v1
C
(pF)
2500
10
2000
Ciss
8
1500
6
1000
4
Coss
500
2
0
0
20
10
30
40
0
0
50 Qg(nC)
Figure 10. Normalized gate threshold voltage
vs temperature
AM08224v1
VGS(th)
(norm)
Crss
20
10
VDS(V)
Figure 11. Normalized on resistance vs
temperature
AM08225v1
RDS(on)
(norm)
1.8
1.2
1.6
1.4
1.0
1.2
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
-50 -25
0.2
0
-50 -25
0
25
50
75 100
TJ(°C)
0
25
50
75 100
TJ(°C)
Figure 12. Source-drain diode forward
characteristics
AM08226v1
VSD
(V)
TJ=-55°C
1.0
0.9
0.8
TJ=25°C
0.7
0.6
TJ=150°C
0.5
0.4
0
10
20
30
40
50
60
70
ISD(A)
Doc ID 15535 Rev 3
7/13
Test circuits
3
STL17N3LLH6
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/13
0
Doc ID 15535 Rev 3
10%
AM01473v1
STL17N3LLH6
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 8.
Package dimensions
mm.
Dim.
A
Min.
Typ
Max.
0.80
0.90
1.00
0.02
0.05
0.30
0.35
A1
b
0.25
D
D2
3.30
2.50
2.65
e
0.65
E
3.30
2.75
E2
1.76
1.91
2.01
L
0.30
0.40
0.50
Doc ID 15535 Rev 3
9/13
Package mechanical data
STL17N3LLH6
Figure 19. Package drawing
10/13
Doc ID 15535 Rev 3
STL17N3LLH6
Package mechanical data
Figure 20. Recommended footprint (dimensions in mm)
AM03834v1
Doc ID 15535 Rev 3
11/13
Revision history
5
STL17N3LLH6
Revision history
Table 9.
12/13
Document revision history
Date
Revision
Changes
24-Mar-2009
1
First release.
06-Jul-2010
2
Updated Table 4: On/off states.
10-Nov-2010
3
Document status promoted from preliminary data to datasheet.
Doc ID 15535 Rev 3
STL17N3LLH6
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Doc ID 15535 Rev 3
13/13