TDA7348 Digitally controlled audio processor Features ● Input multiplexer – Three stereo and one mono inputs – Selectable input gain for optimal adaptation to different sources ● Volume control in 0.3db steps including gain up to 20dB ● Zero crossing mute and direct mute ● Pause detector with programmable threshold ● Soft mute controlled by software or hardware PIN ● Bass and treble control ● Four speaker attenuators – – ● Four independent speakers control in 1.25dB steps for balance and fader facilities Independent mute function All functions programmable via serial I2C bus SO-28 instead of standard bipolar multipliers, very low distortion and very low noise are obtained Several new features like softmute, zero-crossing mute and pause detector are implemented. The Soft Mute function can be activated in two ways, either via the serial bus (bit D0, Mute Byte), or directly on pin 22 through an I/O line of the microcontroller Description The TDA7348 is an upgrade of the TDA7318 audioprocessor. Thanks to the used BIPOLAR/CMOS technology, very low distortion, low noise and DC-stepping are obtained. Due to a highly linear signal processing, using CMOS-switching techniques Very low DC stepping is obtained by use of a BICMOS technology. Order codes Part number Package Packing TDA7348D SO-28 Tube SO-28 Tape and reel SO-28 Tube SO-28 Tape and reel TDA7348D013TR E-TDA7348D (1) E-TDA7348D013TR (1) 1. This device is Pb-free Ecopack , see Chapter 5 Package information. January 2007 Rev 3 1/20 www.st.com 1 Contents TDA7348 Contents 1 Block diagram and PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 I2C BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 3.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 10 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 TDA7348 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3/20 List of figures TDA7348 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. 4/20 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data validity on the I2C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SO-28 mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TDA7348 Block diagram and PIN connections 1 Block diagram and PIN connections Figure 1. Block diagram R2 4.7K C10 2.2μF 3x 1μF C1 LEFT INPUTS C2 OUT(L) IN(L) 17 16 C14 100nF SM BOUT(L) BIN(L) 19 18 22 C16 2.7nF TREBLE(L) C15 100nF 4 SPKR ATT RB L1 14 26 L1 L2 13 L2 L3 12 L3 C3 MUTE ZERO CROSS + MUTE VOL 1, 2 BASS TREBLE SPKR ATT L4 24 MUTE C4 3x 1μF C7 RIGHT INPUTS C6 28 INPUT SELECTOR + GAIN 11 SOFT MUTE SERIAL BUS DECODER + LATCHES 8 R2 9 R1 10 25 R3 ZERO CROSS + MUTE R2 VOL 1, 2 BASS MUTE TREBLE 23 RB 2 SCL BUS SDA OUT RIGHT FRONT SPKR ATT R1 C5 VS 27 OUT LEFT REAR SPKR ATT R4 R3 OUT LEFT FRONT SUPPLY MUTE 3 1 7 6 15 AGND CREF OUT(R) IN(R) CSM 21 20 BOUT(R) OUT RIGHT REAR 5 BIN(R) TREBLE(R) D93AU100B C8 CSM 47nF 10μF C9 2.2μF Figure 2. C11 100nF C12 100nF C13 2.7nF R1 4.7K PIN connections CREF 1 28 SCL VS 2 27 SDA GND 3 26 OUT LF L 4 25 OUT RF R 5 24 OUT LR IN(R) 6 23 OUT RR OUT(R) 7 22 SM IN R3 8 21 BOUT(R) IN R2 9 20 BIN(R) IN R1 10 19 BOUT(L) AM MONO 11 18 BIN(L) IN L3 12 17 OUT(L) IN L2 13 16 IN(L) IN L1 14 15 CSM TREBLE BUS INPUTS BASS D94AU099 5/20 Electrical characteristics 2 TDA7348 Electrical characteristics Table 1. Electrical characteristics VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified. Symbol Parameter Test Condition Min. Typ. Max. Unit 70 100 130 KΩ 2.1 2.6 VRMS 100 dB Input selector RI VCL Input resistance Clipping level d ≤ 0.3% SI Input separation 80 RL Output load resistance 2 KΩ GI MIN Minimum input gain -0.75 0.75 dB GI MAX Maximum input gain 10.25 11.25 12.25 dB Step resolution 2.75 dB Gstep eN VDC Input noise 0 3.75 20Hz to 20 KHz unweighted 2.3 Adiacent gain steps 1.5 4.75 μV 10 mV DC steps GIMIN to GIMAX 3 mV KΩ Volume control (1 + 2) RI Input resistance 35 50 GMAX Maximum gain 18.75 20 AMAX Maximum attenuation ASTEPC Step resolution coarse attenuation 0.5 1.25 2.0 dB ASTEPF Step resolution fine attenuation 0.11 0.31 0.51 dB G = 20 to -20dB -1.25 0 1.25 dB EA Attenuation set error G = -20 to -58dB -3 2 dB Et Tracking error 2 dB 0 3 mV From 0dB to AMAX 0.5 5 mV WIN = 11 20 mV WIN = 10 40 mV WIN = 01 80 mV WIN = 00 160 mV 100 dB 78.45 Adiacent attenuation steps VDC 21.25 -3 dB dB DC steps Zero crossing mute VTH AMUTE VDC 6/20 Zero crossing threshold Mute attenuation DC step 80 0dB to Mute 0 3 mV TDA7348 Electrical characteristics Table 1. Electrical characteristics (continued) VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified. Symbol Parameter Test Condition Min. Typ. Max. Unit 45 60 CCSM = 22nF; 0 to -20dB; I = IMAX 0.7 1 1.7 ms CCSM = 22nF; 0 to -20dB; I = IMIN 20 35 55 ms VCSM = 0V; I = IMAX 25 50 75 μA Soft mute AMUTE Mute attenuation TDON ON delay time dB TDOFF OFF delay time VTHSM Soft mute threshold 1.5 2.5 3.5 V RINT Pull-up resistor (pin 22) 35 50 65 KΩ VSMH (pin 22) level high VSML (pin 22) level low VCSM = 0V; I = IMIN Soft Mute active μA 1 3.5 V 1 V Bass control BBOOST Max bass boost 15 18 20 dB BCUT Max bass cut -8.5 -10 -11.5 dB Astep Step resolution 1 2 3 dB Internal feedback resistance 45 65 85 KΩ ±13 ±14 ±15 dB 1 2 3 dB Control range 35 37.5 40 dB Step resolution 0.5 1.25 2.0 dB 80 100 Rg Treble control CRANGE Astep Control range Step resolution Speaker attenuators CRANGE Astep AMUTE Output mute attenuation EA Attenuation set error VDC DC steps Data word = XXX11111 Adjacent attenuation steps 0 dB 1.25 dB 3 mV Audio output Vclip Clipping level RL Output load resistance RO Output impedance VDC DC voltage level d = 0.3% 2.1 2.6 Vrms 2 KΩ 30 100 W 3.5 3.8 4.1 V 6 9 10.2 V General VCC Supply voltage 7/20 Electrical characteristics Table 1. Electrical characteristics (continued) VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified. Symbol ICC TDA7348 Parameter Test Condition Min. Typ. Max. Unit 5 10 15 mA 60 80 dB B = 20 to 20kHz "A" weighted 65 dB Output Muted (B = 20 to 20kHz flat) 2.5 μV All Gains 0dB (B = 20 to 20kHz flat) 5 15 μV AV= 0 to -20dB 0 1 dB AV= -20 to -60dB 0 2 dB Supply current f = 1KHz PSRR eNO Power supply rejection ratio Output noise Et Total tracking error S/N Signal to noise ratio SC Channel separation d All Gains = 0dB; VO= 1Vrms 80 Vin = 1V Distortion 106 dB 100 dB 0.01 0.08 % 1 V Bus inputs VIL Input low voltage VlN Input high voltage IlN Input current VIN = 0.4V VO Output voltage SDA acknowledge IO = 1.6mA 3 Table 2. Absolute maximum ratings Symbol Parameter VS V -5 0.4 Operating supply voltage μA 0.8 V Value Unit 10.5 V Tamb Operating ambient temperature -40 to 85 °C Tstg Storage temperature range -55 to 150 °C SO28 Unit 65 °C/W Table 3. Thermal data Symbol Parameter Rth j-amb Thermal Resistance Junction pins Table 4. Quick reference data Symbol 8/20 5 Parameter VS Supply voltage VCL Max. input signal handling Min. Typ. Max. Unit 6 9 10.2 V 2.1 2.6 THD Total harmonic distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to noise ratio 106 Vrms 0.08 % dB TDA7348 Electrical characteristics Table 4. Quick reference data (continued) Symbol SC Parameter Min. Channel separation f = 1KHz Typ. Max. 100 Unit dB 78.45 20 dB Treble control 2dB step -14 +14 dB Bass control 2dB step -10 +18 dB 38.75 0 dB 0 11.2 5 dB Volume control Fader and balance control 1.25dB step Input gain 3.75dB step Mute attenuation 100 dB 9/20 I2C BUS interface 3 TDA7348 I2C BUS interface Data transmission from microprocessor to the TDA7348 and vice-versa takes place through the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to the positive supply voltage must be externally connected). 3.1 Data validity As shown in Figure 3., the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and stop conditions As shown in Figure 4. a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. 3.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 5.). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without acknowledgement The microprocessor can use a simpler transmission, if it avoids detection of the acknowledgement from the audio processor. It simply waits one clock pulse without checking the slave acknowledgment, and sends the new data. This approach of course is less protected from errors, increases the possibility of interference, and decreases the immunity to noise. 10/20 I2C BUS interface TDA7348 Figure 3. Data validity on the I2C BUS SDA SCL DATA LINE STABLE, DATA VALID Figure 4. CHANGE DATA ALLOWED D99AU1031 Timing diagram of I2C BUS SCL I2CBUS SDA D99AU1032 START Figure 5. STOP Acknowledge on the I2C BUS SCL 1 2 3 7 8 9 SDA MSB START D99AU1033 ACKNOWLEDGMENT FROM RECEIVER 11/20 Software specification TDA7348 4 Software specification 4.1 Interface protocol The interface protocol comprises: ● A start condition (s) ● A chip address byte, (the LSB bit determines read/write transmission) ● A subaddress byte. ● A sequence of data (N-bytes + acknowledge) ● A stop condition (P) Chip address Subaddress MSB S 1 LSB Data 1 to data n MSB 0 0 0 1 0 0 R/W ACK X LSB X X MSB I A3 A2 A1 A0 ACK LSB DATA ACK P ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used Max clock speed 500kbits/s 4.2 Auto increment If bit I in the subaddress byte is set to "1", the auto-increment of the subaddress is enabled Table 5. Subaddress (receive mode) MSB X 12/20 LSB X X I Function A3 A2 A1 A0 0 0 0 0 Input selector 0 0 0 1 Loudness 0 0 1 0 Volume 0 0 1 1 Bass, Treble 0 1 0 0 Speaker attenuator LF 0 1 0 1 Speaker attenuator LR 0 1 1 0 Speaker attenuator RF 0 1 1 1 Speaker attenuator RR 1 0 0 0 Mute TDA7348 4.3 Software specification Transmitted data Table 6. Send mode MSB LSB X X X X X SM ZM X ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address. 4.4 Data byte specification X = not relevant; set to "1" during testing Table 7. Input Selector MSB LSB Function D7 D6 D5 X X X D4 D3 D2 D1 D0 1 0 0 0 not used X 1 0 0 1 IN 2 X X 1 0 1 0 IN 1 X X 1 0 1 1 AM mono X X 1 1 0 0 not used X X 1 1 0 1 IN 3 X X 1 1 1 0 not allowed X X 1 1 1 1 not allowed X X 1 0 0 11.25dB gain X X 1 0 1 7.5dB gain X X 1 1 0 3.75dB gain X X 1 1 1 0dB gain For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1 Table 8. Loudness MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 X X X 1 0 0 0 0 0dB X X X 1 0 0 0 1 -1.25dB X X X 1 0 0 1 0 -2.5dB 13/20 Software specification Table 8. TDA7348 Loudness (continued) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 X X X 1 0 0 1 1 -3.75dB X X X 1 0 1 0 0 -5dB X X X 1 0 1 0 1 -6.25dB X X X 1 0 1 1 0 -7.5dB X X X 1 0 1 1 1 -8.75dB X X X 1 1 0 0 0 -10dB X X X 1 1 0 0 1 -11.25dB X X X 1 1 0 1 0 -12.5dB X X X 1 1 0 1 1 -13.75dB X X X 1 1 1 0 0 -15dB X X X 1 1 1 0 1 -16.25dB X X X 1 1 1 1 0 -17.5dB X X X 1 1 1 1 1 -18.75dB For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0 Table 9. Mute MSB LSB Function D7 D6 D5 D4 D3 D2 1 D0 1 Soft mute on 0 1 Soft mute with fast slope (I = IMAX) 1 1 Soft mute with slow slope (I = IMIN) Direct mute 0 1 Zero crossing mute on 0 0 Zero crossing mute off (delayed until next zerocrossing) 1 14/20 D1 Zero crossing mute and pause detector reset 0 0 160mV ZC window threshold (WIN = 00) 0 1 80mV ZC window threshold (WIN = 01) 1 0 40mV ZC window threshold (WIN = 10) 1 1 20mV ZC window threshold (WIN = 11) 0 Non-symmetrical Bass Cut 1 Symmetrical Bass Cut TDA7348 Software specification An additional direct mute function is included in the speaker attenuators. Note: Bass cut for very low frequencies should not be used at +16 & +18dB bass boost (DC gain) Table 10. Speaker attenuators MSB LSB Speaker attenuator LF, LR, RF, RR D7 D6 D5 D4 D3 D2 D1 D0 1.25dB step X X X 0 0 0 0dB X X X 0 0 1 -1.25dB X X X 0 1 0 -2.5dB X X X 0 1 1 -3.75dB X X X 1 0 0 -5dB X X X 1 0 1 -6.25dB X X X 1 1 0 -7.5dB X X X 1 1 1 -8.75dB 10dB step X X X 0 0 0dB X X X 0 1 -10dB X X X 1 0 -20dB X X X 1 1 -30dB X X X 1 1 1 1 1 Speaker mute For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0 Table 11. Bass/Treble MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 Treble step 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 15/20 Software specification Table 11. TDA7348 Bass/Treble (continued) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB BASS STEPS 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 -0dB 1 1 1 1 -0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB 0 0 0 1 146B 0 0 0 0 18dB For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1 16/20 TDA7348 Software specification Table 12. Volume MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 0.31dB Fine attenuation steps 0 0 0dB 0 1 -0.31dB 1 0 -0.62dB 1 1 -0.94dB 1.25dB Coarse attenuation steps 0 0 0 0dB 0 0 1 -1.25dB 0 1 0 -2.5dB 0 1 1 -3.75dB 1 0 0 -5dB 1 0 1 -6.25dB 1 1 0 -7.5dB 1 1 1 -8.75dB 10dB Gain / attenuation steps 0 0 0 20dB 0 0 1 10dB 0 1 0 0dB 0 1 1 -10dB 1 0 0 -20dB 1 0 1 -30dB 1 1 0 -40dB 1 1 1 -50dB For example to select -47.81dB volume the data byte is: 1 1 0 1 1 0 0 1 Power on RESET: All bytes set to 1 1 1 1 1 1 1 0 17/20 Package information 5 TDA7348 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. SO-28 mechanical, data and package dimensions mm DIM. MIN. TYP. A MAX. MIN. TYP. 2.65 MAX. 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S OUTLINE AND MECHANICAL DATA 0.104 a1 C 18/20 inch 8 ° (max.) SO-28 TDA7348 6 Revision history Revision history Table 13. Document revision history Date Revision Changes 14-Jan-2004 1 Initial release. 21-Jun-2004 2 Technical migration from ST-PRESS to EDOCS DMS 26-Jan-2007 3 DIP28 package removed, block diagram changed, layout modified. 19/20 TDA7348 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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