STMICROELECTRONICS TS922AIN

TS922
Rail-to-rail high output current dual operational amplifier
Features
■
Rail-to-rail input and output
■
Low noise: 9nV/√Hz
■
Low distortion
■
High output current: 80mA
(able to drive 32Ω loads)
■
High-speed: 4MHz, 1V/μs
■
Operating from 2.7V to 12V
■
Low input offset voltage: 900μV max (TS922A)
■
ESD Internal protection: 2kV
■
Latch-up immunity
■
Macromodel included in this specification
■
Dual version available in flip-chip package
J
(Flip-chip)
N
DIP8
(Plastic package)
D
SO-8
(Plastic micropackage)
Description
The TS922 is a rail-to-rail dual BiCMOS
operational amplifier optimized and fully specified
for 3V and 5V operation.
The device’s high output current allows low-load
impedances to be driven.
P
TSSOP8
(Thin shrink small outline package)
Very low noise, low distortion, low offset and a
high output current capability make this device an
excellent choice for high quality, low voltage or
battery operated audio systems.
The device is stable for capacitive loads up to
500pF.
January 2007
Applications
■
Headphone amplifier
■
Sound cards, multimedia systems
■
Line driver, actuator driver
■
Servo amplifier
■
Mobile phone and portable equipment
■
Instrumentation with low noise as key factor
■
Piezoelectric speaker driver
Rev 6
1/21
www.st.com
21
Contents
TS922
Contents
1
Pin diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
4.1
Important note concerning this macromodel . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Electrical characteristics from macromodelization . . . . . . . . . . . . . . . . . . 11
4.3
Macromodel code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Flip-chip package (8 bumps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
DIP8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
SO-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4
TSSOP8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
TS922
1
Pin diagrams
Pin diagrams
Figure 1.
Figure 2.
Pin connections (top view)
Output 1
1
Inverting Input 1
2
-
Non-inverting Input 1
3
+
VCC
4
8 VCC +
7 Output 2
-
6 Inverting Input 2
+
5 Non-inverting Input 2
Pin-out for flip-chip package (top view)
OUT2
-IN2
+IN2
+
GND
VCC+
+
OUT1
-IN1
+IN1
3/21
Absolute maximum ratings and operating conditions
2
TS922
Absolute maximum ratings and operating conditions
Table 1.
Absolute maximum ratings (AMR)
Symbol
VCC
Vid
Parameter
Value
Unit
14
V
±1
V
VDD-0.3 to VCC+0.3
V
-65 to +150
°C
Supply voltage (1)
Differential input voltage
(2)
(3)
Vin
Input voltage
Tstg
Storage temperature
(4)
Rthja
Thermal resistance junction to ambient
SO8
TSSOP8
DIP8
Flip-chip
Rthjc
Thermal resistance junction to case
SO8
TSSOP8
DIP8
40
37
41
Maximum junction temperature
150
°C
HBM: human body model(5)
MM: machine model(6)
CDM: charged device model
2
100
1.5
kV
Tj
ESD
Output short circuit duration
125
120
85
90
°C/W
°C/W
V
kV
(7)
see note
Latch-up immunity
200
mA
Soldering temperature (10sec), leaded version
Soldering temperature (10sec), unleaded version
250
260
°C
1. All voltage values, except differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. If
Vid > ±1V, the maximum input current must not exceed ±1mA. In this case (Vid > ±1V) an input series
resistor must be added to limit input current.
3. Do not exceed 14V.
4. Rth are typical values.
5. Human body model, 100pF discharged through a 1.5kΩ resistor into pin of device.
6. Machine model ESD, a 200pF cap is charged to the specified voltage, then discharged directly into the IC
with no external series resistor (internal resistor < 5Ω), into pin of device.
7. There is no short-circuit protection inside the device: short-circuits from the output to VCC can cause
excessive heating. The maximum output current is approximately 80mA, independent of the magnitude of
VCC. Destructive dissipation can result from simultaneous short-circuits on all amplifiers.
Table 2.
Operating conditions
Symbol
4/21
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
Unit
2.7 to 12
V
VDD -0.2 to VCC +0.2
V
-40 to +125
°C
TS922
Electrical characteristics
3
Electrical characteristics
Table 3.
Electrical characteristics measured at VCC = +3V, VDD = 0V, Vicm = VCC/2,
Tamb = 25°C, and RL connected to VCC/2 (unless otherwise specified)
Symbol
Vio
DVio
Parameter
Input offset voltage
Test conditions
Min.
Typ.
Max.
TS922, T=25°C
TS922A, T=25°C
TS922IJ (flip-chip), T=25°C
3
0.9
1.5
Tmin ≤ Tamb ≤ Tmax TS922
Tmin ≤ Tamb ≤ Tmax TS922A
Tmin ≤ Tamb ≤ Tmax TS922IJ (flip-chip)
5
1.8
2.5
Unit
mV
Input offset voltage drift
μV/°C
2
Iio
Input offset current
Vout = VCC/2
T=25°C
Tmin ≤ Tamb ≤ Tmax
1
30
30
nA
Iib
Input bias current
Vout = VCC/2
T=25°C
Tmin ≤ Tamb ≤ Tmax
15
100
100
nA
VOH
High level output voltage
RL= 10k, T=25°C
Tmin ≤ Tamb ≤ Tmax
2.90
2.90
V
RL = 600Ω, T=25°C
Tmin ≤ Tamb ≤ Tmax
2.87
2.87
V
RL = 32Ω, T=25°C
VOL
Low level output voltage
2.63
RL= 10k, T=25°C
Tmin ≤ Tamb ≤ Tmax
50
50
mV
RL = 600Ω, T=25°C
Tmin ≤ Tamb ≤ Tmax
100
100
mV
RL = 32Ω, T=25°C
Avd
Large signal voltage gain
(Vout = 2Vp-p)
V
180
RL= 10k, T=25°C
RL= 10k, Tmin ≤ Tamb ≤ Tmax
70
RL = 600Ω, T=25°C
RL = 600Ω, Tmin ≤ Tamb ≤ Tmax
15
mV
200
V/mV
35
RL = 32Ω, T=25°C
16
Total supply current
No load, Vout = VCC/2,
T=25°C
Tmin ≤ Tamb ≤ Tmax
2
GBP
Gain bandwidth product
RL = 600Ω
4
CMR
Common mode rejection ratio
T=25°C
Tmin ≤ Tamb ≤ Tmax
60
56
80
SVR
Supply voltage rejection ratio
VCC = 2.7 to 3.3V
T=25°C
Tmin ≤ Tamb ≤ Tmax
60
60
85
Output short circuit current
50
80
mA
SR
Slew rate
0.7
1.3
V/μs
φm
Phase margin at unit gain
68
Degrees
ICC
Io
RL = 600Ω, CL =100pF
3
3.2
mA
MHz
dB
dB
5/21
Electrical characteristics
Table 3.
Symbol
TS922
Electrical characteristics measured at VCC = +3V, VDD = 0V, Vicm = VCC/2,
Tamb = 25°C, and RL connected to VCC/2 (unless otherwise specified) (continued)
Parameter
Test conditions
Gm
Gain margin
en
Equivalent input noise voltage f = 1kHz
THD
Cs
6/21
Total harmonic distortion
Channel separation
RL = 600Ω, CL =100pF
Vout= 2Vp-p, F= 1kHz, Av= 1, RL=600Ω
Min.
Typ.
Max.
Unit
12
dB
9
nV
-----------Hz
0.005
%
120
dB
TS922
Table 4.
Symbol
Vio
DVio
Electrical characteristics
Electrical characteristics measured at VCC = 5V, VDD = 0V, Vicm = Vcc/2,
Tamb = 25°C, and RL connected to Vcc/2 (unless otherwise specified)
Parameter
Input offset voltage
Conditions
Min.
Typ.
Max.
TS922, T=25°C
TS922A, T=25°C
TS922IJ (flip-chip), T=25°C
3
0.9
1.5
Tmin ≤ Tamb ≤ Tmax TS922
Tmin ≤ Tamb ≤ Tmax TS922A
Tmin ≤ Tamb ≤ Tmax TS922IJ (flip-chip)
5
1.8
2.5
Unit
mV
Input offset voltage drift
μV/°C
2
Iio
Input offset current
Vout = VCC/2
T=25°C
Tmin ≤ Tamb ≤ Tmax
1
30
30
nA
Iib
Input bias current
Vout = VCC/2
T=25°C
Tmin ≤ Tamb ≤ Tmax
15
100
100
nA
VOH
High level output voltage
RL= 10k, T=25°C
Tmin ≤ Tamb ≤ Tmax
4.9
4.9
RL = 600Ω, T=25°C
Tmin ≤ Tamb ≤ Tmax
4.85
4.85
RL = 32Ω, T=25°C
VOL
Low level output voltage
4.4
RL= 10k, T=25°C
Tmin ≤ Tamb ≤ Tmax
50
50
RL = 600Ω, T=25°C
Tmin ≤ Tamb ≤ Tmax
120
120
RL = 32Ω, T=25°C
Avd
Large signal voltage gain
(Vout = 2Vp-p)
V
mV
300
RL= 10k, T=25°C
RL= 10k, Tmin ≤ Tamb ≤ Tmax
70
200
RL = 600Ω, T=25°C
RL = 600Ω, Tmin ≤ Tamb ≤ Tmax
20
V/mV
35
RL = 32Ω, T=25°C
16
Total supply current
No load, Vout = VCC/2,
T=25°C
Tmin ≤ Tamb ≤ Tmax
2
GBP
Gain bandwidth product
RL = 600Ω
4
CMR
Common mode rejection
ratio
T=25°C
Tmin ≤ Tamb ≤ Tmax
60
56
80
SVR
Supply voltage rejection ratio T=25°C
VCC = 4.5 to 5.5V
Tmin ≤ Tamb ≤ Tmax
60
60
85
Output short circuit current
50
80
mA
SR
Slew rate
0.7
1.3
V/μs
φm
Phase margin at unit gain
RL = 600Ω, CL =100pF
68
Degrees
Gm
Gain margin
RL = 600Ω, CL =100pF
12
dB
en
Equivalent input noise
voltage
f = 1kHz
9
nV
-----------Hz
Icc
Io
3
3.2
mA
MHz
dB
dB
7/21
Electrical characteristics
Table 4.
Symbol
THD
Cs
8/21
TS922
Electrical characteristics measured at VCC = 5V, VDD = 0V, Vicm = Vcc/2,
Tamb = 25°C, and RL connected to Vcc/2 (unless otherwise specified) (continued)
Parameter
Total harmonic distortion
Channel separation
Conditions
Vout= 2Vp-p, F= 1kHz, Av= 1, RL=600Ω
Min.
Typ.
Max.
Unit
0.005
%
120
dB
TS922
Figure 3.
Electrical characteristics
Output short circuit current vs.
output voltage
Figure 4.
Total supply current vs. supply
voltage
Figure 6.
Equivalent input noise voltage vs.
frequency
100
O u tp u t Sh o rt-Circu it Cu rre n t (mA)
80
60
Sink
40
20
Vcc=0/3V
0
-20
-40
-60
Source
-80
-100
0
0,5
Figure 5.
1
1,5
O utput Voltage (V)
2
2,5
3
Voltage gain and phase vs.
frequency
60
180
phase
120
40
G ain (d B)
gain
60
20
Ph a se (De g )
Rl=10k
Cl=100pF
0
0
Equivalent Input Noise (nV/sqrt(Hz)
30
25
VCC=±1.5V
RL=100Ω
20
15
10
5
0
0.01
-20
1E+02
Figure 7.
1E+03
1E+04
1E+05
Frequency (Hz)
1E+06
1E+07
0.1
1
10
100
Frequency (kHz)
-60
1E+08
THD + noise vs. frequency
Figure 8.
THD + noise vs. frequency
0.04
0.02
0.032
THD+Noise (%)
THD+Noise (%)
0.015
RL=2k Vo=10Vpp
VCC=±6V Av= 1
0.01
0.024
RL=32Ω Vo=4Vpp
VCC=±2.5V Av= 1
0.016
0.005
0.008
0
0
0.01
0.1
1
Frequency (kHz)
10
100
0.01
0.1
1
10
100
Frequency (kHz)
9/21
Electrical characteristics
Figure 9.
TS922
THD + noise vs. frequency
Figure 10. THD + noise vs. output voltage
10,000
0.7
0.6
1,000
0.4
THD+No ise (%)
THD+Noise (%)
0.5
RL=32Ω Vo=2Vpp
VCC=±1.5V Av= 10
0.3
RL=600Ω f=1kHz
VCC=0/3V Av= -1
0,100
0.2
0,010
0.1
0
0.01
0.1
1
10
0,001
100
0
0,2
0,4
Frequency (kHz)
Figure 11. THD + noise vs. output voltage
0,6
Vout (V rm s)
0,8
1
1,2
Figure 12. THD + noise vs. output voltage
10
10
1
THD+Noise (%)
THD+Noise (%)
1
RL=32Ω f=1kHz
VCC=±1.5V Av= -1
0.1
RL=2kΩ f=1kHz
VCC=±1.5V Av= -1
0.1
0.01
0.01
0
0.2
0.4
0.6
0.8
1
Vout (Vrms)
0.001
0
0.2
0.4
0.6
Vout (Vrms)
Figure 13. Open loop gain and phase vs.
frequency
180
50
40
Phase (Deg)
Gain (dB)
120
30
CL=500pF
20
60
10
0
0
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
10/21
1E+6
1E+7
1E+8
0.8
1
1.2
TS922
Macromodel
4
Macromodel
4.1
Important note concerning this macromodel
Please consider the following remarks before using this macromodel.
●
All models are a trade-off between accuracy and complexity (i.e. simulation time).
●
Macromodels are not a substitute to breadboarding; rather, they confirm the validity of
a design approach and help to select surrounding component values.
●
A macromodel emulates the nominal performance of a typical device within specified
operating conditions (temperature, supply voltage, for example). Thus the
macromodel is often not as exhaustive as the datasheet, its purpose is to illustrate the
main parameters of the product.
Data derived from macromodels used outside of the specified conditions (VCC, temperature,
for example) or even worse, outside of the device operating conditions (VCC, Vicm, for
example), is not reliable in any way.
Section 4.2 presents the electrical characteristics resulting from the use of these
macromodels.
4.2
Electrical characteristics from macromodelization
Table 5.
Electrical characteristics resulting from macromodel simulation at VCC =
3V, VDD = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise
specified)
Symbol
Conditions
Vio
Value
Unit
0
mV
Avd
RL = 10kΩ
200
V/mV
ICC
No load, per operator
1.2
mA
-0.2 to 3.2
V
Vicm
VOH
RL = 10kΩ
2.95
V
VOL
RL = 10kΩ
25
mV
Isink
VO = 3V
80
mA
Isource
VO = 0V
80
mA
GBP
RL = 600kΩ
4
MHz
SR
RL = 10kΩ, CL = 100pF
1.3
V/μs
φm
RL = 600kΩ
68
Degrees
11/21
Macromodel
4.3
TS922
Macromodel code
** Standard Linear Ics Macromodels, 1996.
** CONNECTIONS:
* 1 INVERTING INPUT
* 2 NON-INVERTING INPUT
* 3 OUTPUT
* 4 POSITIVE POWER SUPPLY
* 5 NEGATIVE POWER SUPPLY
*
.SUBCKT TS92X 1 2 3 4 5
*
.MODEL MDTH D IS=1E-8 KF=2.664234E-16 CJO=10F
*
* INPUT STAGE
CIP 2 5 1.000000E-12
CIN 1 5 1.000000E-12
EIP 10 5 2 5 1
EIN 16 5 1 5 1
RIP 10 11 8.125000E+00
RIN 15 16 8.125000E+00
RIS 11 15 2.238465E+02
DIP 11 12 MDTH 400E-12
DIN 15 14 MDTH 400E-12
VOFP 12 13 DC 153.5u
VOFN 13 14 DC 0
IPOL 13 5 3.200000E-05
CPS 11 15 1e-9
DINN 17 13 MDTH 400E-12
VIN 17 5 -0.100000e+00
DINR 15 18 MDTH 400E-12
VIP 4 18 0.400000E+00
FCP 4 5 VOFP 1.865000E+02
FCN 5 4 VOFN 1.865000E+02
FIBP 2 5 VOFP 6.250000E-03
FIBN 5 1 VOFN 6.250000E-03
* GM1 STAGE ***************
FGM1P 119 5 VOFP 1.1
FGM1N 119 5 VOFN 1.1
RAP 119 4 2.6E+06
RAN 119 5 2.6E+06
* GM2 STAGE ***************
G2P 19 5 119 5 1.92E-02
G2N 19 5 119 4 1.92E-02
R2P 19 4 1E+07
R2N 19 5 1E+07
**************************
VINT1 500 0 5
GCONVP 500 501 119 4 19.38
VP 501 0 0
GCONVN 500 502 119 5 19.38
VN 502 0 0
12/21
TS922
Macromodel
********* orientation isink isource
VINT2 503 0 5
FCOPY 503 504 VOUT 1
DCOPYP 504 505 MDTH 400E-9
VCOPYP 505 0 0
DCOPYN 506 504 MDTH 400E-9
VCOPYN 0 506 0
***************************
F2PP 19 5 poly(2) VCOPYP VP 0 0 0 0
F2PN 19 5 poly(2) VCOPYP VN 0 0 0 0
F2NP 19 5 poly(2) VCOPYN VP 0 0 0 0
F2NN 19 5 poly(2) VCOPYN VN 0 0 0 0
* COMPENSATION ************
CC 19 119 25p
* OUTPUT ***********
DOPM 19 22 MDTH 400E-12
DONM 21 19 MDTH 400E-12
HOPM 22 28 VOUT 6.250000E+02
VIPM 28 4 5.000000E+01
HONM 21 27 VOUT 6.250000E+02
VINM 5 27 5.000000E+01
VOUT 3 23 0
ROUT 23 19 6
COUT 3 5 1.300000E-10
DOP 19 25 MDTH 400E-12
VOP 4 25 1.052
DON 24 19 MDTH 400E-12
VON 24 5 1.052
.ENDS;TS92X
*******
0.5
0.5
1.75
1.75
13/21
Package mechanical data
5
TS922
Package mechanical data
In order to meet environmental requirements, STMicroelectronics offers these devices in
ECOPACK® packages. These packages have a Lead-free second level interconnect. The
category of second level interconnect is marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics
trademark. ECOPACK specifications are available at: www.st.com.
5.1
Flip-chip package (8 bumps)
Figure 14. Top view and dimensions of 8-bump flip-chip
1600 µm
1600 µm
■
Die size: 1600µm x 1600µm ±30µm
■
Die height: 350µm ±20µm
■
Die height (including bumps):
600µm
■
Bumps diameter: 315µm ±50µm
■
Bumps height: 250µm ±40µm
■
Pitch: 500µm ±10µm
500µm
500µm
∅ 315µm
600 µm
Figure 15. Flip-chip footprint recommendation
TS922IJ Footprint
500μm
75µm min.
100μm max.
500μm
Φ=400μm
Track
150μm min.
500μm
500μm
Φ=250μm
Solder mask opening
Pad in Cu 18μm with Flash NiAu (6μm, 0.15μm)
14/21
TS922
Package mechanical data
Figure 16. Flip-chip marking (top view)
BUMP 1A CORNER
n
n
n
n
E
Logo: ST
Part Number: 922
Date Code: YWW
The dot is for marking the bump
1A corner
LEADFREE
922
YWW
1
A
1
A
User direction of feed
Note:
Device orientation: the devices are oriented in the carrier pocket with bump number A1
adjacent to the sprocket holes.
15/21
Package mechanical data
5.2
TS922
DIP8 package
Dimensions
Ref.
Millimeters
Min.
A
Typ.
Max.
Min.
3.3
Typ.
Max.
0.130
a1
0.7
B
1.39
1.65
0.055
0.065
B1
0.91
1.04
0.036
0.041
b
b1
0.028
0.5
0.38
0.020
0.5
D
0.015
0.020
9.8
0.386
E
8.8
0.346
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
7.1
0.280
I
4.8
0.189
L
Z
16/21
Inches
3.3
0.44
0.130
1.6
0.017
0.063
TS922
5.3
Package mechanical data
SO-8 package
Dimensions
Ref.
Millimeters
Min.
Typ.
Inches
Max.
Min.
Typ.
Max.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.04
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
ddd
8° (max.)
0.1
0.04
17/21
Package mechanical data
5.4
TS922
TSSOP8 package
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.2
A1
0.05
A2
0.80
b
Max.
0.047
0.15
0.002
1.05
0.031
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
2.90
3.00
3.10
0.114
0.118
0.122
E
6.20
6.40
6.60
0.244
0.252
0.260
E1
4.30
4.40
4.50
0.169
0.173
0.177
e
1.00
0.65
K
0°
L
0.45
L1
18/21
Inches
0.60
1
0.006
0.039
0.041
0.0256
8°
0°
0.75
0.018
8°
0.024
0.039
0.030
TS922
6
Ordering information
Ordering information
Table 6.
Order codes
Part number
Temperature
range
Package
Packaging
DIP8
Tube
TS922IN
Marking
TS922IN
TS922AIN
TS922AIN
TS922ID/IDT
SO-8
TS922AID/AIDT
TS922IPT
Tube or tape &
reel
922I
922AI
922I
TSSOP8
(Thin shrink outline package)
Tape & reel
TS922IJT/EIJT
Flip-chip
Tape & reel
922
TS922IYD/IYDT
SO-8
(automotive grade level)
Tube or tape &
reel
922IY
TSSOP8
(automotive grade level)
Tape & reel
TS922AIPT
TS922AIYD/AIYDT
TS922IYPT
TS922AIYPT
-40°C, +125°C
922AI
922AIY
922IY
922AY
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Revision history
7
TS922
Revision history
Table 7.
20/21
Document revision history
Date
Revision
Changes
1-Feb-2001
1
First release.
1-Jul-2004
2
Flip-chip package inserted in the document.
2-May-2005
3
Modifications in AMR Table 1 on page 4 (explanation of Vid and Vi
limits, ESD MM and CDM values added, Rthja added).
1-Aug-2005
4
PPAP references inserted in the datasheet, see Table 6 on page 19.
1-Mar-2006
5
TS922EIJT part number inserted in the datasheet, see
Table 6 on page 19.
26-Jan-2007
6
Modifications in AMR Table 1 on page 4 (Rthjc added), parameter
limits on full temperature range added in Table 3 on page 5 and
Table 4 on page 7.
TS922
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