TS912 Rail-to-rail CMOS dual operational amplifier Features ■ Rail-to-rail input and output voltage ranges ■ Single (or dual) supply operation from 2.7V to 16V ■ Extremely low input bias current: 1pA typ. ■ Low input offset voltage: 2mV max. ■ Specified for 600Ω and 100Ω loads ■ Low supply current: 200μA/ampli (VCC = 3V) ■ Latch-up immunity ■ ESD tolerance: 3kV ■ Spice macromodel included in this specification N DIP-8 (Plastic package) D SO-8 (Plastic micropackage) Description Pin connections (top view) The TS912 is a rail-to-rail CMOS dual operational amplifier designed to operate with a single or dual supply voltage. The input voltage range Vicm includes the two supply rails VCC+ and VCC-. Output 1 1 8 VCC + Inverting Input 1 2 - Non-inverting Input 1 3 + VCC 4 7 Output 2 - 6 Inverting Input 2 + 5 Non-inverting Input 2 The output reaches: ■ VCC- +30mV, VCC+ -40mV, with RL = 10kΩ ■ VCC- +300mV, VCC+ -400mV, with RL = 600Ω This product offers a broad supply voltage operating range from 2.7V to 16V and supply current of only 200μA/amp (VCC = 3V). Source and sink output current capability is typically 40mA (at VCC = 3V), fixed by an internal limitation circuit. October 2007 Rev 5 1/18 www.st.com 18 Absolute maximum ratings and operating conditions TS912 1 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol VCC Vid Parameter Supply voltage (1) Differential input voltage (2) (3) Value Unit 18 V ±18 V -0.3 to 18 V Vi Input voltage Iin Current on inputs ±50 mA Io Current on outputs ±130 mA -65 to +150 °C Maximum junction temperature 150 °C Rthja Thermal resistance junction to ambient (4) DIP8 SO-8 85 125 °C/W Rthjc Thermal resistance junction to case (4) DIP8 SO-8 41 40 °C/W HBM: human body model(5) 3 kV 200 V 1500 V Tstg Tj ESD Storage temperature MM: machine model(6) CDM: charged device model(7) 1. All voltage values, except differential voltage are with respect to network ground terminal. 2. Differential voltages are non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of input and output voltages must never exceed VCC+ +0.3V. 4. Short-circuits can cause excessive heating. Destructive dissipation can result from simultaneous short-circuits on all amplifiers. These values are typical. 5. Human body model: A 100pF capacitor is charged to the specified voltage, then discharged through a 1.5kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 6. Machine model: A 200pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5Ω). This is done for all couples of connected pin combinations while the other pins are floating. 7. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. Table 2. Operating conditions Symbol VCC 2/18 Parameter Value Supply voltage Vicm Common mode input voltage range Toper Operating free air temperature range Unit 2.7 to 16 - V + VCC -0.2 to VCC +0.2 V -40 to + 125 °C TS912 Schematic diagram 2 Schematic diagram Figure 1. Schematic diagram (1/2 TS912) VCC Non-inverting Input Internal Vref Inverting Input Output VCC 3/18 Electrical characteristics TS912 3 Electrical characteristics Table 3. VCC+ = 3V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified) Symbol Vio ΔVio Parameter Input bias current (1) Tmin ≤ Tamb ≤ Tmax ICC Supply current (per amplifier, AVCL = 1, no load) Tmin ≤ Tamb ≤ Tmax CMR Common mode rejection ratio Vic = 0 to 3V, Vo = 1.5V SVR Supply voltage rejection ratio (VCC+ = 2.7 to 3.3V, Vo = VCC/2) Avd Large signal voltage gain (RL = 10kΩ, Vo = 1.2V to 1.8V) Tmin ≤ Tamb ≤ Tmax VOH High level output voltage (Vid = 1V) RL = 100kΩ RL = 10kΩ RL = 600Ω RL = 100Ω Tmin ≤ Tamb ≤ Tmax RL = 10kΩ RL = 600Ω GBP 4/18 Gain bandwidth product (AVCL = 100, RL = 10kΩ, CL = 100pF, f = 100kHz) mV μV/°C 5 1 100 200 pA 1 150 300 pA 200 300 400 μA 70 dB 50 80 dB 3 2 10 2.95 2.9 2.3 V/mV 2.96 2.6 2 V 2.8 2.1 Low level output voltage (Vid = -1V) RL = 100kΩ RL = 10kΩ RL = 600Ω RL = 100Ω Tmin ≤ Tamb ≤ Tmax RL = 10kΩ RL = 600Ω Output short-circuit current (Vid = ±1V) Source (Vo = VCC-) Sink (Vo = VCC+) Unit 12 7 3 (1) Iib Max. 10 5 2 Input offset voltage drift Input offset current Tmin ≤ Tamb ≤ Tmax Io Typ. Input offset voltage (Vic = Vo = VCC/2) TS912 TS912A TS912B Tmin ≤ Tamb ≤ Tmax TS912 TS912A TS912B Iio VOL Min. 30 300 900 50 70 400 mV 100 600 20 20 40 40 mA 0.8 MHz TS912 Table 3. Electrical characteristics VCC+ = 3V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified) (continued) Symbol Parameter Min. Typ. Max. Unit SR+ Slew rate (AVCL = 1, RL = 10kΩ, CL = 100pF, Vi = 1.3V to 1.7V) 0.4 V/μs SR- Slew rate (AVCL = 1, RL = 10kΩ, CL = 100pF, Vi = 1.3V to 1.7V) 0.3 V/μs φm Phase margin 30 Degrees en Equivalent input noise voltage (Rs = 100Ω, f = 1kHz) 30 nV/√Hz 1. Maximum values include unavoidable inaccuracies of the industrial tests. 5/18 Electrical characteristics Table 4. TS912 VCC+ = 5V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified) Symbol Vio ΔVio Parameter Min. Typ. Input offset voltage (Vic = Vo = VCC/2) TS912 TS912A TS912B Tmin ≤ Tamb ≤ Tmax TS912 TS912A TS912B 10 5 2 Iib Input bias current (1) Tmin ≤ Tamb ≤ Tmax ICC Supply current (per amplifier, AVCL = 1, no load) Tmin ≤ Tamb ≤ Tmax mV μV/°C 5 (1) Input offset current Tmin ≤ Tamb ≤ Tmax Unit 12 7 3 Input offset voltage drift Iio Max. 1 100 200 pA 1 150 300 pA 230 350 450 μA CMR Common mode rejection ratio Vic = 1.5 to 3.5V, Vo = 2.5V 60 85 dB SVR Supply voltage rejection ratio (VCC+ = 3 to 5V, Vo = VCC/2) 55 80 dB Avd Large signal voltage gain (RL = 10kΩ, Vo = 1.5V to 3.5V) Tmin ≤ Tamb ≤ Tmax 10 7 40 VOH High level output voltage (Vid = 1V) RL = 100kΩ RL = 10kΩ RL = 600Ω RL = 100Ω Tmin ≤ Tamb ≤ Tmax RL = 10kΩ RL = 600Ω VOL 4.95 4.55 3.7 V 4.8 4.1 Low level output voltage (Vid = -1V) RL = 100kΩ RL = 10kΩ RL = 600Ω RL = 100Ω Tmin ≤ Tamb ≤ Tmax RL = 10kΩ RL = 600Ω Output short-circuit current (Vid = ±1V) Source (Vo = VCC-) Sink (Vo = VCC+) Io 4.95 4.9 4.25 V/mV 40 350 1400 50 100 500 mV 150 750 45 45 65 65 mA 1 MHz GBP Gain bandwidth product (AVCL = 100, RL = 10kΩ, CL = 100pF, f = 100kHz) SR+ Slew rate (AVCL = 1, RL = 10kΩ, CL = 100pF, Vi = 1V to 4V) 0.8 V/μs - Slew rate (AVCL = 1, RL = 10kΩ, CL = 100pF, Vi = 1V to 4V) 0.6 V/μs SR 6/18 TS912 Table 4. Electrical characteristics VCC+ = 5V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified) (continued) Symbol en VO1/VO2 φm Parameter Min. Typ. Max. Unit Equivalent input noise voltage (Rs = 100Ω, f = 1kHz) 30 nV/√Hz Channel separation (f = 1kHz) 120 dB Phase margin 30 Degrees 1. Maximum values include unavoidable inaccuracies of the industrial tests. 7/18 Electrical characteristics Table 5. TS912 VCC+ = 10V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified) Symbol Vio ΔVio Parameter Min. Typ. Input offset voltage (Vic = Vo = VCC/2) TS912 TS912A TS912B Tmin ≤ Tamb ≤ Tmax TS912 TS912A TS912B 10 5 2 Iib Input bias current (1) Tmin ≤ Tamb ≤ Tmax ICC Supply current (per amplifier, AVCL = 1, no load) Tmin ≤ Tamb ≤ Tmax mV μV/°C 5 (1) Input offset current Tmin ≤ Tamb ≤ Tmax Unit 12 7 3 Input offset voltage drift Iio Max. 1 100 200 pA 1 150 300 pA 400 600 700 μA CMR Common mode rejection ratio Vic = 3 to 7V, Vo = 5V Vic = 0 to 10V, Vo = 5V 60 50 90 75 dB SVR Supply voltage rejection ratio (VCC+ = 5 to 10V, Vo = VCC/2) 60 90 dB Avd Large signal voltage gain (RL = 10kΩ, Vo = 2.5V to 7.5V) Tmin ≤ Tamb ≤ Tmax 15 10 50 VOH High level output voltage (Vid = 1V) RL = 100kΩ RL = 10kΩ RL = 600Ω RL = 100Ω Tmin ≤ Tamb ≤ Tmax RL = 10kΩ RL = 600Ω VOL Io GBP 8/18 9.95 9.85 9 Gain bandwidth product (AVCL = 100, RL = 10kΩ, CL = 100pF, f = 100kHz) 9.95 9.35 7.8 V 9.8 8.8 Low level output voltage (Vid = -1V) RL = 100kΩ RL = 10kΩ RL = 600Ω RL = 100Ω Tmin ≤ Tamb ≤ Tmax RL = 10kΩ RL = 600Ω Output short circuit current (Vid = ±1V) Source (Vo = VCC-) Sink (Vo = VCC+) V/mV 50 650 2300 50 150 800 mV 150 900 45 50 65 75 mA 1.4 MHz TS912 Table 5. Electrical characteristics VCC+ = 10V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified) (continued) Symbol Parameter Min. Typ. Max. Unit SR+ Slew rate (AVCL = 1, RL = 10kΩ, CL = 100pF, Vi = 2.5V to 7.5V) 1.3 V/μs SR- Slew rate (AVCL = 1, RL = 10kΩ, CL = 100pF, Vi = 2.5V to 7.5V) 0.8 V/μs φm Phase margin 40 Degrees en Equivalent input noise voltage (Rs = 100Ω, f = 1kHz) 30 nV/√Hz Total harmonic distortion (AVCL = 1, RL = 10kΩ, CL = 100pF, Vo = 4.75V to 5.25V, f = 1kHz) 0.02 % Input capacitance 1.5 pF THD Cin 1. Maximum values include unavoidable inaccuracies of the industrial tests. 9/18 Electrical characteristics Figure 2. TS912 Supply current (each amplifier) vs. supply voltage Figure 3. 5 Tamb = 25°C A VCL = 1 V O = VCC / 2 500 OUTPUT VOLTAGE, VOH (V) SUPPLY CURRENT, I CC ( m A) 600 400 300 200 100 0 High level output voltage vs. high level output current 4 8 12 2 VCC = +3V 1 -70 SUPPLY VOLTAGE, V CC (V) Figure 4. Low level output voltage vs. low level output current Figure 5. T amb = 25 ° C V id = -100mV VCC = +3V 2 VCC = +5V 1 0 -14 0 14 28 42 56 70 V CC = 10V V i = 5V No load 10 1 25 50 75 100 125 TEMPERATURE, T amb ( °C) High level output voltage vs. high level output current Figure 7. Low level output voltage vs. low level output current T amb = 25° C Vid = 100mV 16 OUTPUT VOLTAGE, VOL (V) 10 20 OUTPUT VOLTAGE, VOH (V) -28 Input bias current vs. temperature OUTPUT CURRENT, I OL (mA) Figure 6. -42 100 INPUT BIAS CURRENT, I ib (pA) OUTPUT VOLTAGE, V OL (V) 3 -56 OUTPUT CURRENT, I OH (mA) 5 4 VCC = +5V 3 0 16 T amb = 25 °C V id = 100mV 4 VCC = +16V 12 VCC = +10V 8 4 8 T amb = 25 ° C V id = -100mV 6 V CC = 16V 4 V CC = 10V 2 0 -70 -56 -42 -28 -14 OUTPUT CURRENT, IOH (mA) 10/18 0 0 14 28 42 56 70 OUTPUT CURRENT, I OL (mA) TS912 Electrical characteristics GAIN GAIN (dB) 40 30 PHASE 20 Phase Margin Tamb = 25°C VCC = 10V R L = 10k W C L = 100pF A VCL = 100 10 0 0 45 90 135 Gain Bandwidth Product 180 -10 10 2 10 3 4 5 6 10 10 10 FREQUENCY, f (Hz) 10 7 1000 600 200 0 4 8 40 30 12 30 16 16 10 10 Phase Margin Tamb = 25°C V CC = 10V R L = 600W C L = 100pF A VCL = 100 20 2 SUPPLY VOLTAGE, VCC (V) 10 3 0 45 PHASE 0 10 20 8 12 GAIN 40 GAIN (dB) PHASE MARGIN, f m (Degrees) 1400 50 Tamb = 25°C R L = 10kW C L = 100pF 4 Tamb = 25°C R L = 10kW C L = 100pF Figure 11. Gain and phase vs. frequency 60 0 1800 SUPPLY VOLTAGE, VCC (V) Figure 10. Phase margin vs. supply voltage 50 Gain bandwidth product vs. supply voltage 135 Gain Bandwidth Product 4 5 10 10 10 FREQUENCY, f (Hz) 90 180 6 10 PHASE (Degrees) 50 Figure 9. GAIN BANDW. PROD., GBP (kHz) Gain and phase vs. frequency PHASE (Degrees) Figure 8. 7 1800 PHASE MARGIN, fm (Degrees) GAIN BANDW. PROD., GBP (kHz) Figure 12. Gain bandwidth product vs. supply Figure 13. Phase margin vs. supply voltage voltage Tamb = 25°C R L = 600W C L = 100pF 1400 1000 600 200 0 4 8 12 SUPPLY VOLTAGE, VCC (V) 16 60 Tamb = 25°C R L = 600W C L = 100pF 50 40 30 20 0 4 8 12 16 SUPPLY VOLTAGE, VCC (V) 11/18 Macromodel TS912 EQUIVALENT INPUT VOLTAGE NOISE (nV/VHz) Figure 14. Input voltage noise vs. frequency 150 VCC = 10V Tamb = 25°C RS = 100W 100 50 0 10 100 1000 10000 FREQUENCY (Hz) 4 Macromodel 4.1 Important note concerning this macromodel Please consider the following remarks before using this macromodel. ● All models are a trade-off between accuracy and complexity (i.e. simulation time). ● Macromodels are not a substitute to breadboarding; rather, they confirm the validity of a design approach and help to select surrounding component values. ● A macromodel emulates the nominal performance of a typical device within specified operating conditions (temperature, supply voltage, for example). Thus the macromodel is often not as exhaustive as the datasheet, its purpose is to illustrate the main parameters of the product. Data derived from macromodels used outside of the specified conditions (VCC, temperature, for example) or even worse, outside of the device operating conditions (VCC, Vicm, for example), is not reliable in any way. 12/18 TS912 4.2 Macromodel Macromodel code ** Standard Linear Ics Macromodels, 1993. ** CONNECTIONS : * 1 INVERTING INPUT * 2 NON-INVERTING INPUT * 3 OUTPUT * 4 POSITIVE POWER SUPPLY * 5 NEGATIVE POWER SUPPLY .SUBCKT TS912 1 2 3 4 5 ********************************************************** .MODEL MDTH D IS=1E-8 KF=6.563355E-14 CJO=10F * INPUT STAGE CIP 2 5 1.500000E-12 CIN 1 5 1.500000E-12 EIP 10 5 2 5 1 EIN 16 5 1 5 1 RIP 10 11 6.500000E+00 RIN 15 16 6.500000E+00 RIS 11 15 7.655100E+00 DIP 11 12 MDTH 400E-12 DIN 15 14 MDTH 400E-12 VOFP 12 13 DC 0.000000E+00 VOFN 13 14 DC 0 IPOL 13 5 4.000000E-05 CPS 11 15 3.82E-08 DINN 17 13 MDTH 400E-12 VIN 17 5 -0.5000000e+00 DINR 15 18 MDTH 400E-12 VIP 4 18 -0.5000000E+00 FCP 4 5 VOFP 7.750000E+00 FCN 5 4 VOFN 7.750000E+00 * AMPLIFYING STAGE FIP 5 19 VOFP 5.500000E+02 FIN 5 19 VOFN 5.500000E+02 RG1 19 5 5.087344E+05 RG2 19 4 5.087344E+05 CC 19 29 2.200000E-08 HZTP 30 29 VOFP 12.33E+02 HZTN 5 30 VOFN 12.33E+02 DOPM 19 22 MDTH 400E-12 DONM 21 19 MDTH 400E-12 HOPM 22 28 VOUT 3135 VIPM 28 4 150 HONM 21 27 VOUT 3135 VINM 5 27 150 EOUT 26 23 19 5 1 VOUT 23 5 0 ROUT 26 3 65 COUT 3 5 1.000000E-12 DOP 19 68 MDTH 400E-12 VOP 4 25 1.924 13/18 Package information TS912 HSCP 68 25 VSCP1 1E8 DON 69 19 MDTH 400E-12 VON 24 5 2.4419107 HSCN 24 69 VSCN1 1.5E8 VSCTHP 60 61 0.1375 DSCP1 61 63 MDTH 400E-12 VSCP1 63 64 0 ISCP 64 0 1.000000E-8 DSCP2 0 64 MDTH 400E-12 DSCN2 0 74 MDTH 400E-12 ISCN 74 0 1.000000E-8 VSCN1 73 74 0 DSCN1 71 73 MDTH 400E-12 VSCTHN 71 70 -0.75 ESCP 60 0 2 1 500 ESCN 70 0 2 1 -2000 .ENDS 5 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 14/18 TS912 5.1 Package information DIP-8 package mechanical data Figure 15. DIP8 package mechanical data Dimensions Ref. Millimeters Min. Typ. A Inches Max. Min. Typ. 5.33 Max. 0.210 A1 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 9.02 9.27 10.16 0.355 0.365 0.400 E 7.62 7.87 8.26 0.300 0.310 0.325 E1 6.10 6.35 7.11 0.240 0.250 0.280 e 2.54 0.100 eA 7.62 0.300 eB L 10.92 2.92 3.30 3.81 0.430 0.115 0.130 0.150 15/18 Package information 5.2 TS912 SO-8 package mechanical data Figure 16. SO-8 package mechanical data Dimensions Ref. Millimeters Min. Typ. A Max. Min. Typ. 1.75 0.25 Max. 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 H 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 0.004 0.010 0.049 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k 1° 8° 1° 8° ccc 16/18 Inches 0.10 0.004 TS912 6 Ordering information Ordering information Table 6. Order codes Part number Temperature range Package Packing DIP8 Tube Marking TS912IN TS912IN TS912AIN TS912AIN TS912ID TS912IDT 912I TS912AID TS912AIDT SO-8 TS912BID TS912BIDT 912AI -40°C, +125°C 912BI Tube or Tape & reel TS912IYD TS912IYDT(1) 912IY TS912AIYD TS912AIYDT(1) SO-8 (Automotive grade level) TS912BIYD TS912BIYDT(1) 912AIY 912BY 1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent. 7 Revision history Table 7. Document revision history Date Revision 4-Dec.-2001 1 First release. 31-Jul-2005 2 PPAP references inserted in the datasheet, see order codes table. ESD protection inserted in AMR table. 3-Oct-2005 3 Some errors in the Order Codes table were corrected. Reorganization of Section 4: Macromodel. 13-Feb- 2006 4 Parameters added in AMR table (Tj, ESD, Rthja, Rthjc). 5 Corrected units and ESD footnotes in Table 1: Absolute maximum ratings. Corrected misalignments in electrical characteristics table. Updated Section 4: Macromodel. Added missing automotive grade order codes and footnote in Table 6: Order codes. Format update. 16-Oct-2007 Changes 17/18 TS912 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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