STMICROELECTRONICS VND5050AKTR-E

VND5050AJ-E
VND5050AK-E
Double channel high side driver with analog current sense
for automotive applications
Features
Max transient supply voltage
VCC
41V
Operating voltage range
VCC 4.5 to 36V
Max On-State resistance (per ch.)
RON
50 mΩ
Current limitation (typ)
ILIMH
18 A
Off state supply current
IS
2 µA(1)
1. Typical value with all loads connected
■
■
■
Main
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/ec
european directive
Diagnostic Functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
Protections
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shut down
– Reverse battery protection (see Application
schematic)
– Electrostatic discharge protection
February 2008
PowerSSO-12
PowerSSO-24
Application
■
All types of resistive, inductive and capacitive
loads
■
Suitable as LED driver
Description
The VND5050AJ-E, VND5050AK-E is a
monolithic device made using STMicroelectronics
VIPower M0-5 technology. It is intended for driving
resistive or inductive loads with one side
connected to ground. Active VCC pin voltage
clamp protects the device against low energy
spikes (see ISO7637 transient compatibility
table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
When CS_DIS is driven high, the current sense
pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Rev 7
1/38
www.st.com
38
Contents
VND5050AJ-E / VND5050AK-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
4
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21
3.1.2
Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2
PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3
PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4
PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5
PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/38
VND5050AJ-E / VND5050AK-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 8.
Table 7.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PowerSSO-12™ thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24™ thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/38
List of figure
VND5050AJ-E / VND5050AK-E
List of figure
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
4/38
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
On state resistance Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
On state resistance Vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum turn Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 24
PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON) . . . 25
Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 27
PowerSSO-24™ Thermal impedance junction ambient single pulse (one channel ON) . . 28
Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28
PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSS0-24TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PowerSSO-24TM tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VND5050AJ-E / VND5050AK-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
VCC
UNDERVOLTAGE
VCC
CLAMP
OUTPUT1
PwCLAMP 1
GND
CURRENT
SENSE1
DRIVER 1
ILIM 1
INPUT1
LOGIC
VDSLIM 1
PwrLIM 1
PwCLAMP 2
DRIVER 2
OUTPUT2
ILIM 2
OVERTEMP. 1
INPUT2
VDSLIM 2
IOUT1
K1
CURRENT
SENSE2
OVERTEMP. 2
IOUT2
K2
PwrLIM 2
CS_DIS
Table 1.
Pin function
Name
VCC
OUTPUT1,2
GND
INPUT1,2
CURRENT
SENSE1,2
CS_DIS
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
Analog current sense pin, delivers a current proportional to the load current
Active high CMOS compatible pin, to disable the current sense pin.
5/38
Block diagram and pin description
Figure 2.
VND5050AJ-E / VND5050AK-E
Configuration diagram (top view)
TAB = Vcc
GND
INPUT2
INPUT1
CURRENT SENSE1
CURRENT SENSE2
CS_DIS
1
2
3
4
5
6
12
11
10
9
8
7
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
VCC
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
CS_DIS.
VCC
Vcc
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
Vcc
TAB = VCC
PowerSSO-12
Table 2.
Suggested connections for unused and N.C. pins
Connection / pin
Floating
To ground
1. Not recommended.
6/38
PowerSSO-24
Current Sense
N.C.
Output
Input
CS_DIS
N.R.(1)
X
X
X
X
Through 1KΩ
resistor
X
N.R.(1)
Through 10KΩ
resistor
Through 10KΩ
resistor
VND5050AJ-E / VND5050AK-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
VFn
ICSD
OUTPUT1
CS_DIS
VCSD
CURRENT
SENSE1
IIN1
INPUT1
VIN1
IIN2
VIN2
OUTPUT2
IOUT1
VOUT1
ISENSE1
VSENSE1
IOUT2
VOUT2
INPUT2
CURRENT
SENSE2
GND
ISENSE2
VSENSE2
IGND
Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 3.
Absolute maximum ratings
Symbol
Parameter
VCC
DC supply voltage
Value
Unit
41
V
-VCC
Reverse DC supply voltage
0.3
V
-IGND
DC reverse ground pin current
200
mA
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
12
A
IIN
ICSD
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
200
mA
VCC-41
+VCC
V
V
104
mJ
-ICSENSE DC reverse CS pin current
VCSENSE Current sense maximum voltage
EMAX
Maximum switching energy
(L= 3mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C; IOUT = IlimL(Typ.))
7/38
Electrical specifications
Table 3.
VND5050AJ-E / VND5050AK-E
Absolute maximum ratings (continued)
Symbol
Value
Unit
4000
2000
4000
5000
5000
V
V
V
V
V
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
VESD
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
– INPUT
– CURRENT SENSE
– CS_DIS
– OUTPUT
– VCC
VESD
Charge device model (CDM-AEC-Q100-011)
Tj
Tstg
2.2
Parameter
Thermal data
Table 4.
Thermal data
Value
Symbol
8/38
Parameter
Rthj-case
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-amb
Thermal resistance junction-ambient
(Max.)
Unit
PowerSSO-12
PowerSSO-24
2.7
2.7
°C/W
See Figure 29
See Figure 33
°C/W
VND5050AJ-E / VND5050AK-E
2.3
Electrical specifications
Electrical characteristics
8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.
Table 5.
Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
RON
Vclamp
IS
IL(off)
VF
Test conditions
Min.
Typ.
Max.
Unit
4.5
13
36
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shut-down
hysteresis
0.5
On state resistance (2)
IOUT= 2A; Tj= 25°C
IOUT= 2A; Tj= 150°C
IOUT= 2A; VCC= 5V; Tj= 25°C
Clamp voltage
IS= 20mA
Supply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V;
IOUT= 0A
Off state output
current(2)
VIN=VOUT=0V; VCC=13V;
Tj= 25°C
VIN=VOUT=0V; VCC=13V;
Tj= 125°C
Output - VCC diode
voltage (2)
41
0
V
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(1)
3
5(1)
6
µA
mA
0.01
3
0
µA
5
-IOUT=4A; Tj=150°C
0.7
V
Max.
Unit
1. PowerMOS leakage included.
2. For each channel.
Table 6.
Symbol
Switching (VCC = 13V; Tj = 25°C)
Parameter
Test conditions
Min.
Typ.
td(on)
Turn-On delay time
RL= 6.5Ω (see Figure 8)
25
µs
td(off)
Turn-Off delay time
RL= 6.5Ω (see Figure 8)
35
µs
dVOUT/dt(on) Turn-On voltage slope
RL= 6.5Ω
See Figure 21
V/ µs
dVOUT/dt(off) Turn-Off voltage slope
RL= 6.5Ω
See Figure 22
V/ µs
WON
Switching energy losses
during twon
RL= 6.5Ω (see Figure 8)
0.24
mJ
WOFF
Switching energy losses
during twoff
RL= 6.5Ω (see Figure 8)
0.2
mJ
9/38
Electrical specifications
Table 7.
Symbol
VND5050AJ-E / VND5050AK-E
Logic input
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VCSDL
CS_DIS low level voltage
ICSDL
Low level CS_DIS
current
VCSDH
CS_DIS high level
voltage
ICSDH
High level CS_DIS
current
VCSD(hyst)
CS_DIS hysteresis
voltage
VCSCL
Table 8.
Symbol
CS_DIS clamp voltage
Test conditions
VIN= 0.9V
Unit
0.9
V
1
µA
2.1
V
10
7
V
V
0.9
V
-0.7
VCSD= 0.9V
1
µA
2.1
V
VCSD= 2.1V
10
0.25
7
-0.7
V
V
Protections and diagnostics (1)
Parameter
Test conditions
IlimL
Short circuit current
during thermal cycling
VCC=13V; TR<Tj<TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
Min.
Typ.
Max.
Unit
12
18
24
24
A
A
7
150
175
A
200
TRS + 1 TRS + 5
135
Thermal hysteresis
(TTSD-TR)
Turn-off output voltage
clamp
IOUT=2A; VIN=0; L=6mH
Output voltage drop
limitation
IOUT=0.1A;
Tj= -40°C...+150°C
(see Figure 9)
°C
°C
°C
7
°C
VCC-41 VCC-46 VCC-52
V
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/38
µA
V
5.5
ICSD= 1mA
ICSD= -1mA
µA
V
5.5
IIN= 1mA
IIN= -1mA
VCC= 13V
5V<VCC<36V
VON
Max.
0.25
DC short circuit current
VDEMAG
Typ.
VIN= 2.1V
IlimH
THYST
Min.
VND5050AJ-E / VND5050AK-E
Table 9.
Symbol
Electrical specifications
Current sense (8V<VCC<16V)
Parameter
Test conditions
K0
IOUT/ISENSE
IOUT=0.05A;
VSENSE=0.5V;VCSD=0V;
Tj= -40°C...150°C
K1
IOUT/ISENSE
IOUT=1A; VSENSE=0.5V;VCSD=0V;
Tj= -40°C
Tj= 25°C...150°C
dK1/K1(1)
K2
dK2/K2
IOUT=1A; VSENSE= 0.5V;
Current sense ratio
VCSD=0V;
drift
TJ=-40 °C to 150 °C
IOUT/ISENSE
(1)
K3
dK3/K3(1)
ISENSE0
IOUT=2A; VSENSE=4V;VCSD=0V;
Tj= -40°C
Tj= 25°C...150°C
IOUT=2 A; VSENSE= 4 V;
Current sense ratio
VCSD=0V;
drift
TJ=-40 °C to 150 °C
IOUT/ISENSE
IOUT=4A; VSENSE=4V;VCSD=0V;
Tj=-40°C
Tj=25°C...150°C
IOUT=4 A; VSENSE= 4 V;
Current sense ratio
VCSD=0V;
drift
TJ=-40 °C to 150 °C
Analog sense
leakage current
Min.
Typ.
Max.
1270
2360
3450
1470
1570
2020
2020
2610
2470
-7
1740
1790
+7
2020
2020
-4
1880
1900
%
2320
2250
+4
2010
2010
Unit
%
2160
2120
-2
+2
%
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V;
Tj=-40°C...150°C
0
1
µA
VCSD=0V; VIN=5V;
Tj=-40°C...150°C
0
2
µA
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V;
Tj=-40°C...150°C
0
1
µA
20
mA
IOL
Openload ON state
current detection
threshold
VIN = 5V, ISENSE= 5 µA
4
VSENSE
Max analog sense
output voltage
IOUT=4A; VCSD=0V
5
VSENSEH
Analog sense
output voltage in
overtemperature
condition
VCC=13V; RSENSE=10KΩ
V
9
V
11/38
Electrical specifications
Table 9.
Symbol
ISENSEH
VND5050AJ-E / VND5050AK-E
Current sense (8V<VCC<16V) (continued)
Parameter
Analog sense
output current in
overtemperature
condition
Test conditions
Min.
Typ.
Max.
VCC=13V; VSENSE=5V
8
Delay response
time from falling
tDSENSE1H
edge of CS_DIS
pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSE max
(see Figure 4)
50
100
µs
Delay response
time from rising
tDSENSE1L
edge of CS_DIS
pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max
(see Figure 4)
5
20
µs
Delay response
tDSENSE2H time from rising
edge of INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSE max
(see Figure 4)
80
250
µs
Delay response
time between rising
edge of output
∆tDSENSE2H
current and rising
edge of current
sense
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=2A (see Figure 5)
65
µs
Delay response
tDSENSE2L time from falling
edge of INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max
(see Figure 4)
250
µs
100
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
12/38
Unit
tDSENSE1L
tDSENSE1H
tDSENSE2L
mA
VND5050AJ-E / VND5050AK-E
Figure 5.
Electrical specifications
Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
VIN
∆tDSENSE2H
t
IOUT
IOUTMAX
90% IOUTMAX
t
ISENSE
ISENSEMAX
90% ISENSEMAX
t
13/38
Electrical specifications
Figure 6.
VND5050AJ-E / VND5050AK-E
IOUT/ISENSE Vs. IOUT
IOUT/ISENSE
3000
2500
M ax -40°C to 150°C
M ax 25°C to 150°C
Typ 25°C
2000
M in 25°C to 150°C
M in -40°C to 150°C
1500
1000
500
1
2
3
4
5
IOUT (A)
Figure 7.
Maximum current sense ratio drift vs load current
dk/k(%)
10
5
0
-5
-10
1
2
3
IOUT (A)
Note:
14/38
Parameter guaranteed by design; it is not tested.
4
VND5050AJ-E / VND5050AK-E
Table 10.
Electrical specifications
Truth table
Input
Output
Sense (VCSD=0V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
Short circuit to GND
(Rsc ≤10 mΩ)
L
H
H
L
L
L
0
0 if Tj < TTSD
VSENSEH if Tj > TTSD
Short circuit to VCC
L
H
H
H
0
< Nominal
Negative output voltage
clamp
L
L
0
Conditions
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Figure 8.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tr
tf
t
INPUT
td(on)
td(off)
t
Figure 9.
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
Iout
15/38
Electrical specifications
Table 11.
ISO 7637-2:
2004(E)
VND5050AJ-E / VND5050AK-E
Electrical transient requirements
Test levels (1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
5000
pulses
0.5 s
5s
2 ms, 10 Ω
+50V
5000
pulses
0.2 s
5s
50 µs, 2 Ω
-100V
-150V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75V
+100V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6V
-7V
1 pulse
100 ms, 0.01
Ω
5b (2)
+65V
+87V
1 pulse
400 ms, 2 Ω
Test pulse
III
IV
1
-75V
-100V
2a
+37V
3a
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b (2)
C
C
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
16/38
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
VND5050AJ-E / VND5050AK-E
Electrical specifications
Figure 10. Waveforms
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
Tj
TTSD
TR
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
VSENSEH
SENSE CURRENT
current power
limitation limitation
thermal cycling
SHORTED LOAD
NORMAL LOAD
17/38
Electrical specifications
2.4
VND5050AJ-E / VND5050AK-E
Electrical characteristics curves
Figure 11. Off state output current
Figure 12. High level input current
Iloff (uA)
Iih (uA)
1
5
4.5
0.875
Off State
Vcc=13V
Vin=Vout=0V
0.75
Vin=2.1V
4
3.5
0.625
3
0.5
2.5
2
0.375
1.5
0.25
1
0.125
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C )
Figure 13. Input clamp voltage
Figure 14. Input high level
Vih (V)
Vicl (V)
4
7
6.8
3.5
Iin=1mA
6.6
3
6.4
2.5
6.2
2
6
5.8
1.5
5.6
1
5.4
0.5
5.2
0
5
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Figure 15. Input low level
75
Figure 16. Input hysteresis voltage
Vil (V)
Vhyst (V)
2
1
1.8
0.9
1.6
0.8
1.4
0.7
1.2
0.6
1
0.5
0.8
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
-50
-25
0
25
50
75
Tc (°C )
18/38
50
Tc (°C )
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
Tc (°C )
100
125
VND5050AJ-E / VND5050AK-E
Electrical specifications
Figure 17. On state resistance Vs. Tcase
Figure 18. On state resistance Vs. VCC
R on (mOhm)
R on (mOhm)
100
100
90
90
Iout=2A
Vcc=13V
80
Tc= 150°C
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
Tc= 125°C
Tc= 25°C
Tc= - 40°C
0
0
-50
-25
0
25
50
75
100
125
150
0
175
5
10
15
20
25
30
35
40
150
175
150
175
Vcc (V)
Tc (°C )
Figure 19. Undervoltage shutdown
Figure 20. ILIMH Vs. Tcase
Ilimh (A)
Vusd (V)
16
25
14
22.5
12
20
10
17.5
8
15
6
12.5
4
10
2
7.5
Vcc=13V
5
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
Figure 21. Turn-On voltage slope
Figure 22. Turn-Off voltage slope
(dVout/dt)on (V/ms)
(dVout/dt)off (V/ms)
1000
1000
900
900
Vcc=13V
RI=6.5Ohm
800
Vcc=13V
RI=6.5Ohm
800
700
700
600
600
500
500
400
400
300
300
200
200
100
100
0
0
-50
-25
0
25
50
75
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C )
19/38
Electrical specifications
VND5050AJ-E / VND5050AK-E
Figure 23. STAT_DIS clamp voltage
Figure 24. Low level STAT_DIS voltage
Vsdcl(V)
Vsdl(V)
8
14
7
12
6
Isd=1mA
10
5
8
4
6
3
4
2
2
1
0
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Vsdh(V)
8
7
6
5
4
3
2
1
0
-25
0
25
50
75
Tc (°C )
20/38
-25
0
25
50
75
Tc (°C )
Figure 25. High level STAT_DIS voltage
-50
-50
100
125
150
175
100
125
150
175
VND5050AJ-E / VND5050AK-E
3
Application information
Application information
Figure 26. Application schematic
+5V
VCC
Rprot
CS_DIS
Dld
µC
Rprot
INPUT
OUTPUT
Rprot
CURRENT SENSE
GND
RSENSE
CEXT
VGND
RGND
DGND
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1 : resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
21/38
Application information
VND5050AJ-E / VND5050AK-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2 : diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤Rprot ≤(VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤Rprot ≤180kΩ.
Recommended values: Rprot =10kΩ, CEXT=10nF.
22/38
VND5050AJ-E / VND5050AK-E
3.4
Application information
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn Off current versus inductance (for each channel)
100
A
B
C
I (A)
10
1
0,1
1
10
100
L (mH)
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
23/38
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
4
Package and PCB thermal data
4.1
PowerSSO-12™ thermal data
Figure 28. PowerSSO-12™ PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition (one channel
ON)
RTHj_amb(°C/W)
70
65
60
55
50
45
40
35
30
0
2
4
6
PCB Cu heatsink area (cm^2)
24/38
8
10
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
100
Footprint
2 cm2
8 cm2
10
1
0,1
0,0001
0,001
0,01
0,1
1
Time (s)
10
100
1000
Equation 1: pulse calculation formula
Z
THδ
= R
TH
⋅ δ+Z
THtp
( 1 – δ)
where δ = tP/T
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ (a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/38
Package and PCB thermal data
Table 12.
26/38
VND5050AJ-E / VND5050AK-E
PowerSSO-12™ thermal parameter
Area/island (cm2)
Footprint
R1= R7 (°C/W)
0.7
R2= R8 (°C/W)
2.8
R3 (°C/W)
4
R4 (°C/W)
2
8
8
8
7
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1= C7 (W.s/°C)
0.001
C2= C8 (W.s/°C)
0.0025
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
VND5050AJ-E / VND5050AK-E
4.2
Package and PCB thermal data
PowerSSO-24™ thermal data
Figure 32. PowerSSO-24™ PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 33. Rthj-amb Vs. PCB copper area in open box free air condition (one channel
ON)
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
27/38
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one
channel ON)
Equation 2: pulse calculation formula
Z
THδ
= R
TH
⋅ δ+Z
THtp
( 1 – δ)
where δ = tP/T
Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™(b)
b. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
28/38
VND5050AJ-E / VND5050AK-E
Table 13.
Package and PCB thermal data
PowerSSO-24™ thermal parameter
Area/island (cm2)
Footprint
R1=R7 (°C/W)
0.4
R2=R8 (°C/W)
2
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
2
8
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
0.001
C2=C8 (W.s/°C)
0.0022
C3 (W.s/°C)
0.025
C4 (W.s/°C)
0.75
C5 (W.s/°C)
1
4
9
C6 (W.s/°C)
2.2
5
17
29/38
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
VND5050AJ-E / VND5050AK-E
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
PowerSSO-12™ package information
Figure 36. PowerSSO-12™ package dimensions
30/38
VND5050AJ-E / VND5050AK-E
Table 14.
Package and packing information
PowerSSO-12™ mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
A
1.25
1.62
A1
0
0.1
A2
1.10
1.65
B
0.23
0.41
C
0.19
0.25
D
4.8
5.0
E
3.8
4.0
e
0.8
H
5.8
6.2
h
0.25
0.5
L
0.4
1.27
k
0°
8°
X
1.9
2.5
Y
3.6
4.2
ddd
0.1
31/38
Package and packing information
5.3
VND5050AJ-E / VND5050AK-E
PowerSSO-24™ package information
Figure 37. PowerSSO-24™ package dimensions
Table 15.
PowerSSO-24™ mechanical data
Millimeters
Symbol
Min.
32/38
Typ.
Max.
A
2.15
2.47
A2
2.15
2.40
a1
0
0.075
b
0.33
0.51
c
0.23
0.32
D
10.10
10.50
E
7.4
7.6
e
0.8
e3
8.8
G
0.1
G1
0.06
VND5050AJ-E / VND5050AK-E
Table 15.
Package and packing information
PowerSSO-24™ mechanical data (continued)
Millimeters
Symbol
Min.
H
10.1
h
L
Typ.
Max.
10.5
0.4
0.55
N
0.85
10deg
X
4.1
4.7
Y
6.5
7.1
33/38
Package and packing information
5.4
VND5050AJ-E / VND5050AK-E
PowerSSO-12™ packing information
Figure 38. PowerSSO-12™ tube shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
Empty components pockets
saled with cover tape.
User direction of feed
34/38
No components
500mm min
500mm min
VND5050AJ-E / VND5050AK-E
5.5
Package and packing information
PowerSSO-24™ packing information
Figure 40. PowerSS0-24TM tube shipment (no suffix)
Base Qty
Bulk Qty
Tube length (±0.5)
A
B
C (±0.1)
C
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 41. PowerSSO-24TM tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C (± 0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
35/38
Order codes
6
VND5050AJ-E / VND5050AK-E
Order codes
Table 16.
Device summary
Order codes
Package
36/38
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12
VND5050AJ-E
VND5050AJTR-E
PowerSSO-24
VND5050AK-E
VND5050AKTR-E
VND5050AJ-E / VND5050AK-E
7
Revision history
Revision history
Table 17.
Document revision history
Date
Revision
Changes
30-Mar-2006
1
Initial release.
14-Apr-2006
2
PowerSSO-24 dimensions table update.
26-Apr-2007
3
Reformatted
Figure 31 title corrected
14-May-2007
4
Table 3 : corrected EMAX value.
Table 9 : added dk1/k1, dk2/k2, dk3/k3, ∆tDSENSE2H .
Added Figure 5.
Updated Figure 6.
Added Figure 7.
Table 11 : Updated test level values III and IV for test pulse 5b and
notes.
Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V).
01-Jun-2007
5
Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-12™, Figure 35: Thermal fitting model of a double channel
HSD in PowerSSO-24™: added notes.
4-Dec-2007
6
Updated Table 9: Current sense (8V<VCC<16V) :
– changed tDSENSE2H max value from 300 µs to 250µs.
– added IOL parameter.
Updated Section 4.1: PowerSSO-12™ thermal data:
– changed Figure 29: Rthj-amb Vs. PCB copper area in open box free
air condition (one channel ON).
– changed Figure 30: PowerSSO-12™ thermal impedance junction
ambient single pulse (one channel ON).
– updated Table 12: PowerSSO-12™ thermal parameter:
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
12-Feb-2008
7
Corrected typing error in Table 9: Current sense (8V<VCC<16V) :
changed IOL test condition from VIN = 0V to VIN = 5V.
37/38
VND5050AJ-E / VND5050AK-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
38/38