VND5T100AJ-E
Double channel high-side driver with analog current sense
for 24 V automotive applications
Features
Max transient supply voltage
VCC
58 V
Operating voltage range
VCC
8 to 36 V
Typ on-state resistance (per ch.)
RON
100 mΩ
Current limitation (typ)
ILIM
22 A
Off-state supply current
IS
2 µA(1)
1. Typical value with all loads connected.
■
■
■
General
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– Compliance with European directive
2002/95/EC
– Fault reset standby pin (FR_Stby)
Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Off-state open-load detection
– Output short to VCC detection
– Overload and short to ground latch-off
– Thermal shutdown latch-off
– Very low current sense leakage
Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shutdown
– Electrostatic discharge protection
March 2011
PowerSSO-12
Application
All types of resistive, inductive and capacitive
loads
Description
The VND5T100AJ-E is a monolithic device made
using STMicroelectronics™ VIPower™
technology, intended for driving resistive or
inductive loads with one side connected to
ground. Active VCC pin voltage clamp protects the
device against low energy spikes.
This device integrates an analog current sense
which delivers a current proportional to the load
current.
Fault conditions such as overload,
overtemperature or short to VCC are reported via
the current sense pin.
Output current limitation protects the device in
overload condition. The device latches off in case
of overload or thermal shutdown.
The device is reset by a low level pass on the fault
reset standby pin.
A permanent low level on the inputs and fault
reset standby pin disables all outputs and sets the
device in standby mode.
Doc ID 018513 Rev 1
1/32
www.st.com
1
Contents
VND5T100AJ-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
4
3.1.1
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4
Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
Doc ID 018513 Rev 1
VND5T100AJ-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current sense (8 V < VCC < 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 018513 Rev 1
3/32
List of figures
VND5T100AJ-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
4/32
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Tstandby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Treset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output stuck to VCC detection delay time at FRSTBY activation . . . . . . . . . . . . . . . . . . . . 15
Delay response time between rising edge of output current and rising edge of current
sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24
PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 25
Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 25
PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 018513 Rev 1
VND5T100AJ-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
9&&
6LJQDO&ODPS
&RQWURO'LDJQRVWLF
8QGHUYROWDJH
,1
&RQWURO'LDJQRVWLF
3RZHU
&ODPS
'5,9(5
,1
&+
921
/LPLWDWLRQ
2YHU
7HPSHUDWXUH
&XUUHQW
/LPLWDWLRQ
2))VWDWH
2SHQORDG
)5B6WE\
96(16(+
&6
&XUUHQW
6HQVH
&+
&6
287
/2*,&
287
29(5/2$'3527(&7,21
$&7,9(32:(5/,0,7$7,21
*1'
*$3*&)7
Table 1.
Pin function
Name
VCC
Function
Battery connection
OUTn
Power output
GND
Ground connection
INn
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
CSn
Analog current sense pin, delivers a current proportional to the load current
FR_Stby
In case of latch-off for OT/overcurrent condition, a low pulse on the FR_Stby pin is
needed to reset the channel.
The device enters in standby mode if all inputs and the FR_Stby pin are low.
Doc ID 018513 Rev 1
5/32
Block diagram and pin description
Figure 2.
VND5T100AJ-E
Configuration diagram (top view)
7$% 9&&
&6
9&&
,1
287
)5B67%<
287
*1'
287
,1
287
&6
9&&
3RZHU662
*$3*&)7
Table 2.
Suggested connections for unused and not connected pins
Connection / pin Current sense
6/32
N.C.
Output
Input
FR_Stby
X
X
Floating
Not allowed
X
X
To ground
Through 10 KΩ
resistor
X
Not allowed
Doc ID 018513 Rev 1
Through
Through
10 KΩ resistor 10 KΩ resistor
VND5T100AJ-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
,6
9&&
9&&
9)Q
,287Q
,)5B6WE\
287Q
)5B6WE\
9)5B6WE\
,1Q
9287Q
,6(16(Q
,,1Q
&6Q
,1Q
96(16(Q
*1'
,*1'
1RWH9)Q 9287Q±9&&GXULQJUHYHUVHEDWWHU\FRQGLWLRQ
2.1
*$3*&)7
Absolute maximum ratings
Stressing the device above the ratings listed in Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions reported in this section for extended periods may affect device
reliability. Refer also to the STMicroelectronics™ SURE program and other relevant quality
documents.
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
58
V
-VCC
Reverse DC supply voltage
0.3
V
-IGND
DC reverse ground pin current
200
mA
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
20
A
DC input current
-1 to 10
mA
Fault reset standby DC input current
-1 to 1.5
mA
200
mA
VCC - 58 to
+VCC
V
IIN
IFR_Stby
-ICSENSE DC reverse CS pin current
VCSENSE Current sense maximum voltage
Doc ID 018513 Rev 1
7/32
Electrical specifications
Table 3.
Absolute maximum ratings (continued)
Symbol
Value
Unit
70
mJ
Maximum switching energy
(L = 1.9 mH; Vbat = 32 V; Tjstart = 150 °C; IOUT = IlimL (Typ))
VESD
Electrostatic discharge
(Human Body Model: R = 1.5 KΩ; C = 100 pF)
– INPUT
– CURRENT SENSE
– FR_STBY
– OUTPUT
– VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
40
µH
Tstg
LSmax
Maximum stray inductance in short circuit
RL = 300 mΩ, Vbat = 32 V, Tjstart = 150 °C, IOUT = IlimHmax
Thermal data
Table 4.
8/32
Parameter
EMAX
Tj
2.2
VND5T100AJ-E
Thermal data
Symbol
Parameter
Maximum value
Unit
Rthj-case
Thermal resistance junction-case (with one channel ON)
3
°C/W
Rthj-amb
Thermal resistance junction-ambient
See Figure 27
°C/W
Doc ID 018513 Rev 1
VND5T100AJ-E
2.3
Electrical specifications
Electrical characteristics
8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless otherwise specified.
Table 5.
.
Power section
Symbol
Parameter
Test conditions
Min. Typ.
Max.
Unit
24
36
V
5
V
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
3.5
VUSDhyst
Undervoltage shutdown
hysteresis
0.5
RON
Vclamp
IS
IL(off)
VF
On-state resistance(1)
8
IOUT = 1.5 A; Tj = 25 °C
100
mΩ
IOUT = 1.5 A; Tj = 150 °C
Clamp voltage
IS = 20 mA
Supply current
Off-state output current
V
200
58
64
70
V
Off-state: VCC = 24 V; Tj = 25 °C;
VIN = VOUT = VSENSE = 0 V
2(2)
5(2)
µA
On-state: VCC = 24 V; VIN = 5 V;
IOUT = 0 A
4.2
6
mA
0.01
3
VIN = VOUT = 0 V; VCC = 24 V;
Tj = 25 °C
0
VIN = VOUT = 0 V; VCC = 24 V;
Tj = 125 °C
0
µA
5
Output - VCC diode voltage -IOUT = 1.5 A; Tj = 150 °C
0.7
V
Max.
Unit
1. For each channel.
2. PowerMos leakage included
Table 6.
Switching(1)
Symbol
Parameter
Test conditions
Min.
Typ.
td(on)
Turn-on delay time
RL = 16 Ω
27
µs
td(off)
Turn-off delay time
RL = 16 Ω
38
µs
dVOUT/dt(on)
Turn-on voltage slope
RL = 16 Ω
1
V/µs
dVOUT/dt(off)
Turn-off voltage slope
RL = 16 Ω
0.65
V/µs
WON
Switching energy losses
during twon
RL = 16 Ω
0.23
mJ
WOFF
Switching energy losses
during twoff
RL = 16 Ω
0.26
mJ
1. Operating conditions: VCC = 24 V; Tj = 25 °C
Doc ID 018513 Rev 1
9/32
Electrical specifications
Table 7.
VND5T100AJ-E
Logic inputs
Symbol
Parameter
Test conditions
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current VIN = 2.1 V
VI(hyst)
VIN = 0.9 V
Input hysteresis voltage
VICL
Input clamp voltage
VFR_Stby_L
Fault_reset_standby
low level voltage
IFR_Stby_L
Low level
fault_reset_standby
current
VFR_Stby_H
Fault_reset_standby
high level voltage
IFR_Stby_H
High level
fault_reset_standby
current
VFR_Stby (hyst)
Fault_reset_standby
hysteresis voltage
VFR_Stby_CL
Fault_reset_standby
clamp voltage
Min.
Max.
Unit
0.9
V
1
µA
2.1
V
10
0.25
IIN = 1 mA
7
-0.7
µA
2.1
V
10
0.25
Overload latch-off reset
See Figure 4
time
tstby
Standby delay
See Figure 5
15
-0.7
2
24
µs
120
1200
µs
)5B6WGE\
,1387Q
,*1'
WVWE\
*$3*&)7
10/32
Doc ID 018513 Rev 1
V
V
Tstandby definition
WVWE\
µA
V
11
IFR_Stby = -1 mA
treset
V
1
VFR_Stby = 2.1 V
IFR_Stby = 15 mA (t < 10 ms)
V
V
0.9
VFR_Stby = 0.9 V
µA
V
5.5
IIN = -1 mA
Figure 4.
Typ.
VND5T100AJ-E
Electrical specifications
Figure 5.
Treset definition
7BUHVHW
)5B67%<
,1
287387
&6
2YHUORDG
&KDQQHO
*$3*&)7
Table 8.
Symbol
Protections and diagnostics
Parameter
Test conditions
IlimH
DC short circuit current
VCC = 24 V
5 V < VCC < 36 V
IlimL
Short circuit current
during thermal cycling
VCC = 24 V;
TR < Tj < TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of status
THYST
VDEMAG
VON
Min.
Typ.
Max.
Unit
16
22
30
30
A
A
6
150
175
TRS + 1
TRS + 5
A
200
135
Thermal hysteresis
(TTSD - TR)
°C
°C
°C
7
°C
Turn-off output voltage
clamp
IOUT = 1.5 A; VIN = 0;
L = 6 mH
VCC - 58 VCC - 64 VCC - 70
V
Output voltage drop
limitation
IOUT = 50 mA;
Tj = -40 °C...+ 150 °C
25
mV
Doc ID 018513 Rev 1
11/32
Electrical specifications
Table 9.
Symbol
K1
dK1/K1(1)
K2
dK2/K2(1)
K3
dK3/K3(1)
K4
dK4/K4(1)
VND5T100AJ-E
Current sense (8 V < VCC < 36 V)
Parameter
IOUT/ISENSE
IOUT = 350 mA; VSENSE = 1 V;
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
Current sense ratio IOUT = 350 mA; VSENSE = 1 V;
drift
Tj = -40 °C to 150 °C
IOUT/ISENSE
IOUT = 0.8 A; VSENSE = 2 V;
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
Current sense ratio IOUT = 0.8 A; VSENSE = 2 V;
drift
Tj = -40 °C to 150 °C
IOUT/ISENSE
IOUT = 1.5 A; VSENSE = 2 V;
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
Current sense ratio IOUT = 1.5 A; VSENSE = 2 V;
drift
Tj = -40 °C to 150 °C
IOUT/ISENSE
IOUT = 6 A; VSENSE = 4 V;
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
Current sense ratio IOUT = 6 A; VSENSE = 4 V;
drift
Tj = -40 °C to 150 °C
Min.
Typ.
Max.
930
1050
1547
1547
2185
2020
-15
1225
1310
15
1528
1528
-12
1340
1405
-8
1450
1475
%
1715
1655
8
1522
1522
%
1835
1745
12
1525
1525
Unit
%
1600
1560
-5
5
%
1
2
µA
µA
ISENSE0
Analog sense
leakage current
IOUT = 0 A; VSENSE = 0 V;
VIN = 0 V; Tj = -40 °C...150 °C
VIN = 5 V; Tj = -40 °C...150 °C
0
0
VSENSE
Max analog sense
output voltage
IOUT = 6 A; RSENSE = 3.9 KΩ
5
VSENSEH
Analog sense
output voltage in
fault condition(2)
VCC = 24 V; RSENSE = 3.9 KΩ
7.5
8.5
9.5
V
ISENSEH
Analog sense
output current in
fault condition(2)
VCC = 24 V; VSENSE = 5 V
4.9
9
12
mA
100
200
µs
Delay response
tDSENSE2H time from rising
edge of INPUT pin
12/32
Test conditions
VSENSE < 4 V, 0.07 A < IOUT < 6 A
ISENSE = 90 % of ISENSE max
(see Figure 6)
Doc ID 018513 Rev 1
V
VND5T100AJ-E
Electrical specifications
Table 9.
Current sense (8 V < VCC < 36 V) (continued)
Symbol
Parameter
Test conditions
Delay response
time between rising
edge of output
ΔtDSENSE2H
current and rising
edge of current
sense
VSENSE < 4 V,
ISENSE = 90 % of ISENSEMAX,
IOUT = 90 % of IOUTMAX
IOUTMAX = 1.5 A (see Figure 11)
Delay response
tDSENSE2L time from falling
edge of INPUT pin
VSENSE < 4 V, 0.07 A < IOUT < 6 A
ISENSE = 10 % of ISENSE max
(see Figure 6)
Min.
Typ.
5
Max.
Unit
150
µs
20
µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open-load in OFF-state condition.
Table 10.
Open-load detection
Symbol
VOL
tDSTKON
Parameter
Test conditions
Min.
Open-load off-state
voltage detection
threshold
VIN = 0 V; 8 V < VCC < 36 V;
FR_STBY = 5 V
Output short circuit to
VCC detection delay at
turn off
See Figure 6;
FR_STBY = 5 V
Output short circuit to
tDFRSTK_ON VCC detection delay at
FRSTBY activation
Max.
Unit
2
4
V
180
1800
µs
50
µs
0
µA
20
µs
See Figure 9; Input1,2 = low
IL(off2)
Off-state output current
at VOUT = 4V
VIN = 0 V; VSENSE = 0 V;
VOUT rising from 0 V to 4 V;
FR_STBY = 5 V
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
open-load
VOUT = 4 V; VIN = 0 V
VSENSE = 90 % of VSENSEH
RSENSE = 3.9 KΩ;
FR_STBY = 5 V
Figure 6.
Typ.
-120
Current sense delay characteristics
,1387
/2$'&855(17
6(16(&855(17
W'6(16(+
W'6(16(/
*$3*&)7
Doc ID 018513 Rev 1
13/32
Electrical specifications
Figure 7.
VND5T100AJ-E
Open-load off-state delay timing
2XWSXWVWXFNDW9&&
9287!92/
9,1
96(16(+
9&6
W'67.21
*$3*&)7
Figure 8.
Switching characteristics
9287
W:RQ
W:RII
G9287GWRII
G9287GWRQ
WU
WI
W
,1387
7GRQ
7GRII
W
*$3*&)7
14/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
Figure 9.
Output stuck to VCC detection delay time at FRSTBY activation
)567%<
9VHQVH+
9&6
W')567.B21
,QSXW /RZ
*$3*&)7
Figure 10. Delay response time between rising edge of output current and rising
edge of current sense
9,1
ǻW'6(16(+
W
,287
,2870$;
,2870$;
W
,6(16(
,6(16(0$;
,6(16(0$;
W
*$3*&)7
Doc ID 018513 Rev 1
15/32
Electrical specifications
Figure 11.
VND5T100AJ-E
Output voltage drop limitation
9&&9287
7M &
7M &
7M &
921
,287
9215217
$*9
Figure 12. Device behavior in overload condition
WBUHVHW
WBUHVHW
)$8/7B5(6(7
,1Q
287387Q
9VHQVH+
&6Q
RYHUORDG
RYHUORDGUHVHW
RYHUORDGGLDJUHVHW
29(5/2$'
&+$11(/Q
287387QDQG&6QFRQWUROOHGE\,QQ
)$8/7B5(6(7IURPµ¶WRµ¶ĺQRDFWLRQRQ&6QSLQ
RYHUORDGODWFKRII,QQKLJKĺ&6QKLJK
)$8/7B5(6(7ORZ$1'7HPSFKDQQHOQRYHUORDGBUHVHWĺRYHUORDGODWFKUHVHWDIWHUWBUHVHW
WR)$8/7B5(6(7ORZ$1',1QKLJKĺWKHUPDOF\FOLQJ&6QKLJK
)$8/7B5(6(7KLJKĺODWFKRIIUHVHWGLVDEOHG
WRRYHUORDGHYHQWDQG)$8/7B5(6(7KLJKĺODWFKRIIQRWKHUPDOF\FOLQJ
WRRYHUORDGGLDJQRVWLFGLVDEOHGHQDEOHGE\WKHLQSXW
RYHUORDGODWFKRIIUHVHWE\)$8/7B5(6(7
29(5/2$' WKHUPDOVKXWGRZQ25SRZHUOLPLWDWLRQ
*$3*&)7
16/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
Table 11.
Truth table
Conditions
Fault reset standby
Input
Output
Sense
Standby
L
L
L
0
Normal operation
X
X
L
H
L
H
0
Nominal
Overload
X
X
L
H
L
H
0
> Nominal
Overtemperature / short to ground
X
L
H
L
H
H
L
Cycling
Latched
0
VSENSEH
VSENSEH
Undervoltage
X
X
L
0
Short to VBAT
L
H
X
L
L
H
H
H
H
0
VSENSEH
< Nominal
Open-load off-state (with pull-up)
L
H
X
L
L
H
H
H
H
0
VSENSEH
0
Negative output voltage clamp
X
L
Negative
0
Doc ID 018513 Rev 1
17/32
Electrical specifications
Table 12.
ISO 7637-2:
2004(E)
VND5T100AJ-E
Electrical transient requirements (part 1)
Test levels (1)
Test pulse
III
IV
Number of
pulses or test
times
1
- 450 V
- 600 V
5000 pulses
0.5 s
5s
1 ms, 50 Ω
2a
+ 37 V
+ 50 V
5000 pulses
0.2 s
5s
50 µs, 2 Ω
3a
- 150 V
- 200 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+ 150 V
+ 200 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
- 12 V
- 16 V
1 pulse
100 ms, 0.01 Ω
5b (2)
+ 123 V
+ 174 V
1 pulse
350 ms, 1 Ω
Table 13.
Burst cycle/pulse
repetition time
Delays and
impedance
Electrical transient requirements (part 2)
ISO 7637-2:
2004(E)
Test level results
Test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b(1)
E
E
3b(2)
C
C
4
C
C
5b (3)
C
C
1. Without capacitor between VCC and GND.
2. With 10 nF between VCC and GND.
3. External load dump clamp, 58 V maximum, referred to ground.
Table 14.
18/32
Electrical transient requirements (part 3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 018513 Rev 1
VND5T100AJ-E
2.4
Electrical specifications
Electrical characteristics curves
Figure 13. Off-state output current
Figure 14. High level input current
)LOFF;U!=
)IH;U!=
6IN6
/FFSTATE
6##6
6IN6OUT
4C; #=
4C; #=
'!0#&4
'!0'#&4
Figure 15. Input clamp voltage
Figure 16. Input high level voltage
6IH;6=
6ICL;6=
)INM !
'!0'#&4
Figure 17. Input low level voltage
'!0'#&4
Figure 18. Input hysteresis voltage
6IHYST;6=
6IL;6=
4C; #=
4C; #=
4C; #=
4C; #=
'!0'#&4
Doc ID 018513 Rev 1
'!0'#&4
19/32
Electrical specifications
VND5T100AJ-E
Figure 19. On-state resistance vs Tcase
Figure 20. On-state resistance vs VCC
2ON;M /HM =
5RQ>P 2KP @
4C #
,RXW $
9FF 9
4C #
4C #
4C #
6CC;6=
7F>&@
'!0'#&4
("1($'5
Figure 21. ILIMH vs Tcase
Figure 22. Turn-on voltage slope
D6OUTDT/N;6US=
)LIM H;!=
6CC6
6CC6
2Lȍ
4C; #=
4C; #=
'!0'#&4
'!0'#&4
Figure 23. Turn-off voltage slope
D6OUTDT/FF;6US=
6CC6
2Lȍ
4C; #=
'!0'#&4
20/32
Doc ID 018513 Rev 1
VND5T100AJ-E
3
Application information
Application information
Figure 24. Application schematic
9
9&&
5SURW
)5B6WE\
'OG
0&8
5SURW
,1
5SURW
&6
287
*1'
56(16(
&H[W
9*1'
'*1'
*$3*&)7
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (RGND only)
This solution can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤ 600 mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0: during reverse battery situations) is:
PD = (-VCC)2 / RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift varies depending on how many devices are ON in the case of several high
side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).
Doc ID 018513 Rev 1
21/32
Application information
3.1.2
VND5T100AJ-E
Solution 2: diode (DGND) in the ground line
A resistor (RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values, if the microprocessor ground is not common to the device
ground. This shift not varies if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO T/R 7637/2 table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins are pulled negative. ST suggests that a resistor (Rprot) be inserted in line to
prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= -600 V and Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V
30 kΩ ≤ Rprot ≤ 180 kΩ.
Recommended Rprot value is 60 kΩ.
22/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Maximum demagnetization energy (VCC = 24 V)
Figure 25. Maximum turn-off current versus inductance
10
A
C
B
1
I (A)
3.4
Application information
0.1
1
10
L (mH)
100
1000
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL =0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature
specified above for curves A and B.
Doc ID 018513 Rev 1
23/32
Package and PCB thermal data
VND5T100AJ-E
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 26. PowerSSO-12 PC board
*$3*&)7
.
Note:
Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10 %; Board double layer; Board
dimension 77 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back side); Thermal vias separation
1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; Footprint dimension 4.1 mm x 6.5 mm)
Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON)
RTHjamb
65
60
55
RTHjamb
50
45
40
35
30
0
2
4
6
8
10
GAPGCFT000124
24/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Package and PCB thermal data
Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=f oot print
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
GAPGCFT000125
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-12
*$3*&)7
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power
limitation or thermal cycling during thermal shutdown) are not triggered.
Equation 1: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
δ = tp ⁄ T
Doc ID 018513 Rev 1
25/32
Package and PCB thermal data
Table 15.
26/32
VND5T100AJ-E
Thermal parameters
Area/island (cm2)
Footprint
R1 = R7 (°C/W)
0.8
R2 = R8 (°C/W)
1.5
R3 (°C/W)
3
R4 (°C/W)
2
8
8
8
7
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1 = C7 (W.s/°C)
0.0008
C2 = C8 (W.s/°C)
0.005
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
Doc ID 018513 Rev 1
VND5T100AJ-E
Package and packing information
5
Package and packing information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-12 mechanical data
Figure 30. PowerSSO-12 package dimensions
*$3*&)7
Doc ID 018513 Rev 1
27/32
Package and packing information
Table 16.
VND5T100AJ-E
PowerSSO-12 mechanical data
Millimeters
Symbol
28/32
Min.
Typ.
Max.
A
1.250
-
1.620
A1
0.000
-
0.100
A2
1.100
-
1.650
B
0.230
-
0.410
C
0.190
-
0.250
D
4.800
-
5.000
E
3.800
-
4.000
e
-
0.800
-
H
5.800
-
6.200
h
0.250
-
0.500
L
0.400
-
1.270
k
0°
-
8°
X
2.200
-
2.800
Y
2.900
-
3.500
ddd
-
-
0.100
Doc ID 018513 Rev 1
VND5T100AJ-E
5.3
Package and packing information
Packing information
Figure 31. PowerSSO-12 tube shipment (no suffix)
All dimensions are in mm.
B
C
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
A
100
2000
532
1.85
6.75
0.6
GA P GC FT000123
Figure 32. PowerSSO-12 tape and reel shipment (suffix “TR”)
Reel dimensions
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
Doc ID 018513 Rev 1
29/32
Order code
6
VND5T100AJ-E
Order code
Table 17.
Device summary
Order codes
Package
PowerSSO-12
30/32
Tube
Tape and reel
VND5T100AJ-E
VND5T100AJTR-E
Doc ID 018513 Rev 1
VND5T100AJ-E
7
Revision history
Revision history
Table 18.
Document revision history
Date
Revision
08-Mar-2011
1
Changes
Initial release.
Doc ID 018513 Rev 1
31/32
VND5T100AJ-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2011 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
32/32
Doc ID 018513 Rev 1