STE45NK80ZD N-channel 800V - 0.11Ω - 45A ISOTOP SuperFREDmesh™ MOSFET General features Type VDSS RDS(on) ID Pw STE45NK80ZD 800V <0.13Ω 45A 600W ■ Extremely high dv/dt capability ■ 100% avalanche tested ■ Very low intrinsic capacitances ■ Very good manufacturing repeatibility ISOTOP Description The SuperFREDMesh™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STE45NK80ZD E45NK80ZD ISOTOP Tube June 2006 Rev 7 1/13 www.st.com 13 Contents STE45NK80ZD Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Electrical characteristics (curves) ............................ 7 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STE45NK80ZD 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol VDS VDGR VGS Parameter Value Unit Drain-source voltage (VGS = 0) 800 V Drain-gate voltage (RGS = 20 kW) 800 V Gate- source voltage ± 30 V ID Drain Current (continuous) at TC = 25°C (Steady State) 45 A A ID Drain Current (continuous) at TC = 100°C 28 A Drain Current (pulsed) 180 A PTOT Total Dissipation at TC = 25°C (steady state) 600 W PTOT Derating factor 5 W/°C 7 KV 8 V/ns 2500 V - 65 to 150 °C Rthj-case Thermal Resistance Junction-case Max 0.2 °C/W Rthj-amb 40 °C/W Value Unit IDM (1) VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5kW) dv/dt (2) Peak diode recovery voltage slope VISO Insulation withstand voltage (AC-RMS) from all four terminals to external heatsink Tj Tstg Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area 2. ISD ≤45A, di/dt £ 500 A/µs, VDD ≤V(BR)DSS. Table 2. Table 3. Symbol Thermal data Thermal Resistance Junction-ambient Max Avalanche characteristics Parameter IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 45 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 1.2 J 3/13 Electrical characteristics 2 STE45NK80ZD Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol On/off states Parameter Test conditions Min. Typ. Max. Unit Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 10 100 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 150µA 3.75 4.5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 22.5 A 0.11 0.13 Ω Typ. Max. Unit V(BR)DSS Table 5. Symbol 800 2.5 V Dynamic Parameter Test conditions Min. gfs (1) Forward transconductance VDS = 15V, ID = 22.5 A 35 S Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V, f = 1 MHz, VGS = 0 26000 1620 260 pF pF pF Coss eq. (2) Equivalent output capacitance VGS = 0V, VDS = 0V to 720V 700 pF td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 400 V, ID = 20 A RG = 4.7Ω ,VGS = 10 V (see Figure 18) 105 128 350 174 ns ns ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 400 V, ID = 40 A, VGS = 10V 558 121 307 781 nC nC nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 4/13 STE45NK80ZD Electrical characteristics Table 6. Symbol Source drain diode Parameter ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD trr Qrr IRRM trr Qrr IRRM Test conditions Min. Typ. ISD = 45 A, VGS = 0 Max. Unit 45 180 A A 1.6 V Reverse recovery time I = 40 A, di/dt = 100A/µs Reverse recovery charge SD VDD = 50 V, Tj = 25°C Reverse recovery current 375 4.65 24.8 ns µC A Reverse recovery time I = 40 A, di/dt = 100A/µs Reverse recovery charge SD VDD = 50 V, Tj = 150°C Reverse recovery current 568 9.66 34 ns µC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Table 7. Symbol BVGSO 2.1 Gate-source zener diode Parameter Test Conditions Gate-source breakdown Igs=± 1mA voltage (open drain) Min. Typ. 30 Max. Unit V Protection features of gate-to-source zener diodes The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 5/13 Electrical characteristics STE45NK80ZD 2.2 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/13 STE45NK80ZD Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized BVDSS vs temperature 7/13 Electrical characteristics Figure 13. Avalanche energy vs starting Tj 8/13 STE45NK80ZD STE45NK80ZD 3 Test circuit Test circuit Figure 14. Unclamped Inductive load test circuit Figure 15. Unclamped inductive waveform Figure 16. Switching times test circuit for resistive load Figure 17. Gate charge test circuit Figure 18. Test circuit for inductive load switching and diode recovery times 9/13 Package mechanical data 4 STE45NK80ZD Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/13 STE45NK80ZD Package mechanical data ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 11.8 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.157 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 N 4 O 7.8 0.157 8.2 0.307 0.322 A G B O F E H D N J K C L M 11/13 Revision history 5 STE45NK80ZD Revision history Table 8. 12/13 Document revision history Date Revision Changes 24-May-2005 1 First Release 10-Jun-2005 2 Inserted new row in Table 6.: Switching times 28-Sep-2005 3 Complete version 14-Oct-2005 4 Modified Figure 3, Figure 6 06-Mar-2006 5 New Stylesheet 29-Mar-2006 6 Modified value on Table 4. 27-Jun-2006 7 New template, no content change STE45NK80ZD Please Read Carefully: Information in this document is provided solely in connection with ST products. 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