TSM12N02 N-Channel Enhancement Mode MOSFET VDS = 20V Pin assignment: 1. Gate 2. Drain 3. Source ID = 12A RDS (on), Vgs @ 10V, Ids@8A = 30mΩ RDS (on), Vgs @ 4.5V, Ids@6A = 40mΩ Features Low gate charge High Density Cell Design for Ultra Low On-Resistance Advanced trench process technology Block Diagram Fully Characterized Avalanche Voltage and Current High performance technology for low RDS(ON) Fast switching speed Ordering Information Part No. Packing Package TSM12N02CP Tape & Reel TO-252 Absolute Maximum Rating (TA = 25 oC unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS 20 V Gate-Source Voltage VGS ±12 V Continuous Drain Current ID 12 Pulsed Drain Current IDM 30 o Maximum Power Dissipation TA = 25 C o TA = 100 C Operating Junction Temperature PD 1.3 W 2 W/ C o +150 o C TJ, TSTG -55 to +150 o C Symbol Limit Unit TL 10 S Rθjc 2.2 Rθja 50 TJ Operating Junction and Storage Temperature Range A Thermal Performance Parameter Lead Temperature (1/8” from case) Junction-to-case Thermal Resistance Junction to Ambient Thermal Resistance (PCB mounted) Note: 1. Maximum DC current limited by the package 2 2. 1-in 2oz Cu PCB board TSM12N02 1-3 2006/05 rev. A o C/W Electrical Characteristics o TJ = 25 C, unless otherwise noted Parameter Conditions Symbol Min Typ Max Unit Static Drain-Source Breakdown Voltage VGS = 0V, ID = 250uA BVDSS 20 -- -- V Drain-Source On-State Resistance VGS = 10V, ID = 8A RDS(ON) -- 21 30 mΩ Drain-Source On-State Resistance VGS = 4.5V, ID = 6A RDS(ON) -- 30 40 mΩ Gate Threshold Voltage VDS = VGS, ID = 250uA VGS(TH) 0.6 -- -- V Zero Gate Voltage Drain Current VDS = 20V, VGS = 0V IDSS -- -- 1.0 uA Gate Body Leakage VGS = ±12V, VDS = 0V IGSS -- -- ±100 nA Forward Transconductance VDS =10V, ID = 6A gfs 7 13 -- S Qg -- 7.1 -- Qgs -- 1.96 -- Qgd -- 2.94 -- td(on) -- 4.9 -- tr -- 2.6 -- td(off) -- 15.7 -- tf -- 14 -- Ciss -- 620 -- Coss -- 124 -- Crss -- 95 -- IS -- -- 1.7 A VSD -- -- 1.2 V Dynamic Total Gate Charge Gate-Source Charge VDS = 10V, ID = 6A, VGS = 4.5V Gate-Drain Charge Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time VDD = 10V, RL = 10Ω, ID = 1A, V GEN = 4.5V, RG = 6Ω Turn-Off Fall Time Input Capacitance Output Capacitance VDS = 10V, VGS = 0V, f = 1.0MHz Reverse Transfer Capacitance nC nS pF Source-Drain Diode Max. Diode Forward Current Diode Forward Voltage IS = 1.7A, V GS = 0V Note: 1. pulse test: pulse width <=300uS, duty cycle <=2% 2. Negligible, Dominated by circuit inductance. TSM12N02 2-3 2006/05 rev. A TO-252 Mechanical Drawing J E J E AA F TO-252 DIMENSION F DIM I I B B G DD TSM12N02 C C H 3-3 H MILLIMETERS MIN INCHES MAX MIN MAX A 6.570 6.840 0.259 0.269 B 9.250 10.400 0.364 0.409 C 0.550 0.700 0.022 0.028 D 2.560 2.670 0.101 0.105 E 2.300 2.390 0.090 0.094 F 0.490 0.570 0.019 0.022 GG 1.460 1.580 0.057 0.062 H 0.520 0.570 0.020 0.022 I 5.340 5.550 0.210 0.219 J 1.460 1.640 0.057 0.065 2006/05 rev. A