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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
K9K8G08U0B
K9WAG08U1B
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Document Title
1G x 8 / 2G x 8 Bit NAND Flash Memory
Revision History
Revision No
History
Draft Date
Remark
0.0
1. Initial issue
Jun. 11, 2008
Advance
0.1
1. K9K8G08U0B-P is added.
Jul. 10, 2008
Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
1G x 8 / 2G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
Organization
2.70 ~ 3.60V
X8
K9K8G08U0B-P
K9WAG08U1B-P
K9WAG08U1B-I
PKG Type
TSOP1
52ULGA
FEATURES
• Voltage Supply
- 3.3V (2.70V ~ 3.60V)
• Organization
- Memory Cell Array :
- K9K8G08U0B : (1G + 32M) x 8bit
- K9WAG08U1B : (2G + 64M) x 8bit
- Data Register : (2K + 64) x 8bit
• Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
• Page Read Operation
- Page Size : (2K + 64)Byte
- Random Read : 25µs(Max.)
- Serial Access : 25ns(Min.)
• Fast Write Cycle Time
- Page Program time : 200µs(Typ.)
- Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles(with 1bit/528Byte
ECC)
- Data Retention : 10 Years
• Command Driven Operation
• Unique ID for Copyright Protection
• Package :
- K9K8G08U0B-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9WAG08U1B-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9WAG08U1B-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.0 mm pitch)
GENERAL DESCRIPTION
Offered in 1G x 8bit, the K9K8G08U0B is a 8G-bit NAND Flash Memory with spare 256M-bit. And the K9WAG08U1B is a 16G-bit
NAND Flash Memory with spare 512M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in
typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as
the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase
functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems
can take advantage of the K9K8G08U0B/K9WAG08U1B′s extended reliability of 100K program/erase cycles by providing ECC(Error
Correcting Code) with real time mapping-out algorithm. The K9K8G08U0B/K9WAG08U1B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
PIN CONFIGURATION (TSOP1)
K9K8G08U0B-PCB0/PIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin TSOP1
Standard Type
12mm x 20mm
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
0.50
0.0197
12.40
0.488 MAX
( 0.25 )
0.010
#1
12.00
0.472
+0.003
0.008-0.001
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
+0.075
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
18.40±0.10
0.724±0.004
0.125 0.035
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.05
0.002 MIN
1.20
0.047MAX
( 0.50 )
0.020
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
PIN CONFIGURATION (TSOP1)
K9WAG08U1B-PCB0/PIB0
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin TSOP1
Standard Type
12mm x 20mm
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
0.50
0.0197
12.40
0.488 MAX
( 0.25 )
0.010
#1
12.00
0.472
+0.003
0.008-0.001
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
+0.075
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
18.40±0.10
0.724±0.004
0.125 0.035
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.05
0.002 MIN
1.20
0.047MAX
( 0.50 )
0.020
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
PIN CONFIGURATION (ULGA)
K9WAG08U1B-ICB0/IIB0
A
C
B
NC
E
D
G
F
H
NC
NC
L
K
J
M
NC
NC
N
NC
7
NC
6
/RE1
Vcc
IO7-2
R/B2
IO6-2
IO7-1
Vss
/RE2
NC
IO5-2
IO5-1
Vcc
5
4
/CE1
3
2
CLE1
/CE2
R/B1
CLE2
/WE1
ALE2
Vss
1
NC
ALE1
NC
NC
IO6-1
/WP2
IO0-1
/WP1
IO2-1
IO1-1
IO0-2
/WE2
IO4-1
Vss
IO3-2
Vss
IO3-1
NC
IO2-2
IO1-2
NC
NC
NC
IO4-2
NC
PACKAGE DIMENSIONS
52ULGA (measured in millimeters)
Bottom View
Top View
12.00±0.10
10.00
1.00
1.00
2.00
7
(Datum A)
6
5
4
3
2
1
B
1.00
1.00
1.30
12.00±0.10
A
#A1
A
B
C
1.00
2.50
17.00±0.10
E
F
1.00
H
1.00
2.50
G
J
2.00
K
12.00
17.00±0.10
D
(Datum B)
0.50
L
M
N
Side View
17.00±0.10
41-∅0.70±0.05
∅0.1
M C AB
1.0(Max.)
12-∅1.00±0.05
∅0.1 M C AB
0.10 C
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
PIN DESCRIPTION
Pin Name
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE / CE1
CHIP ENABLE
The CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is
ignored, and the device does not return to standby mode in program or erase operation.
Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation.
CE2
CHIP ENABLE
The CE2 input enables the second of K9WAG08U1B.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
R/B / R/B1
READY/BUSY OUTPUT
The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program,
erase or random read operation is in process and returns to high state upon completion. It is an open drain
output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
Vcc
POWER
VCC is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Figure 1. K9K8G08U0B Functional Block Diagram
VCC
VSS
A12 - A30
X-Buffers
Latches
& Decoders
(8,192M + 256M) bit
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
(2,048 + 64)Byte x 524,288
Data Register & S/A
Y-Gating
Command
Command
Register
CE
RE
WE
VCC
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2. K9K8G08U0B Array Organization
1 Block = 64 Pages
(128K + 4k) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 8,192 Blocks
= 8,448 Mbits
512K Pages
(=8,192 Blocks)
8 bit
2K Bytes
64 Bytes
I/O 0 ~ I/O 7
Page Register
2K Bytes
I/O 0
I/O 1
64 Bytes
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
A11
*L
*L
*L
*L
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
4th Cycle
A20
A21
A22
A23
A24
A25
A26
A27
5th Cycle
A28
A29
A30
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
Column Address
Row Address :
Page Address : A12 ~ A17
Plane Address : A18
Block Address : A19 ~ the last Address
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Product Introduction
The K9K8G08U0B has a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8
columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made
up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists
of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program
and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0B.
The K9K8G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1,056M byte physical space
requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9K8G08U0B.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
The K9WAG08U1B is composed of two K9K8G08U0B chips which are selected separately by each CE1 and CE2.
Table 1. Command Sets
1st Cycle
2nd Cycle
Read
Function
00h
30h
Read for Copy Back
00h
35h
Read ID
90h
-
Reset
FFh
-
Page Program
Two-Plane Page Program(3)
Copy-Back Program
Two-Plane Copy-Back Program(3)
Block Erase
Two-Plane Block Erase
80h
10h
80h---11h
81h---10h
85h
10h
85h---11h
81h---10h
60h
D0h
60h---60h
D0h
Random Data Input(1)
85h
-
Random Data Output(1)
05h
E0h
Read Status
Acceptable Command during Busy
O
70h
O
Chip1 Status
(2)
F1h
O
Chip2 Status
(2)
F2h
O
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Interleave-operation between two chips is allowed.
It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.
3. Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Memory Map
The K9K8G08U0B is arranged in four 2Gb memory planes. Each plane contains 2,048 blocks and 2,112 byte page registers. This
allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address
map is configured so that two-plane program/erase operations can be executed by dividing the memory array into plane 0~1 or plane
2~3 separately.
For example, two-plane program/erase operation into plane 0 and plane 2 is prohibited. That is to say, two-plane program/erase operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed.
Plane 0
(2048 Block)
Block 0
Plane 3
(2048 Block)
Plane 2
(2048 Block)
Plane 1
(2048 Block)
Block 4096
Block 1
Block 4097
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
Block 2
Block 4098
Block 3
Block 4099
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
Block 4092
Block 8188
Block 4093
Block 8189
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
Block 4094
Block 8190
Block 4095
Block 8191
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
Page 62
Page 63
2112byte Page Registers
2112byte Page Registers
2112byte Page Registers
2112byte Page Registers
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
Storage Temperature
K9XXG08UXB-XCB0
Symbol
Rating
VCC
-0.6 to +4.6
VIN
-0.6 to +4.6
VI/O
-0.6 to Vcc+0.3 (<4.6V)
K9XXG08UXB-XCB0
K9XXG08UXB-XIB0
Short Circuit Current
V
-10 to +125
TBIAS
K9XXG08UXB-XIB0
Unit
°C
-40 to +125
TSTG
-65 to +150
°C
IOS
5
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9XXG08UXB-XCB0 :TA=0 to 70°C, K9XXG08UXB-XIB0:TA=-40 to 85°C)
Symbol
Min
Typ.
Max
Unit
Supply Voltage
VCC
2.7
3.3
3.6
V
Supply Voltage
VSS
0
0
0
V
Parameter
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Page Read with
Operating Serial Access
Current
Program
Erase
Symbol
ICC1
Test Conditions
ICC2
-
ICC3
-
Stand-by Current(TTL)
ISB1
CE=VIH, WP=0V/VCC
Stand-by Current(CMOS)
ISB2
Input Leakage Current
Output Leakage Current
Min
Typ
Max
-
25
35
-
-
1
Unit
tRC=25ns
CE=VIL, IOUT=0mA
CE=VCC-0.2, WP=0V/VCC
-
40
200
ILI
VIN=0 to Vcc(max)
-
-
±40
ILO
VOUT=0 to Vcc(max)
Input High Voltage
VIH(1)
Input Low Voltage, All inputs
VIL(1)
Output High Voltage Level
VOH
IOH=-400µA
Output Low Voltage Level
VOL
IOL=2.1mA
Output Low Current(R/B)
IOL(R/B)
VOL=0.4V
-
-
±40
-
0.8xVcc
-
Vcc+0.3
-
-0.3
-
0.2xVcc
2.4
-
-
-
-
0.4
8
10
-
mA
µA
V
mA
NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
2. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
3. The maximum value of K9K8G08U0B-P’s ILI and ILO is ±40µA, the maximum value of K9K8G08U0B-I’s ILI and ILO is ±20µA.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
VALID BLOCK
Parameter
Symbol
K9K8G08U0B
NVB
K9WAG08U1B
Min
Typ.
Max
8,028
-
8,192
Unit
16,064*
-
16,384*
Blocks
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9K8G08U0B chip in the K9WAG08U1B has Maximun 160 invalid blocks.
AC TEST CONDITION
(K9XXG08UXB-XCB0: TA=0 to 70°C, K9XXG08UXB-XIB0:TA=-40 to 85°C ,K9XXG08UXB: Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9WAG08U1B
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
1 TTL GATE and CL=50pF (K9K8G08U0B-P/K9WAG08U1B-I)
Output Load
1 TTL GATE and CL=30pF (K9WAG08U1B-P)
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Max
Unit
Symbol
Test Condition
Min
K9K8G08U0B
K9WAG08U1B*
Input/Output Capacitance
CI/O
VIL=0V
-
20
40
pF
Input Capacitance
CIN
VIN=0V
-
20
40
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K9WAG08U1B-IXB0’s capacitance(I/O, Input) is 20pF.
MODE SELECTION
CLE
ALE
CE
RE
WP
H
L
L
WE
H
X
L
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
X
Data Output
X
X
X
X
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
H
Mode
Read Mode
Write Mode
Command Input
Address Input(5clock)
Command Input
Address Input(5clock)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/VCC(2)
Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
12
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Program / Erase Characteristics
Symbol
Min
Typ
Max
Unit
Program Time
Parameter
tPROG
-
200
700
µs
Dummy Busy Time for Two-Plane Page Program
tDBSY
-
0.5
1
µs
Number of Partial Program Cycles
Nop
-
-
4
cycles
Block Erase Time
tBERS
-
1.5
2
ms
NOTE : 1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.
AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE Setup Time
Symbol
Min
Max
Unit
12
-
ns
CLE Hold Time
tCLH
5
-
ns
CE Setup Time
t
CS(1)
20
-
ns
tCH
5
-
ns
WE Pulse Width
tWP
12
-
ns
ALE Setup Time
tALS(1)
12
-
ns
CE Hold Time
tCLS
(1)
ALE Hold Time
tALH
5
-
ns
Data Setup Time
tDS(1)
12
-
ns
Data Hold Time
tDH
5
-
ns
Write Cycle Time
tWC
25
-
ns
tWH
10
-
ns
tADL(2)
70
-
ns
WE High Hold Time
Address to Data Loading Time
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
tR
-
25
µs
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
12
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
25
-
ns
RE Access Time
tREA
-
20
ns
CE Access Time
tCEA
-
25
ns
RE High to Output Hi-Z
tRHZ
-
100
ns
CE High to Output Hi-Z
tCHZ
-
30
ns
RE High to Output hold
tRHOH
15
-
ns
RE Low to Output hold
tRLOH
5
-
ns
CE High to Output hold
tCOH
15
-
ns
RE High Hold Time
tREH
10
-
ns
tIR
0
-
ns
RE High to WE Low
tRHW
100
-
ns
WE High to RE Low
tWHR
60
-
Device Resetting Time(Read/Program/Erase)
tRST
-
Output Hi-Z to RE Low
5/10/500
ns
(1)
µs
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)
have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)
does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on
00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 2,048. Since the initial invalid block information is also erasable in
most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the
initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following
suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update)
Initial
Invalid Block(s) Table
No
Check "FFh" at the column address 2,048
of the 1st and 2nd page in the block
Check "FFh"
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be
reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
No
Yes
No
I/O 0 = 0 ?
Yes
Program Completed
*
16
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Write 30h
Read Status Register
Read Data
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Yes
*
No
Erase Error
No
Verify ECC
Yes
I/O 0 = 0 ?
Page Read Completed
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
1
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
2
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Interleave Page Program
K9WAG08U1B is composed of two K9K8G08U0Bs. And K9K8G08U0B also is composed of two K9F4G08U0Bs. K9K8G08U0B provides interleaving operation between two K9F4G08U0Bs.
This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.
At first, the host issues page program command to one of the K9F4G08U0B chips, say K9F4G08U0B(chip #1). Due to this
K9K8G08U0B goes into busy state. During this time, K9F4G08U0B(chip #2) is in ready state. So it can execute the page program
command issued by the host.
After the execution of page program by K9F4G08U0B(chip #1), it can execute another page program regardless of the
K9F4G08U0B(chip #2). Before that the host needs to check the status of K9F4G08U0B(chip #1) by issuing F1h command. Only
when the status of K9F4G08U0B(chip #1) becomes ready status, host can issue another page program command. If the
K9F4G08U0B(chip #1) is in busy state, the host has to wait for the K9F4G08U0B(chip #1) to get into ready state.
Similarly, K9F4G08U0B chip(chip #2) can execute another page program after the completion of the previous program. The host can
monitor the status of K9F4G08U0B(chip #2) by issuing F2h command. When the K9F4G08U0B(chip #2) shows ready state, host can
issue another page program command to K9F4G08U0B(chip #2).
This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip
individually. This reduces the time lag for the completion of operation.
NOTES : During interleave operations, 70h command is prohibited.
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80h
A30 : Low
Add & Data
10h
80h
Add & Data
A
10h
busy of Chip #1
A30 : High
B
busy of Chip #2
F1h or F2h
Command
C
D
another page program on Chip #1
19
Chip 1 : Ready, Chip 2 : Busy
Chip 1 : Ready, Chip 2 : Ready
C
D
Chip 2 : Busy
Chip 1 : Busy,
B
Chip 2 : Ready
Chip 1 : Busy,
Operation
A
Status
Cxh
Cxh
8xh
8xh
F1h
Cxh
8xh
8xh
Cxh
F2h
Status Command / Data
According to the above process, the system can operate page program on chip #1 and chip #2 alternately.
State A : Chip #1 is executing a page program operation and chip #2 is in ready state. So the host can issue a page program command to chip #2.
State B : Both chip #1 and chip #2 are executing page program operation.
State C : Page program on chip #1 is terminated, but page program on chip #2 is still operating. And the system should issue F1h command to detect the status of chip
#1. If chip #1 is ready, status I/O6 is "1" and the system can issue another page program command to chip #1.
State D : Chip #1 and Chip #2 are ready.
R/B
(#2)
internal only
R/B
internal only
R/ B (#1)
I/OX
≈
≈
≈
Interleave Page Program
K9K8G08U0B
K9WAG08U1B
Advance
FLASH MEMORY
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60h
A30 : Low
Add
D0h
60h
A
D0h
busy of Chip #1
A30 : High
Add
B
busy of Chip #2
F1h or F2h
Command
C
D
another Block Erase on Chip #1
20
Chip 1 : Ready, Chip 2 : Busy
Chip 1 : Ready, Chip 2 : Ready
C
D
Chip 2 : Busy
Chip 1 : Busy,
B
Chip 2 : Ready
Chip 1 : Busy,
Operation
A
Status
Cxh
Cxh
8xh
8xh
F1h
Cxh
8xh
8xh
Cxh
F2h
Status Command / Data
According to the above process, the system can operate block erase on chip #1 and chip #2 alternately.
State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2.
State B : Both chip #1 and chip #2 are executing block erase operation.
State C : Block erase on chip #1 is terminated, but block erase on chip #2 is still operating. And the system should issue F1h command to detect the status of chip #1. If
chip #1 is ready, status I/O6 is "1" and the system can issue another block erase command to chip #1.
State D : Chip #1 and Chip #2 are ready.
R/B
(#2)
internal only
R/B
internal only
R/ B (#1)
I/OX
≈
≈
≈
Interleave Block Erase
K9K8G08U0B
K9WAG08U1B
Advance
FLASH MEMORY
Samsung Confidential
21
R/B
1
F1h or F2h*
Command
80h
11h
t DBSY
C
tPROG of Chip #2
A30 : Low
Add & Data
81h
A30 :Low
Add & Data
10h
80h
A30: High
Add & Data
11h
D
A
t DBSY
Add & Data
A30 :High
t PROG of chip #1
81h
10h
State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2.
State B : Both chip #1 and chip #2 are executing page program operation.
State C : Page program on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing page program operation.
State D : Both chip #1 and chip #2 are ready.
Note : *F1h command is required to check the status of chip #1 to issue the next page program command to chip #1.
F2h command is required to check the status of chip #2 to issue the next page program command to chip #2.
According to the above process, the system can operate two-plane page program on chip #1 and chip #2 alternately.
internal only
R/B (#2)
internal only
R/nB (#1)
I/OX
R/B
internal only
R/B (#2)
internal only
R/B (#1)
I/OX
≈ ≈
≈
tPROG of Chip #2
≈
≈
B
≈
Interleave Two-Plane Page Program
1
K9K8G08U0B
K9WAG08U1B
Advance
FLASH MEMORY
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22
1
Add
A30 : Low
F1h or F2h*
Command
60h
60h
Add
D0h
chip #2
C
tBERS of
A30 :Low
60h
Add
A30 : High
A
60h
t BERS of
D0h
chip #1
A30 :High
Add
D
B
t BERS of chip #2
State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2.
State B : Both chip #1 and chip #2 are executing block erase operation.
State C : Block erase on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing block erase operation.
State D : Both chip #1 and chip #2 are ready.
Note : *F1h command is required to check the status of chip #1 to issue the next block erase command to chip #1.
F2h command is required to check the status of chip #2 to issue the next block erase command to chip #2.
As the above process, the system can operate two-plane block erase on chip #1 and chip #2 alternatively.
R/B
internal only
R/B (#2)
internal only
R/B (#1)
I/OX
R/B
internal only
R/B (#2)
internal only
R/B (#1)
I/OX
≈≈
≈
Interleave Two-Plane Block Erase
1
K9K8G08U0B
K9WAG08U1B
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
≈
≈
CLE
≈
Figure 4. Program Operation with CE don’t-care.
I/Ox
≈
ALE
80h
Address(5Cycles)
tCS
≈
≈≈
WE
≈ ≈
≈
CE
≈ ≈
CE don’t-care
Data Input
tCH
Data Input
10h
tCEA
CE
CE
tREA
tWP
RE
WE
I/O0~7
out
≈
CLE
≈
Figure 5. Read Operation with CE don’t-care.
CE don’t-care
≈
ALE
tR
≈
R/B
≈≈
≈ ≈ ≈
RE
≈
WE
I/Ox
≈ ≈
CE
00h
Address(5Cycle)
Data Output(serial access)
30h
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
NOTE
Device
K9K8G08U0B
I/O
DATA
ADDRESS
I/Ox
Data In/Out
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
I/O 0 ~ I/O 7
2,112byte
A0~A7
A8~A11
A12~A19
A20~A27
A28~A30
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
I/Ox
Command
Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE
tWP
tWP
WE
tWH
tALH
tALS
tALS
tWP
tWP
tALH
tWH
tALS
tWH
tALH
tALS
tWH
tALH
tALS
tALH
ALE
tDS
I/Ox
tDH
Col. Add1
tDS
tDH
Col. Add2
24
tDS
tDH
Row Add1
tDS
tDH
Row Add2
tDS
tDH
Row Add3
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Input Data Latch Cycle
tCLH
≈
CLE
tCH
≈
CE
tWC
≈
ALE
tALS
tWP
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
tWP
≈
tWP
WE
I/Ox
DIN final
DIN 1
≈
DIN 0
* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tREA
tREA
≈
tREH
tCHZ
tREA
tCOH
RE
tRHZ
tRHZ
tRHOH
Dout
Dout
Dout
≈
I/Ox
≈
tRR
R/B
NOTES : Transition is measured at ± 200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
≈
CE
tRC
tCHZ
tCOH
tREH
≈
tRP
RE
tCEA
I/Ox
tRHZ
tREA
tRHOH
tRLOH
≈
tREA
Dout
≈
Dout
≈
tRR
R/B
NOTES : Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tWP
tCH
WE
tCEA
tCHZ
tCOH
tWHR
RE
tDS
I/Ox
tDH
tIR
tREA
tRHZ
tRHOH
Status Output
70h
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Read Operation
tCLR
CLE
CE
tWC
WE
tWB
tAR
ALE
tR
tRHZ
tRC
≈
RE
I/Ox
00h
Col. Add1
Col. Add2
Row Add1
Column Address
Row Add2 Row Add3
30h
Dout N
Dout N+1
Row Address
≈ ≈
tRR
Dout M
Busy
R/B
Read Operation(Intercepted by CE)
CLE
CE
WE
tWB
tCHZ
tCOH
tAR
ALE
tRC
tR
RE
tRR
I/Ox
00h
Col. Add1
Col. Add2
Column Address
Row Add1
Row Add2 Row Add3
Dout N
30h
Dout N+1
Dout N+2
Row Address
Busy
R/B
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28
R/B
I/Ox
RE
ALE
WE
CE
CLE
00h
Col. Add2
Column Address
Col. Add1
Random Data Output In a Page
Row Add2 Row Add3
Row Address
Row Add1
30h
Busy
tRR
tR
tWB
tAR
Dout N
tRC
Dout N+1
tRHW
05h
Col Add1
Col Add2
Column Address
E0h
tWHR
tCLR
Dout M
tREA
Dout M+1
K9K8G08U0B
K9WAG08U1B
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FLASH MEMORY
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Page Program Operation
CLE
CE
tWC
≈
tWC
tWC
WE
tWB
tADL
tPROG
tWHR
ALE
I/Ox
80h
Co.l Add1 Col. Add2
SerialData
Column Address
Input Command
Row Add1
≈ ≈
RE
Din
Din
N
M
1 up to m Byte
Serial Input
Row Add2 Row Add3
Row Address
70h
I/O0
Read Status
Command
≈
R/B
10h
Program
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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30
R/B
I/Ox
RE
ALE
WE
Col. Add1
Col. Add2
Row Add2 Row Add3
Row Address
Row Add1
tWC
tADL
Din
M
85h
Col. Add1
Col. Add2
Serial Input Random Data Column Address
Input Command
Din
N
tWC
tADL
Din
K
Serial Input
Din
J
NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Serial Data
Column Address
Input Command
80h
tWC
≈
≈ ≈
CE
≈
≈ ≈
CLE
10h
Program
Command
tWB
tPROG
≈
Page Program Operation with Random Data Input
Read Status
Command
70h
tWHR
I/O0
K9K8G08U0B
K9WAG08U1B
Advance
FLASH MEMORY
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R/B
I/Ox
RE
ALE
WE
CE
CLE
Column Address
Row Address
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
35h
tR
tWB
Busy
Data 1
tRC
≈ ≈
Data N
Column Address
Row Address
Data 1
tADL
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Copy-Back Data
Input Command
85h
NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
00h
tWC
≈
31
Data N
10h
tWB
70h
I/Ox
tWHR
Read Status Command
tPROG
I/O0=0 Successful Program
I/O0=1 Error in Program
Busy
≈
Copy-Back Program Operation with Random Data Input
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Block Erase Operation
CLE
CE
tWC
WE
tBERS
tWB
tWHR
ALE
RE
I/Ox
60h
Row Add1
Row Add2 Row Add3
D0h
70h
I/O 0
Row Address
Busy
Auto Block Erase
Setup Command
≈
R/B
Erase Command
Read Status
Command
32
I/O0=0 Successful Erase
I/O0=1 Error in Erase
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R/B
I/Ox
RE
ALE
WE
Din
N
≈
33
Din
M
tWB
A0 ~ A11 : Valid
A12 ~ A17 : Fixed ’Low’
: Fixed ’Low’
A18
A19 ~ A29 : Fixed ’Low’
: Valid
A30
Col Add1,2 & Row Add 1,2,3
2112 Byte Data
Address & Data Input
Note
tDBSY
typ. 500ns
max. 1µs
11h
tDBSY :
tDBSY
81h
81h
Din
N
10h
Din
M
10h
tPROG
Program Confirm
Command
(True)
tWB tPROG
A0 ~ A11 : Valid
A12 ~ A17 : Valid
: Fixed ’High’
A18
A19 ~ A29 : Valid
A30
:Must be same as previous A30
Col Add1,2 & Row Add 1,2,3
2112 Byte Data
Address & Data Input
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Note: Any command between 11h and 81h is prohibited except 70h and FFh.
I/O0~7
80h
Ex.) Two-Plane Page Program
R/B
≈ ≈
11h
Program
Page Row Address 1 up to 2112 Byte Data Command
(Dummy)
Serial Input
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Serial Data Column Address
Input Command
80h
tWC
≈
CE
≈
≈ ≈
CLE
≈
Two-Plane Page Program Operation
70h
I/O 0
Read Status Command
70h
tWHR
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Row Address
60h
tWC
D0h
tWB
Erase Confirm Command
Row Address
Row Add1 Row Add2 Row Add3
Block Erase Setup Command2
Row Add1 Row Add2 RowD0h
Add3
Block Erase Setup Command1
60h
tWC
Busy
tBERS
I/O0~7
R/B
60h
A12 ~ A17 : Fixed ’Low’
: Fixed ’Low’
A18
A19 ~ A29 : Fixed ’Low’
A30
: Valid
Row Add1,2,3
Address
60h
D0h
A12 ~ A17 : Fixed ’Low’
: Fixed ’High’
A18
A19 ~ A29 : Valid
A30
: Must be same as previous A30
Row Add1,2,3
D0h
~ A25
A9Address
Ex.) Address Restriction for Two-Plane Block Erase Operation
tBERS
70h
* For Two-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
R/B
I/OX
RE
ALE
WE
CE
CLE
Two-Plane Block Erase Operation
I/O 0
I/O 0 = 0 Successful Erase
I/O 0 = 1 Error in Erase
Read Status Command
70h
tWHR
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Read ID Operation
CLE
CE
WE
tAR
ALE
RE
tREA
I/Ox
00h
90h
Read ID Command
Address 1cycle
ECh
Device
Code
3rd cyc.
4th cyc.
5th cyc.
Maker Code Device Code
Device
Device Code(2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
K9K8G08U0B
DCh
51h
95h
58h
K9WAG08U1B
Same as K9K8G08U0B
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ID Definition Table
Description
1 Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
st
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc
Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum
Plane Number, Plane Size
3rd ID Data
Description
I/O7
I/O6
I/O5 I/O4
I/O3 I/O2
I/O1 I/O0
0
0
1
1
Internal Chip Number
1
2
4
8
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
Number of
Simultaneously
Programmed Pages
1
2
4
8
Interleave Program
Between multiple chips
Not Support
Support
Cache Program
Not Support
Support
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4th ID Data
Description
Page Size
(w/o redundant area )
1KB
2KB
4KB
8KB
Block Size
(w/o redundant area )
64KB
128KB
256KB
512KB
Redundant Area Size
( byte/512byte)
8
16
Organization
x8
x16
Serial Access Minimum
50ns/30ns
25ns
Reserved
Reserved
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
36
0
0
1
1
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5th ID Data
Description
Plane Number
1
2
4
8
Plane Size
(w/o redundant Area)
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
I/O7
I/O6 I/O5 I/O4
I/O3 I/O2
0
0
1
1
0
0
0
0
1
1
1
1
Reserved
0
37
0
0
1
1
0
0
1
1
I/O1
I/O0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
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Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 20µs(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
≈
CLE
≈
CE
≈≈
WE
≈
ALE
RE
I/Ox
tR
≈
R/B
00h
Address(5Cycle)
Data Output(Serial Access)
30h
Col. Add.1,2 & Row Add.1,2,3
Data Field
Spare Field
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Figure 7. Random Data Output In a Page
tR
R/B
RE
I/Ox
Address
5Cycles
00h
Data Output
30h
05h
Col. Add.1,2 & Row Add.1,2,3
Address
2Cycles
E0h
Data Output
Col. Add.1,2
Data Field
Data Field
Spare Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive
bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential
order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into
the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
tPROG
R/B
"0"
I/Ox
80h
Address & Data Input
10h
70h
Pass
I/O0
Col. Add.1,2 & Row Add.1,2,3
"1"
Data
Fail
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Figure 9. Random Data Input In a Page
tPROG
R/B
"0"
I/Ox
Address & Data Input
80h
Address & Data Input
85h
10h
Col. Add.1,2
Data
Col. Add.1,2 & Row Add1,2,3
Data
Pass
I/O0
70h
"1"
Fail
Copy-Back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is
improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to
the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with
the destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte
data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error,
the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command
(85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once
the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When
the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10 & Figure 11). The command register
remains in Read Status command mode until another valid command is written to the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11.
Figure 10. Page Copy-Back Program Operation
tR
tPROG
≈
R/B
00h
Add.(5Cycles)
Data Output
35h
≈
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Source Address
85h
Add.(5Cycles)
10h
70h
I/O0
Col. Add.1,2 & Row Add.1,2,3
Destination Address
"0"
Pass
"1"
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
Fail
Figure 11. Page Copy-Back Program Operation with Random Data Input
≈
R/B
00h
Add.(5Cycles)
35h
Col. Add.1,2 & Row Add.1,2,3
Source Address
Data Output
≈
I/Ox
tPROG
tR
85h
Add.(5Cycles)
Data
Col. Add.1,2 & Row Add.1,2,3
Destination Address
40
85h
Add.(2Cycles)
Data
10h
70h
Col. Add.1,2
There is no limitation for the number of repetition.
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BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A18 to A30 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
tBERS
R/B
"0"
I/Ox
60h
Address Input(3Cycle)
70h
D0h
Pass
I/O0
"1"
Row Add 1,2,3
Fail
Two-Plane Page Program
Two-Plane Page Program is an extension of Page Program, for a single plane with 2,112 byte page registers. Since the device is
equipped with four memory planes, activating the two sets of 2,112 byte page registers enables a simultaneous programming of two
pages. But there is some restriction, two-plane program operations can be executed by dividing the memory array into plane 0~1 or
plane 2~3 separately. For example, two-plane program operation into plane 0 and plane 2 is prohibited. That is to say, two-plane program operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed.
After writing the first set of data up to 2,112 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved,
R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device
returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the
81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy
Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the
same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when
the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails.
Restriction in addressing with Two-Plane Page Program is shown is Figure13.
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Figure 13. Two-Plane Page Program
tDBSY
R/B
I/O0 ~ 7
Address & Data Input
80h
11h
Note2
tPROG
81h
A0 ~ A11 : Valid
A12 ~ A17 : Fixed ’Low’
A18
: Fixed ’Low’
A19 ~ A29 : Fixed ’Low’
A30
: Valid
Address & Data Input
70h
10h
A0 ~ A11 : Valid
A12 ~ A17 : Valid
A18
: Fixed ’High’
A19 ~ A29 : Valid
A30
: Must be same as previous A30
NOTE : 1. It is noticeable that same row address except for A18 is applied to the two blocks
2. Any command between 11h and 81h is prohibited except 70h and FFh.
80h
Data
Input
11h
81h
10h
Plane 0
(2048 Block)
Plane 1
(2048 Block)
Block 0
Block 1
Block 2
Block 3
Block 4092
Block 4094
Block 4093
Block 4095
NOTE : It is an example for two-plane page program into plane 0~1(In this case, A30 is low), and the method for two-plane page program into
plane 2 ~3 is same. two-plane page program into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.
Two-Plane Block Erase
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by
three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.
The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/
Busy status bit (I/O 6).
Two-plane erase operations can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately.
For example, two-plane erase operation into plane 0 and plane 2 is prohibited. That is to say, two-plane erase operation into plane 0
and plane 1 or into plane 2 and plane 3 is allowed.
Figure 14. Two-Plane Block Erase Operation
tBERS
R/B
I/OX
60h
Address (3 Cycle)
A12 ~ A17 : Fixed ’Low’
:Fixed ’Low’
A18
A19 ~ A29 : Fixed ’Low’
A30
: Valid
60h
Address (3 Cycle)
D0h
70h
A12 ~ A17 : Fixed ’Low’
: Fixed ’High’
A18
A19 ~ A29 : valid
A30
: Must
must be same as previous A30
I/O 0
"0"
Pass
"1"
Fail
NOTE : Two-plane block erase into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.
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Two-Plane Copy-Back Program
Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2,112 byte page registers. Since the
device is equipped with four memory planes, activating the two sets of 2,112 byte page registers enables a simultaneous programming of two pages.
Figure 15. Two-Plane Copy-Back Program Operation
35h
00h
Data Output
Col. Add.1,2 & Row Add.1,2,3
Source Address On Plane0
Add.(5Cycles)
35h
I/Ox
Add.(5Cycles)
85h
1
11h
Data Output
Col. Add.1,2 & Row Add.1,2,3
Source Address On Plane1
Note2
1
tPROG
tDBSY
R/B
≈
Add.(5Cycles)
≈
00h
≈
I/Ox
tR
≈
tR
R/B
Add.(5Cycles)
81h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
A0 ~ A11 : Fixed ’Low’
A12 ~ A17 : Fixed ’Low’
A18
: Fixed ’Low’
A19 ~ A29 : Fixed ’Low’
A30
: Valid
10h
70h/F1h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
A0 ~ A11 : Fixed ’Low’
A12 ~ A17 : Valid
A18
: Fixed ’High’
A19 ~ A29 : Valid
A30
: Must be same as previous A30
Plane0
Plane1
Source page
Source page
Target page
(1)
Data Field
(1) : Read for Copy Back On Plane0(or Plane2)
(2) : Read for Copy Back On Plane1(or Plane3)
Target page
(3)
(2)
Spare Field
(3) : Two-Plane Copy-Back Program
(3)
Data Field
Spare Field
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd address page(target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
3. Two-plane copy-back page program into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.
4. Any command between 11h and 81h is prohibited except 70h and FFh.
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Figure 16. Two-Plane Copy-Back Program Operation with Random Data Input
≈
Add.(5Cycles)
35h
Col. Add.1,2 & Row Add.1,2,3
Source Address On Plane0
Data Output
00h
Add.(5Cycles)
Data Output
35h
≈
00h
≈
I/Ox
tR
≈
tR
R/B
Col. Add.1,2 & Row Add.1,2,3
Source Address On Plane1
1
tDBSY
R/B
I/Ox
85h
Add.(5Cycles)
Data
85h
Col. Add.1,2 & Row Add.1,2,3
1
Add.(2Cycles)
Data
11h
Note4
Col. Add.1,2
Destination Address
2
A0 ~ A11 : Valid
A12 ~ A17 : Fixed ’Low’
A18
: Fixed ’Low’
A19 ~ A29 : Fixed ’Low’
A30
: Valid
tPROG
R/B
I/Ox
81h
2
Add.(5Cycles)
Data
85h
Col. Add.1,2 & Row Add.1,2,3
Add.(2Cycles)
Data
10h
Col. Add.1,2
Destination Address
A0 ~ A11 : Valid
A12 ~ A17 : Valid
A18
: Fixed ’High’
A19 ~ A29 : Valid
A30
: Must be same as previous A30
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd address page(target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
3. Any command between 11h and 81h is prohibited except 70h and FFh.
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K9K8G08U0B
K9WAG08U1B
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to Table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table 2. Status Register Definition for 70h Command
I/O
Page Program
Block Erase
Read
Definition
I/O 0
Pass/Fail
Pass/Fail
Not use
Pass : "0"
I/O 1
Not use
Not use
Not use
Don’t -cared
I/O 2
Not use
Not use
Not use
Don’t -cared
I/O 3
Not Use
Not Use
Not Use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Don’t -cared
Don’t -cared
I/O 5
Not Use
Not Use
Not Use
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Busy : "0"
I/O 7
Write Protect
Write Protect
Write Protect
Protected : "0"
Fail : "1"
Ready : "1"
Not Protected : "1"
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
2. Status Register Definition for F1h & F2h command is same as that of 70h command.
Table 3. Read Status Register Definition for F1h/F2h Command
I/O No.
Page Program
Block Erase
Read
Definition
I/O 0
Chip Pass/Fail
Chip Pass/Fail
Not use
Pass : "0"
Fail : "1"
I/O 1
Plane0 Pass/Fail
Plane0 Pass/Fail
Not use
Pass : "0"
Fail : "1"
I/O 2
Plane1 Pass/Fail
Plane1 Pass/Fail
Not use
Pass : "0"
Fail : "1"
I/O 3
Not Use
Not Use
Not Use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Don’t -cared
Don’t -cared
I/O 5
Not Use
Not Use
Not Use
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Busy : "0"
I/O 7
Write Protect
Write Protect
Write Protect
Protected : "0"
Ready : "1"
Not Protected : "1"
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 17 shows the operation sequence.
Figure 17. Read ID Operation
tCLR
CLE
tCEA
CE
WE
tAR
ALE
tWHR
RE
I/OX
90h
00h
tREA
ECh
Maker code
Address. 1cycle
Device
Code
3rd Cyc.
4th Cyc.
5th Cyc.
Device code
Device
Device Code(2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
K9K8G08U0B
DCh
51h
95h
58h
K9WAG08U1B
Same as K9K8G08U0B
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 18
below.
Figure 18. RESET Operation
tRST
R/B
I/OX
FFh
Table 4. Device Status
Operation mode
After Power-up
After Reset
00h Command is latched
Waiting for next command
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.19). Its value can be
determined by the following guidance.
Rp
VCC
ibusy
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Figure 19. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
2.4
200
tr,tf [s]
2m
Ibusy [A]
Ibusy
200n
150
1.2
100
100n
1m
0.8
tr
0.6
50
3.6
1K
tf
3.6
3.6
2K
3K
Rp(ohm)
4K
3.6
Rp value guidance
Rp(min, 3.3V part) =
3.2V
VCC(Max.) - VOL(Max.)
=
IOL + ΣIL
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
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FLASH MEMORY
K9K8G08U0B
K9WAG08U1B
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to be
kept at VIL during power-up and power-down. A recovery time of minimum 100µs is required before internal circuit gets ready for any
command sequences as shown in Figure 20. The two step command sequence for program/erase provides additional software protection.
≈
Figure 20. AC Waveforms for Power Transition
~ 2.3V
~ 2.3V
VCC
≈
High
≈
WP
WE
≈
Don’t care
Operation
5 ms max
100µs
≈
Ready/Busy
Invalid
Don’t care
Note :During the initialization, the device consumes a maximum current of 30mA (ICC1)
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