TPD4E001 SLLS682F – JULY 2006 – REVISED MAY 2011 www.ti.com 4-CHANNEL ESD PROTECTION ARRAY WITH 1.5-pF IO CAPACITANCE Check for Samples: TPD4E001 FEATURES • 1 • 2 • • • • • • • 4-Channel ESD Clamp Array to Enhance System-Level ESD Protection Exceeds IEC61000-4-2 (Level 4) ESD Protection Requirements – ±8-kV IEC 61000-4-2 Contact Discharge – ±15-kV IEC 61000-4-2 Air-Gap Discharge ±15-kV Human-Body Model (HBM) 5.5-A Peak Pulse Current (8/20-us Pulse) Low 1.5-pF Input Capacitance Low 1-nA (Max) Leakage Current 0.9-V to 5.5-V Supply-Voltage Range Space-Saving DRL, DBV, DCK, and DRS Package Options Alternate 2-, 3-, 6-Channel Options Available: TPD2E001, TPD3E001, and TPD6E001 APPLICATIONS • • • • • USB 2.0 Ethernet FireWire™ Precision Analog Interface SVGA Connections DESCRIPTION/ORDERING INFORMATION The TPD4E001 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND. The TPD4E001 protects against ESD pulses up to ±15-kV Human-Body Model (HBM), ±8-kV Contact Discharge, and ±15-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a 1.5-pF IO capacitance per channel, making it ideal for use in high-speed data IO interfaces. The ultra low leakage current (<1 nA max) is suitable for precision analog measurements in applications like glucose meters, heart rate monitors, etc. The TPD4E001 is available in DRL, DBV (SOT-23), DCK (SC-70), and DRS (QFN) packages and is specified for –40°C to 85°C operation. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING 1.6 × 1.6 DRL Reel of 4000 TPD4E001DRLR 2CR 2.9 × 2.8 DBV (SOT-23) Reel of 3000 TPD4E001DBVR NFY5 2.1 × 2.0 DCK (SC-70) Reel of 3000 TPD4E001DCKR 2CF 3 × 3 DRS (QFN) Reel of 1000 TPD4E001DRSR ZWM For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV/DCK PACKAGE (TOP VIEW) DRL PACKAGE (TOP VIEW) IO1 1 6 VCC IO2 2 5 IO4 GND 3 4 QFN PACKAGE (TOP VIEW) IO1 1 6 IO4 GND 2 5 VCC IO2 3 4 IO3 IO3 IO1 1 IO2 2 6 VCC 5 IO4 4 IO3 GND GND 3 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FireWire is a trademark of Apple Computer, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2011, Texas Instruments Incorporated TPD4E001 SLLS682F – JULY 2006 – REVISED MAY 2011 www.ti.com Figure 1. FUNCTIONAL BLOCK DIAGRAM VCC IO1 IO3 IO2 IO4 GND PIN DESCRIPTION DRS/DRL NO. DBV/DCK NO. 1, 2, 4, 5 1, 3, 4, 6 IOx 3 2 GND Ground 6 5 VCC Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor. N/A Exposed thermal pad. Connect to GND or leave floating. Exposed Thermal Pad (DRS package only) NAME FUNCTION ESD-protected channel Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX –0.3 7 UNIT V VI/O IO voltage tolerance –0.3 VCC + 0.3 V Tstg Storage temperature range –65 150 °C TJ Junction temperature 150 °C Bump temperature (soldering) Lead temperature (soldering, 10 s) (1) 2 Infrared (15 s) 220 Vapor phase (60 s) 215 300 °C °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright © 2006–2011, Texas Instruments Incorporated TPD4E001 SLLS682F – JULY 2006 – REVISED MAY 2011 www.ti.com Electrical Characteristics VCC = 5 V ± 10%, TA = -40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VCC Supply voltage ICC Supply current VF Diode forward voltage IF = 10 mA 0.65 VBR Breakdown Voltage IBR = 10mA 11 Channel clamp voltage (2) VC MAX 5.5 V 1 100 nA 0.95 V 0.9 TA = 25°C, ±15-kV HBM, IF = 10 A Positive transients TA = 25°C, ±8-kV Contact Discharge (IEC 61000-4-2), IF = 24 A Positive transients TA = 25°C, ±15-kV Air-Gap Discharge (IEC 61000-4-2), IF = 45 A Positive transients Ii/o Channel leakage current Vi/o = GND to VCC Ci/o Channel input capacitance VCC = 5 V, Bias of VCC/2 (1) (2) TYP (1) UNIT V VCC + 25 –25 Negative transients VCC + 60 –60 Negative transients V VCC + 100 –100 Negative transients ±1 1.5 nA pF Typical values are at VCC = 5 V and TA = 25°C. Channel clamp voltage is not production tested ESD Protection PARAMETER TYP UNIT ±15 kV IEC 61000-4-2 Contact Discharge ±8 kV IEC 61000-4-2 Air-Gap Discharge ±15 kV Peak Pulse Current, IPK (Tp = 8/20 µs) 5.5 Amps Peak Pulse Power, PPK (Tp = 8/20 µs) 100 Watts HBM Copyright © 2006–2011, Texas Instruments Incorporated 3 TPD4E001 SLLS682F – JULY 2006 – REVISED MAY 2011 www.ti.com TYPICAL OPERATING CHARACTERISTICS IO CAPACITANCE vs IO VOLTAGE (VCC = 5.0 V) 2.20 IO Capacitance (pF) 2.00 1.80 1.60 1.40 1.20 1.00 0.00 1.00 2.00 2.50 3.00 4.00 5.00 IO Voltage (V) IO LEAKAGE CURRENT vs TEMPERATURE (VCC = 5.5 V) IO Leakage Current (pA) 1000 100 10 1 –40 25 45 65 85 Temperature (°C) 4 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 90 80 70 Current (A) 60 50 40 PPK (W) IPK (A) PEAK PULSE WAVEFORM, VCC = 5.5 V 30 Power (W) 20 10 0 5 10 15 20 25 30 Time (μs) 35 40 45 0 50 Copyright © 2006–2011, Texas Instruments Incorporated TPD4E001 SLLS682F – JULY 2006 – REVISED MAY 2011 www.ti.com APPLICATION INFORMATION VBUS 0.1 µF VCC D+ D– RT GND IO4 IO1 USB Controller D1 IO3 IO2 VBUS D+ GND D– GND Detailed Description When placed near the connector, the TPD4E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD4E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines should be followed: 1. Place the TPD4E001 solution close to the connector. This allows the TPD4E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. 2. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. 3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD4E001 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. 4. Leave the unused IO pins floating . 5. The VCC pin can be connected in two different ways: (a) If the VCC pin is connected to the system power supply, the TPD4E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD bypass. (b) If the VCC pin is not connected to the system power supply, the TPD4E001 can tolerate higher signal swing in the range up to 10V. Please note that a 0.1μF capacitor is still recommended at the VCC pin for ESD bypass. Copyright © 2006–2011, Texas Instruments Incorporated 5 TPD4E001 SLLS682F – JULY 2006 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Revision C (April 2007) to Revision D • Added DVB (SOT-23) Package and package information. .................................................................................................. 1 Changes from Revision D (December 2010) to Revision E • Page Page Added DCK (SC-70) Package to Ordering Information table. .............................................................................................. 1 Changes from Revision E (April 2011) to Revision F Page • Added Peak Pulse current and power values to ESD Protection Table. .............................................................................. 3 • Added Peak Pulse Waveform Graph to Typical Operating Characteristics. ........................................................................ 4 6 Copyright © 2006–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 3-Jun-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPD4E001DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD4E001DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD4E001DRLR ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD4E001DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD4E001DRSR ACTIVE SON DRS 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 3-Jun-2011 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPD4E001DRLR SOT DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 TPD4E001DRSR SON DRS 6 1000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD4E001DRLR SOT DRL 6 4000 202.0 201.0 28.0 TPD4E001DRSR SON DRS 6 1000 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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