TPD8E003 www.ti.com SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 8-CHANNEL ESD ARRAY FOR PORTABLE SPACE-SAVING APPLICATIONS Check for Samples: TPD8E003 FEATURES 1 • • • • • • • 8-Channel ESD Clamp Array to Enhance System-Level ESD Protection Exceeds IEC61000-4-2 (Level 4) ESD Protection Requirements – ±12-kV IEC 61000-4-2 Contact Discharge – ±15-kV IEC 61000-4-2 Air-Gap Discharge 3.5-A Peak Pulse Current (8/20-µs Pulse) ±15-kV Human-Body Model (HBM) Low Breakdown Voltage of 6 V Low Leakage Current Space-Saving Ultra-Thin, Small Outline No-Lead [WSON (DQD)] Package (0.4-mm Pitch) APPLICATIONS • • • • Keypad Touch-Screen Interface Memory Interface Docking Connector Interface DQD PACKAGE (TOP VIEW) DESCRIPTION The TPD8E003 is an array of 8 ESD clamps in a space saving SON (DQD) package. This integrated transient voltage suppressor device is designed for applications requiring system level ESD robustness. It is intended for use in sensitive equipment such as portable computers, cell phone, communication systems, and other applications. Its integrated design provides very effective and reliable protection for eight separate lines using only one package. The monolithic silicon technology of TPD8E003 offers superior matching between multiple lines over discrete ESD clamp solutions. The TPD8E003 includes an ESD protection circuitry which prevents damage to the application when subjected to ESD stress exceeding IEC 61000-4-2 (Level 4). The TPD8E003 is specified for –40°C to 85°C operation. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) WSON – DQD (2) ORDERABLE PART NUMBER L = 1.7 mm, W = 1.35 mm, H = 0.75 mm, pitch = 0.4 mm TPD8E003DQDR TOP-SIDE MARKING 65S Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. CIRCUIT SCHEMATIC 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPD8E003 SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN IO voltage tolerance IO pins MAX UNIT 6 V ºC TA Operating free-air temperature range −40 85 Tstg Storage temperature −55 155 ºC IEC 61000-4-2 Contact Discharge IO pins ±12 kV IEC 61000-4-2 Air-Gap Discharge IO pins ±15 kV Peak pulse power (tp = 8/20 µs) 55 W Peak pulse current (tp = 8/20 µs) 3.5 Amp ±15 kV Human Body Model ESD (1) IO pins Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT Vclamp Clamp voltage IIO = 2 A, IO pin to ground 10 V II Leakage current IO pin to ground 0.1 mA CIO IO capacitance VIO = 2.5 V, IO pins 12 pF ΔCIO Differential line capacitance VIO = 2.5 V, between IO pins VBR Break-down voltage IIO = 1 mA Rdyn Dynamic resistance IIO = 1 A, between IO pin and ground 2 Submit Documentation Feedback 7 9 0.1 6 pF V 1 Ω Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD8E003 TPD8E003 www.ti.com SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS Figure 1. IO Capacitance vs IO Voltage Figure 2. DC Characteristics Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD8E003 3 TPD8E003 SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 3. Peak Pulse Waveforms Figure 4. IEC Clamping Waveforms 8 kV Contact 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD8E003 TPD8E003 www.ti.com SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Figure 5. IEC Clamping Waveforms -8 kV Contact Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD8E003 5 TPD8E003 SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 www.ti.com APPLICATION INFORMATION The TPD8E003 offers eight ESD clamp circuits in a space-saving DQD package. When placed near the connector, the TPD8E003 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD8E003 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation of the ESD clamps, both during normal function and ESD events, the following layout/design guidelines should be followed: • Place the TPD8E003 solution close to the connector. This allows the TPD8E003 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. • It is recommended to employ two signal layers in the printed circuit board (PCB) to route through the eight ESD clamp terminals of the TPD8E003. • Ensure that there is proper metallization for the GND vertical interconnect access (VIA). During an ESD event, the in-rush current flows to the system GND plane through the GND VIA. Having a low-impedance path allows the current to flow quickly to GND, effectively building a robust, system-level ESD immunity. • Place the VIA under the DQD pad in locations that offer maximum flexibility in board routing. • One common set of guidelines (not restricted to all cases) – Trace width: 4 mil – VIA diameter: 6 mil – DQD package pad dimensions: 8 mil × 12 mil Figure 6. Board Layout with the TPD8E003DQDR 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD8E003 TPD8E003 www.ti.com SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 Figure 7. Top and Bottom Layer Board Layout with the TPD8E003DQDR Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD8E003 7 TPD8E003 SLLSE38A – JUNE 2010 – REVISED AUGUST 2010 www.ti.com REVISION HISTORY Changes from Original (June 2010) to Revision A • 8 Page Changed pulse timing from 8/20-ms to 8/20-µs .................................................................................................................... 1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD8E003 PACKAGE OPTION ADDENDUM www.ti.com 7-Aug-2010 PACKAGING INFORMATION Orderable Device TPD8E003DQDR Status (1) ACTIVE Package Type Package Drawing WSON DQD Pins Package Qty 8 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD8E003DQDR Package Package Pins Type Drawing WSON DQD 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 1.65 B0 (mm) K0 (mm) P1 (mm) 2.0 0.95 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD8E003DQDR WSON DQD 8 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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