Ordering number : ENA1254A Thick-Film Hybrid IC STK672-340-E Unipolar Fixed-Current Chopper (External-Excited PWM) Scheme and Built-in Phase Signal Distribution IC Two-Phase Stepping Motor Driver (Square Wave Drive) Output Current 2.2A Overview The STK672-340-E is a unipolar fixed-current chopper type 2-phase stepping motor driver hybrid IC. It features power MOSFETs in the output stage and a built-in phase signal distribution IC. The incorporation of a phase distribution IC allows the STK672-340-E to control the speed of the motor based on the frequency of an external input clock signal. It supports two types of excitation for motor control: 2-phase excitation and 1-2 phase excitation. It also provides a function for switching the motor direction. The STK672-340-E features an ENABLE pin, a function not provided in the STK672-120-E. When the ENABLE pin is set low while the clock signal is being supplied, all MOSFET devices are forced to the off state. When ENABLE is set high again later, the IC resumes operation, continuing with the prior excitation timing. Applications • Two-phase stepping motor drive in send/receive facsimile units. • Paper feed in copiers, industrial robots, and other applications that require 2-phase stepping motor drive. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 62911HKPC 5-6520/72308HKIM No.A1254-1/13 STK672-340-E Features • The motor speed can be controlled by the frequency of an external clock signal (the CLOCK pin signal). • The excitation type is switched according to the state (low or high) of the MODE pin. The mode is set to 2-phase or 1-2 phase excitation on the rising edge of the clock signal. • A motor direction switching pin (the CWB pin) is provided. • Supports Schmitt input for 2.5V High level input. • The motor current can be set by changing the Vref pin voltage. Since a 0.14Ω current detection resistor is built in, a current of 1A is set for each 0.14V of applied voltage. • The input frequency range for the clock signal used for motor speed control is 0 to 50kHz. • Supply voltage ranges: VCC = 10 to 42V, VDD = 5.0V ±5% • This IC supports motor operating currents of up to 2.2A at Tc = 105°C, and of up to 3.6A at Tc = 25°C. • Provides a function that, during clock input, forces all MOSFET devices to the off state when the ENABLE pin is set low, and then, when ENABLE is set high, resumes operation continuing with the prior excitation timing. Specifications Absolute Maximum Ratings at Tc = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage 1 VCC max No signal 52 V Maximum supply voltage 2 VDD max No signal -0.3 to +7.0 V Input voltage VIN max Logic input pins -0.3 to +7.0 V Output current IOH max VDD = 5V, CLOCK ≥ 200Hz 3.6 A Allowable power dissipation Pd max With an arbitrarily large heat sink. Per MOSFET 8 W Operating substrate temperature Tc max 105 °C Junction temperature Tj max 150 °C Storage temperature Tstg -40 to +125 °C Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Operating supply voltage 1 VCC With signals applied Operating supply voltage 2 VDD With signals applied Input voltage VIH Output current 1 IOH1 Tc=105°C, CLOCK≥200Hz Output current 2 IOH2 Tc=80°C, CLOCK≥200Hz, Ratings See the motor current (IOH) derating curve CLOCK frequency Phase driver withstand voltage Recommended operating substrate fCL VDSS Tc unit 10 to 42 V 5.0±5% V 0 to VDD V 2.2 A 2.7 A Minimum pulse width: at least 10μs 0 to 50 kHz ID=1mA (Tc=25°C) 100min V 0 to 105 °C No condensation temperature Electrical Characteristics at Tc = 25°C, VCC = 24V, VDD = 5V Parameter Symbol Rating Conditions min VDD supply current ICCO CLOCK=GND Output average current Ioave With R/L=3Ω/3.8mH in each phase Vref = 0.137V FET diode forward voltage Vdf If=1A (RL=23Ω) Output saturation voltage Vsat RL=23Ω Input high voltage VIH Pins 8 to 12 (5 pins) Input low voltage VIL Pins 8 to 12 (5 pins) Input current IIL With pins 8 to 12 at the ground level. Vref input voltage VrH Pin 7 Vref input bias current IIB With pin 7 at 1V PWM frequency fc typ 0.52 unit max 3.1 7 0.58 0.64 A 1.1 1.7 V 0.31 0.44 V 2.5 V 0 35 mA 0.6 V 10 μA 3.5 V 50 500 nA 45 55 kHz Note: A fixed-voltage power supply must be used. No.A1254-2/13 STK672-340-E Package Dimensions unit:mm (typ) 46.6 8.5 1 2.0 (9.6) 11 2=22 12 0.5 1.0 4.0 12.7 3.6 25.5 41.2 0.4 2.9 Internal Equivalent Circuit Block Diagram VDD(5V) 6 8 CLOCK 9 CWB 10 RESETB 11 RESETB 12 AB B BB 5 4 3 2 VDD F1 MODE A MODE Excitation mode selection F3 F4 FAO Phase excitation signal generation CLOCK CWB F2 Phase advance counter FAB FBO FBB RESETB R1 R2 AI Chopping circuit RESETB BI CI 1 GND VSS Vref 7 ITF02169 No.A1254-3/13 STK672-340-E Sample Application Circuit STK672-340-E 10μF VDD=5V CO3 + 6 CLOCK 9 MODE 8 2-phase stepping motor 5 10 CWB 12 ENABLE RO4 20kΩ RESETB 5V 3 11 2 5V RO3 4 A AB VCC 24V B BB + CO2 At least 100μF RO1 D1 Vref 7 1 GND P.GND + 10μF CO4 0.1μF RO2 CO1 ITF02170 • To minimize noise in the 5V system, locate the ground side of capacitor CO2 in the above circuit as close as possible to pin 1 of the IC. Also, if at all possible, the ground used for Vref must not be common to the P.GND pattern, but must be directly wired from pin 1. • Insert resistor RO3 (47 to 100Ω) so that the discharge energy from capacitor CO4 is not directly applied to the CMOS IC in this hybrid device. If the diode D1 has Vf characteristics with Vf less than or equal to 0.6V (when If = 0.1A), this will be smaller than the CMOS IC input pin diode Vf. If this is the case RO3 may be replaced with a short without problem. • Apply 2.5V High level input to pins 8, 9, 10, 11, and 12. • Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 8, 9, 10, 11, and 12 are used as inputs, a 10 to 47kΩ pull-up resistor (to VDD) must be used. • To prevent incorrect operation due to chopping noise, we recommend inserting 470 to 1000pF capacitors between pin 1 and each of the pins 8, 9, 10, and 12. (With the open-collector type IC, we also recommend inserting a 470 to 1000pF capacitor between pin 11 (RESETB) and pin 1 when pin 11 is used as an input.) • The following circuit (for a lowered current of over 0.2A) is recommended if the application needs to temporarily lower the motor current. Here, a value of close to 100kΩ must be used for resistor RO1 to make the transistor output saturation voltage as low as possible. 5V 5V RO1 Vref RO1 RO3 Vref RO2 RO3 RO2 ITF02171 ITF02172 No.A1254-4/13 STK672-340-E • Motor current peak value IOH setting IOH 0 ITF02173 IOH = Vref ÷ Rs Vref = (RO2 ÷ (RO1 + RO2)) × 5V (or 3.3V) Rs is the hybrid IC internal current detection resistor. In the STK672-330-E (and STK672-350-E) Rs is 0.195Ω. (In the STK672-340-E and STK672-360-E, Rs is 0.14Ω.) Input Pin Functions Pin Name Pin No. Function Input Conditions When Operating CLOCK 9 Reference clock for motor phase current switching Operates on the rising edge of the signal MODE 8 Excitation mode selection Low: 2-phase excitation CWB 10 Motor direction switching Low: CW (forward) RESETB 11 System reset and A, AB, B, and BB outputs cutoff. High: 1-2 phase excitation High: CCW (reverse) A reset is applied by a low level Applications must apply a reset signal for at least 10μs when VDD is first applied. ENABLE 12 The A, AB, B, and BB outputs are turned off, and after The A, AB, B, and BB outputs are turned off by a low- operation is restored by returning the ENABLE pin to the level input. high level, operation continues with the same excitation timing as before the low-level input. (1) A simple reset function is formed from D1, CO4, RO3, and RO4 in this application circuit. With the CLOCK input held low, when the 5V supply voltage is brought up a reset is applied if the motor output phases A and BB are driven. If the 5V supply voltage rise time is slow (over 50ms), the motor output phases A and BB may not be driven. Increase the value of the capacitor CO4 and check circuit operation again. (2) See the timing chart for the concrete details on circuit operation. Usage Notes 1. STK672-340-E input signal functions and timing (Specifications common to the STK672-330-E as well) (All inputs have no internal pull-up resistor.) [RESETB and CLOCK (Input signal timing when power is first applied)] As shown in the timing chart, a RESETB signal input is required by the driver to operate with the timing in which the F1 gate is turned on first. The RESETB signal timing must be set up to have a width of at least 10μs, as shown below. The capacitor CO4, and the resistors RO3 and RO4 in the application circuit form simple reset circuit that uses the RC time constant rising time. However, when designing the RESETB input based on VIH levels, the application must have the timing shown in figure 1. Rise of the 5V supply voltage RESETB signal input At least 10μs CLOCK signal At least 5μs ITF02174 Figure 1 RESETB and CLOCK Signals Input Timing No.A1254-5/13 STK672-340-E [CLOCK (Phase switching clock)] • Input frequency: DC to 50kHz • Minimum pulse width: 10μs • Signals are read on the rising edge. [CWB (Motor direction setting)] The direction of rotation is switched by setting CWB to 1 (high) or 0 (low). See the timing charts for details on the operation of the outputs. Note: The state of the CWB input must not be changed during the 6.25μs period before and after the rising edge of the CLOCK input. [ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and selection of the operate or hold state for hybrid IC internal operation)] ENABLE = 1 (high): Normal operation ENABLE = 0 (low): Outputs A, AB, B, and BB forced to the off state. If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 (low) and then is later restored to the 1 (high) state, the IC will resume operation with the excitation timing continued from before the point ENABLE was set to 0 (low). [MODE (Excitation mode selection)] MODE = 0 (low): 2-phase excitation MODE = 1 (high): 1-2 phase excitation See the timing charts for details on output operation in these modes. Note: The state of the MODE input must not be changed during the 5μs period before and after the rising edge of the CLOCK input. 2. Allowable motor current operating range The motor current (IOH) must be held within the range corresponding to the area under the curve shown in figure 3. For example, if the operating substrate temperature Tc is 105°C, then IOH must be held under IOH = 2.2A, and in hold mode IOH must be held under IOH = 1.8A. 3. Thermal design [Operating range in which a heat sink is not used] This section discusses the safe operating range when no heat sink is used. In the maximum ratings specifications, Tc max is specified to be 105°C, and when mounted in an actual end product system, the Tc max value must never be exceeded during operation. Tc can be expressed by formula (A) below, and thus the range for ΔTc must be stipulated so that Tc is always under 105°C. Tc = Ta + ΔTc (A) Ta: Hybrid IC (HIC) ambient temperature, ΔTc: Temperature increase across the aluminum substrate As shown in figure 5, the value of ΔTc increases as the hybrid IC internal average power dissipation PD increases. As shown in figure 4, PD increases with the motor current. Here we describe the actual PD calculation using the example shown in the motor current timing chart in figure 2. Since there are periods when current flows and periods when the current is off during actual motor operation, PD cannot be determined from the data presented in figure 4. Therefore, we calculate PD assuming that actual motor operation consists of repetitions of the operation shown in figure 2. IO1 Motor phase current (sink side) IO2 -IO1 T1 T2 T3 T0 ITF02175 Figure 2 Motor Current Timing No.A1254-6/13 STK672-340-E T1: Motor rotation operation time T2: Motor hold operation time T3: Motor current off time T2 may be reduced, depending on the application. T0: Single repeated motor operating cycle IO1 and IO2: Motor current peak values Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. Note that figure 2 presents the concepts here, and that the on/off duty of the actual signals will differ. The hybrid IC (HIC) internal average power dissipation PD can be calculated from the following formula. PD = (T1 × P1 + T2 × P2 + T3 × 0) ÷ T0 ·························································· (I) (Here, P1 is the PD for IO1 and P2 is the PD for IO2) If the value calculated in formula (I) above is under 1.5W, then from figure 5 we see that operation is allowed up to an ambient temperature Ta of 60°C. While the operating range when a heat sink is not used can be determined from formula (I) above, figure 4 is merely a single example of one operating mode for a single motor. For example, while figure 4 shows a 2-phase excitation motor, if 1-2 phase excitation is used with a 500Hz clock frequency, the drive will be turned off for 25% of the time and the dissipation PD will be reduced to 75% of that in figure 4. It is extremely difficult for SANYO to calculate the internal average power dissipation PD for all possible end product conditions. After performing the above rough calculations, always install the hybrid IC (HIC) in an actual end product and verify that the substrate temperature Tc does not rise above 105°C. [Operating range in which a heat sink is used] Although a heat sink is attached to lower Tc if the hybrid IC (HIC) internal average power dissipation PD increases, the resulting size can be found using the value of θc-a in Equation (II) below and the graph depicted in Figure 6. θc-a= (Tc max-Ta) ÷ PD ---------------------------- (II) Tc max: Maximum operating substrate temperature =105°C Ta: HIC ambient temperature Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and confirm that the substrate temperature, Tc, is 105°C or less. The average HIC power loss, PD, described above represents the power loss when there is no avalanche operation. To add the loss during avalanche operations, be sure to add Equation (2), “Allowable STK672-3** Avalanche Energy Value”, to PD. θc-a - S Figure 6 Heat sink thermal resistance, θc-a - °C/W 100 7 5 3 2 Wit h 10 Wit h 7 5 a fl no at b l 3 surf ace fini sh ack surf ac e fi 2 nish 1.0 10 2 3 5 7 100 2 Heat sink area, S - cm2 3 5 7 1000 ITF02652 No.A1254-7/13 STK672-340-E 4. STK672-340-E Allowable Avalanche Energy Value [Allowable Range in Avalanche Mode] When driving a 2-phase stepping motor with constant current chopping using an STK672-3** Series hybrid IC, the waveforms shown in Figure 7 below result for the output current, ID, and voltage, VDS. VDSS: Voltage during avalanche operations VDS IOH: Motor current peak value IAVL: Current during avalanche operations ID tAVL: Time of avalanche operations ITF02557 Figure 7 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-3** Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping When operations of the MOSFET built into STK672-3** Series ICs is turned off for constant current chopping, the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly rises due to electromagnetic induction generated by the motor coil. In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at this time, EAVL1, is represented by Equation (1). EAVL1=VDSS×IAVL×0.5×tAVL ------------------------------------------- (1) VDSS: V units, IAVL: A units, tAVL: sec units The coefficient 0.5 in Equation (1) is a constant required to convert the IAVL triangle wave to a square wave. During STK672-3** Series operations, the waveforms in the figure above repeat due to the constant current chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (2) used to find the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (1). PAVL=VDSS×IAVL×0.5×tAVL×fc ------------------------------------------- (2) fc: Hz units (fc is set to the PWM frequency of 50kHz.) For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-3** Series and substitute values when operations are observed using an oscilloscope. Ex. If VDSS=110V, IAVL=1A, tAVL=0.2μs when using a STK672-340-E driver, the result is: PAVL=110×1×0.5×0.2×10-6×50×103=0.55W VDSS=110V is a value actually measured using an oscilloscope. The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 9. When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL waveforms during operation, and then check that the result of calculating Equation (2) falls within the allowable range for avalanche operations. No.A1254-8/13 STK672-340-E [ID and VDSS Operating Waveforms in Non-avalanche Mode] Although the waveforms during avalanche mode are given in Figure 7, sometimes an avalanche does not result during actual operations. Factors causing avalanche are listed below. • Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and BB phase). • Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor. • Increases in VDSS, tAVL, and IAVL in Figure 7 due to an increase in the supply voltage from 24V to 36V. If the factors above are negligible, the waveforms shown in Figure 7 become waveforms without avalanche as shown in Figure 8. Under operations shown in Figure 8, avalanche does not occur and there is no need to consider the allowable loss range of PAVL shown in Figure 9. VDS IOH: Motor current peak value ID ITF02558 Figure 8 Output Current, ID, and Voltage, VDS, Waveforms 2 of the STK672-3** Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping Average power loss in the avalanche state, PAVL - W Figure 9 Allowable Loss Range, PAVL-IOH During STK672-340-E Avalanche Operations PAVL - IOH 5.0 4.5 4.0 3.5 Tc =8 3.0 2.5 10 5 2.0 0° C °C 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 Motor phase current, IOH - A 3.0 3.5 ITF02653 Note: The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. Because it is possible to apply 3.0W or more at IOH=0A, be sure to avoid using the MOSFET body diode that is used to drive the motor as a zener diode. [Smoke Emission Precuations] If any of the output pins 2, 3, 4, and 5 is held open, the electrical stress onto the driver due to the inductive energy accumulated in the motor could cause short-circuit followed by permanent damage to the internal MOSFET. As a result, the STK672-340-E may give rise to emit smoke. No.A1254-9/13 STK672-340-E Timing Charts 2-phase excitation MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB No.A1254-10/13 STK672-340-E 1-2 phase excitation (CWB) MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB Switching from 2-phase to 1-2 phase excitation MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB No.A1254-11/13 STK672-340-E 1-2 phase excitation (ENABLE) MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB 4.0 IOH - Tc Figure 3 16 Internal average power dissipation, PD - W 200Hz 2 phase excitation 3.5 Motor current, IOH - A Hold mode 3.0 2.5 2.0 1.5 1.0 0.5 0 10 20 30 40 50 60 70 80 90 Substrate temperature, Tc - °C Substrate temperature rise, ΔTc - °C VCC=24V, VDD=5.0V 500Hz, 2 phase excitation Motor R=0.63Ω L=0.62mH 14 12 10 8 6 4 2 0 0 80 PD - IOH Figure 4 110 ITF02650 ΔTc - PD Figure 5 100 0 0.5 1.0 1.5 2.0 2.5 Motor current, IOH - A 3.0 3.5 4.0 ITF02651 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Hybrid IC internal average power dissipation, PD - W 3.5 ITF02178 No.A1254-12/13 STK672-340-E SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2011. Specifications and information herein are subject to change without notice. PS No.A1254-13/13