STMICROELECTRONICS LPS001WP

LPS001WP
MEMS pressure sensor
300-1100 mbar absolute digital output barometer
Preliminary data
Features
■
Piezoresistive pressure sensor
■
300-1100 mbar absolute pressure range
■
0.065 mbar resolution
■
Embedded offset and span temperature
compensation
■
Embedded 16-bit ADC
SPI and I C interfaces
■
Supply voltage 2.2 V to 3.6 V
■
High shock survivability (10000 g)
■
Small and thin package
■
ECOPACK® lead-free compliant
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Applications
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Altimeter and barometer for portable devices
■
Smartphones
■
Indoor navigation
■
GPS applications
■
Weather station equipment
■
Sports watches
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The VENSENS process allows the building of a
mono-silicon membrane above an air cavity with
controlled gap and defined pressure.
The membrane is very small compared to the
traditionally built silicon micromachined
membranes. Membrane breakage is prevented by
intrinsic mechanical stoppers.
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The IC interface is manufactured using a standard
CMOS process that allows a high level of
integration to design a dedicated circuit which is
trimmed to better match the sensing element
characteristics.
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Description
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The LPS001WP is an ultra compact absolute
piezoresistive pressure sensor. It includes a
monolithic sensing element and an IC interface
able to take information from the sensing element
and to provide a digital signal to the external
world.
Table 1.
Device summary
Part number
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The sensing element consists of a suspended
membrane realized inside a single mono-silicon
substrate. It is capable of detecting pressure and
is manufactured using a dedicated process
developed by ST, called VENSENS.
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HCLGA-8L (3x5x1 mm)
The LPS001WP is available in a small plastic land
grid array (HCLGA) package and is guaranteed to
operate over a temperature range extending from
-40 °C to +85 °C. The package is holed to allow
external pressure to reach the sensing element.
The LPS001WP belongs to a family of products
suitable for a variety of applications.
Temperature range [°C]
Package
-40 to +85
HCLGA-8L
LPS001WP
Tray
LPS001WPTR
November 2010
Packing
Tape and reel
Doc ID 18171 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/30
www.st.com
30
Contents
LPS001WP
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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4.1
Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2
Procedure for single acquisition (low power consumption) . . . . . . . . . . . 11
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5.2.1
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Reduced power consumption procedure . . . . . . . . . . . . . . . . . . . . . . . . 12
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
let
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I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1.1
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2.3
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/30
8.1
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.2
CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Doc ID 18171 Rev 1
LPS001WP
Contents
8.3
CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.4
STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.5
PRESS_OUT_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.6
PRESS_OUT_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.7
TEMP_OUT_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.8
TEMP_OUT_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.9
DELTA_P_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.10
DELTA_P_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.11
REF_P_L (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.12
REF_P_H (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.13
THS_P_L (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.14
THS_P_H (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Doc ID 18171 Rev 1
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List of tables
LPS001WP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 42.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power consumption @ 1 Hz and @ 4 Hz ODR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 15
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 15
Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
WHO_AM_I (0Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CTRL_REG1 (20h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CTRL_REG1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output data rate bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CTRL_REG2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CTRL_REG2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PRESS_OUT_L (28h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
RESS_OUT_L (28h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PRESS_OUT_H (29h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TEMP_OUT_L (2Ah) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TEMP_OUT_L (2Ah) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TEMP_OUT_H (2Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TEMP_OUT_H (2Bh) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DELTA_P_L (2Ch) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DELTA_P_L (2Ch) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DELTA_P_H (2Dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DELTA_P_H (2Dh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REF_P_L (30h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REF_P_L (30h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REF_P_H (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REF_P_H (31h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
THS_P_L (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
THS_P_L (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
THS_P_H (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
THS_P_H (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Doc ID 18171 Rev 1
LPS001WP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
LPS001WP electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
HCLGA-8L mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Doc ID 18171 Rev 1
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Block diagram and pin description
LPS001WP
1
Block diagram and pin description
1.1
Block diagram
Figure 1.
Block diagram
-58
2S
6OUT
2S
")46'!$#
$)')4!,&),4%2
2S
,/7./)3%
!.!,/'
&2/.4%.$
6UP
#3
$30&/2
4%-0%2!452%
#/-0%.3!4)/.
P
3%.3).'
%,%-%.4
4%-0%2!452%
3%.3/2
6/,4!'%
!.$#522%.4
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Pin connection
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'.$
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(6
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4OPVIEW
!-6
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Doc ID 18171 Rev 1
#,/#+
!.$
4)-).'
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Pin description
Figure 2.
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3!3$/
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LPS001WP
Block diagram and pin description
Table 2.
Pin description
Pin n°
Pin name
1
Vdd
Power supply
2
PS
Protocol selection
I2C/SPI mode selection (logic 1: I2C mode; logic 0: SPI enabled)
3
GND
4
HV
Connect to VDD (logical ‘1’)
5
CS
SPI enable (chip select)
6
SA0/SDO
7
SDA/
SDI/
SDO
8
SCL/SPC
Function
0 V supply
I2C less significant bit of device slave address (SA0)
SPI serial data output
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
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I2C serial clock (SCL)
SPI serial port clock (SPC)
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Mechanical and electrical specifications
2
LPS001WP
Mechanical and electrical specifications
Conditions @ Vdd = 2.5 V, T = 25 °C, unless otherwise noted.
2.1
Mechanical characteristics
.
Table 3.
Mechanical characteristics
Symbol
Pop
Res(2)
Parameter
Test condition
Operating pressure range
Pressure noise density
Acc
Accuracy
TSo
Temperature resolution
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Parameter
Test condition
Supply voltage
64
LSb/°C
Min. Typ.(1)
Supply current
Continous mode
ODRP = 7 Hz
ODRT = 1 Hz
190
During conversion
400
Supply current in power-down mode
ODRP
Pressure output data rate
ODRT
Temperature output data rate(3)
1
Top(3)
Extended operating temperature
range
-40
2. For pressure and temperature output data rate configurations refer to Table 18.
Doc ID 18171 Rev 1
Unit
3.6
V
1
(2)
3. Datasheet specification guaranteed only between -10 to 85 °C.
Max.
µA
1. Typical specifications are not guaranteed.
8/30
mbar
2.2
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+/-25
Electrical characteristics
Symbol
so
mbar/sqrt
(Hz)
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Table 4.
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Lsb/mbar
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P = 300 to 1100 mbar
T = -10 to 85 °C
Electrical characteristics
let
mbar
1100
0.028
2. Parameter given as standard deviation value.
Idd
300
16
Pn
Vdd
Unit
Pressure resolution
1. Typical specifications are not guaranteed.
2.2
Min. Typ.(1) Max.
µA
7
12.5
Hz
7
12.5
Hz
+85
°C
LPS001WP
3
Absolute maximum ratings
Absolute maximum ratings
Stress above those listed as “Absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
Ratings
Vdd
Supply voltage
Vin
Input voltage on any control pin
P
Maximum value
Unit
-0.3 to 6
V
Overpressure
TSTG
(s)
-0.3 to Vdd +0.3
ct
20
du
Storage temperature range
-40 to +125
V
bar
°C
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This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part
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This is an ESD sensitive device, improper handling can cause permanent damage to
the part
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Functionality
4
LPS001WP
Functionality
The LPS001WP is a high-resolution, digital-output pressure sensor packaged in an LGA
holed package. The complete device includes a sensing element based on a piezoresistive
Whetstone bridge approach, and an IC interface capable of providing information from the
sensing element to external applications as a digital signal.
4.1
Sensing element
An ST proprietary process is used to obtain a mono-silicon µ-sized membrane for MEMS
pressure sensors, without requiring substrate-to-substrate bonding.
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When pressure is applied, membrane deflection induces an imbalance in the Wheatstone
bridge piezoresistors, whose output signal is converted by the IC interface.
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Intrinsic mechanical stoppers prevent breakage in case of pressure overstress, ensuring
measurement repeatability.
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The pressure inside the buried cavity under the membrane is constant and controlled by
process parameters.
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To be compatible with traditional packaging technologies, a silicon holed cap is placed on
top of the sensing element. During the moulding phase, this opening is covered by
dedicated protection to avoid membrane blocking.
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The package design leaves the holed cap exposed, allowing ambient pressure to reach the
sensing element.
4.2
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IC interface
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The complete measurement chain consists of a low-noise capacitive amplifier, which
converts the resistive unbalance of the MEMS sensor into an analog voltage signal, and of
an analog-to-digital converter, which translates the produced signal into a digital bitstream.
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4.3
The converter is coupled with a dedicated reconstruction filter which removes the high
frequency components of the quantization noise and provides low rate and high resolution
digital words.
The pressure data can be accessed through an I2C/SPI interface, making the device
particularly suitable for direct interfacing with a microcontroller.
Factory calibration
The IC interface is factory-calibrated at two temperatures and two pressure levels for
sensitivity and accuracy.
The trimming values are stored inside the device using a non-volatile structure. Each time
the device is turned on, the trimming parameters are downloaded into the registers to be
employed during normal operation. This allows the user to employ the device without
requiring further calibration.
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Doc ID 18171 Rev 1
LPS001WP
5
Application hints
Application hints
Figure 3.
LPS001WP electrical connection
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The device core is supplied through the Vdd line. Power supply decoupling capacitors (100
nF ceramic, 10 µF aluminum) should be placed as near as possible to the supply pad of the
device (common design practice).
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The functionality of the device and the measured data outputs are selectable and accessible
through the I2C/SPI interface. When using the I2C, CS must be tied high.
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It is possible to change, on the fly, the communication interface used to access the device
registers. The PS (Protocol Selection) pin performs this change.
5.1
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Soldering
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The HCLGA package is compliant with the ECOPACK® standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C.
Procedure for single acquisition (low power consumption)
If the LPS001WP output data rate requested is lower than 7 Hz, a dedicated procedure to
reduce the power consumption can be implemented.
LPS001WP is in power down, then it is woken up for the acquisition and again put in power
down. This procedure reduces the power consumption.
Doc ID 18171 Rev 1
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Application hints
5.2.1
LPS001WP
Reduced power consumption procedure
1.
LPS001WP power down and low resolution mode
a)
Write CTRL_REG1 (20h) <= ‘1000xxxx’b
b)
Write CTRL_REG1 (20h) <= ‘0000xxxx’b (normal resolution)
or
2.
LPS001WP wake up
a)
Write CTRL_REG1 (20h) <= ‘1100xxxx’b
b)
Write CTRL_REG1 (20h) <= ‘0100xxxx’b (normal resolution)
or
3.
Wait 80 ms - settling time
4.
Output read
5.
a)
Read PRESS_OUT_H (29h)
b)
Read PRESS_OUT_L (28h)
c)
Read TEMP_OUT_H (2Bh)
d)
Read TEMP_OUT_L (2Ah)
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LPS001WP power down and low power mode
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Write CTRL_REG1 (20h) <= ‘1000xxxx’b
b)
Write CTRL_REG1 (20h) <= ‘0000xxxx’b (normal resolution)
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Power down and normal mode configuration: CTRL_REG1 (20h) <= ‘0000xxxx’b
Table 6.
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Power consumption @ 1 Hz and @ 4 Hz ODR
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Power consumption
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Idd
Condition
Min. Typ.(1)
Low resolution
ODR = 1 Hz
21
Normal resolution
ODR = 4 Hz
75
Normal resolution
ODR = 1 Hz
40
Normal resolution
ODR = 4 Hz
150
Supply current
Max.
Unit
µA
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1. Typical specifications are not guaranteed.
12/30
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Note:
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Doc ID 18171 Rev 1
LPS001WP
6
Digital interfaces
Digital interfaces
The registers embedded inside the LPS001WP may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS
line must be tied high.
PS pin select I2C or SPI interface.
If the I2C interface is disabled (PS pin connected to GND or logical ‘0’) and CS is kept high
(logical ‘1’), pin SDO and SDI are put in tri-state.
Table 7.
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Serial interface pin description
PIN Name
PIN Description
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PS
Protocol selection
I2C/SPI mode selection (logic 1: I2C mode; logic 0: I2C disabled)
CS
SPI enable (chip select)
I2C serial clock (SCL)
SPI serial port clock (SPC)
SCL/SPC
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SDA/SDI/SDO
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I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SA0/SDO
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I2C less significant bit of device slave address (SA0)
SPI serial data output (SDO)
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I2C serial interface
6.1
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The LPS001WP I2C is a bus slave. The I2C is employed to write the data into the registers
whose content can also be read back.
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The relevant I2C terminology is given in Table 8.
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Table 8.
Serial interface pin description
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals, and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both the lines are connected to Vdd through a pull-up resistor
embedded inside the LPS001WP. When the bus is free, both lines are high.
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Digital interfaces
LPS001WP
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as normal
mode.
I2C operation
6.1.1
The transaction on the bus is started through a START (ST) signal. A start condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
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The slave address (SAD) associated to the LPS001WP is 101110xb. The SDO pad can be
used to modify the less significant bit of the device address. If the SDO pad is connected to
voltage supply, LSb is ‘1’ (address 1011101b), otherwise, if the SDO pad is connected to
ground, the LSb value is ‘0’ (address 1011100b). This solution permits to connect and
address two different LPS001WPs to the same I2C lines.
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Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data has
been received.
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The I2C embedded inside the LPS001WP behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent (SAD +
R/W), once a slave acknowledge (SAK) has been returned, an 8-bit sub-address is
transmitted (SUB): the 7 LSb represent the actual register address while the MSB enables
address auto increment. If the MSb of the SUB field is 1, the SUB (register address) is
automatically incremented to allow a multiple data read/write.
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The slave address is completed with a read/write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write),
the master transmits to the slave with an unchanged direction. Table 9 explains how the
SAD+read/write bit pattern is composed, listing all the possible configurations.
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Table 9.
Command
SAD[6:1]
SAD[0] = SDO
R/W
SAD+R/W
Read
101110
0
1
10111001 (B9h)
Write
101110
0
0
10111000 (B8h)
Read
101110
1
1
10111011 (BBh)
Write
101110
1
0
10111010 (BAh)
Table 10.
Master
Slave
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SAD+read/write patterns
Transfer when master is writing one byte to slave
ST
SAD + W
SUB
SAK
Doc ID 18171 Rev 1
DATA
SAK
SP
SAK
LPS001WP
Digital interfaces
Table 11.
Master
Transfer when master is writing multiple bytes to slave
ST
SAD + W
SUB
Slave
SAK
Table 12.
Master
Master
DATA
SAK
SP
SAK
SAK
Transfer when master is receiving (reading) one byte of data from slave
ST
SAD + W
Slave
Table 13.
DATA
SUB
SR
SAK
SAD + R
SAK
NMAK
SAK
SP
DATA
Transfer when master is receiving (reading) multiple bytes of data from slave
ST SAD+W
Slave
SUB
SAK
SR SAD+R
SAK
MAK
SAK
DATA
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MAK
DATA
NMAK
SP
DATA
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Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW, to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
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In order to read multiple bytes incrementing the register address, it is necessary to assert
the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1
while SUB(6-0) represents the address of the first register to read.
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In the presented communication format MAK is master acknowledge and NMAK is no
master acknowledge.
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6.2
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SPI bus interface
The LPS001WP SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
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Digital interfaces
LPS001WP
Figure 4.
Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD 0
SDO
DO 7 DO6 DO5 DO 4 DO3 DO2 DO1DO0
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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and returns to high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
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Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in the case of multiple byte read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
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bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In the latter case, the chip drives SDO at the start of bit 8.
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bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands.
When 1, the address is auto incremented in multiple read/write commands.
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bit 2-7: address AD(5:0). This is the address field of the indexed register.
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bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
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bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
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In multiple read/write commands further blocks of 8 clock periods are added. When the MS
bit is 0, the address used to read/write data remains the same for every block. When MS bit
is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
Doc ID 18171 Rev 1
LPS001WP
6.2.1
Digital interfaces
SPI read
Figure 5.
SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7DO6 D O5 DO4DO3 D O2 DO1DO0
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The SPI read command is performed with 16 clock pulses. The multiple byte read command
is performed adding blocks of 8 clock pulses at the previous one.
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bit 0: READ bit. The value is 1.
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bit 1: MS bit. When 0, do not increment the address, when 1, increment the address in
multiple readings.
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bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
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bit 16-... : data DO(...-8). Further data in multiple byte readings.
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Figure 6.
Multiple bytes SPI read protocol (2 bytes example)
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CS
SPC
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SDI
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RW
MS AD5 AD4 AD 3 AD 2 AD1 AD0
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SDO
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6.2.2
DO7 DO6DO5 DO4 D O3 DO2 DO1 DO0 D O1 5DO14DO13D O1 2
DO11DO10DO9 D O8
SPI write
Figure 7.
SPI write protocol
CS
SPC
SDI
D I7 D I6 D I5 DI 4 DI 3 DI 2 DI 1 DI0
RW
MS AD5 AD4 AD3 AD2 AD 1 AD0
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Digital interfaces
LPS001WP
The SPI write command is performed with 16 clock pulses. The multiple byte write
command is performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0, do not increment the address, when 1, increment the address in
multiple writings.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writings.
Figure 8.
CS
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SPC
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SDI
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DI7 DI 6 DI5 D I4 DI3 DI2 DI1 DI0 D I15DI 14 DI13D I1 2DI11 DI10DI9 DI8
RW
MS AD5 AD4 AD3 AD 2 AD 1AD0
6.2.3
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Multiple bytes SPI write protocol (2 bytes example)
SPI read in 3-wires mode
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3-wires mode is entered by setting to 1 bit SIM (SPI serial interface mode selection) in the
internal control register.
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Figure 9.
SPI read protocol in 3-wires mode
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CS
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SPC
SDI/O
DO7 DO6 D O5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD 4 AD 3 AD2 AD1
AD 0
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0, do not increment the address, when 1, increment the address in
multiple readings.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Multiple read command is also available in 3-wires mode.
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LPS001WP
7
Register mapping
Register mapping
Table 14 below provides a listing of the 8-bit registers embedded in the device and the
related addresses.
.
Table 14.
Registers address map
Register address
Name
Type
Default
Hex
Reserved (Do not modify)
00-0E
WHO_AM_I
r
Reserved (Do not modify)
10111010
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20
010 0000
00000000
CTRL_REG2
rw
21
010 0001
00000000
23-26
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00000000
010 1000
output
010 1001
output
010 1010
output
2B
010 1011
output
2C
010 1100
output
2D
010 1101
output
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PRESS_OUT_L
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28
PRESS_OUT_H
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29
TEMP_OUT_L
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TEMP_OUT_H
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Reserved (Do not modify)
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Pr
010 0111
Status_Reg
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2A
2E-2F
rw
30
011 0000
00000000
REF_P_H
rw
31
011 0001
00000000
THS_P_L
rw
32
011 0010
00000000
THS_P_H
rw
33
011 0011
00000000
INTERRUPT_CFG
rw
34
011 0100
00000000
INT_SOURCE
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35
011 0101
output
INT_ACK
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36
011 0110
Reserved (Do not modify)
37-3F
Reserved
Reserved
REF_P_L
ete
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Dummy register
Reserved
rw
DELTA_P_H
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000 1111
CTRL_REG1
DELTA_P_L
ol
0F
Reserved
10-1F
Reserved (Do not modify)
Comment
Binary
Dummy register
Reserved
Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.
Doc ID 18171 Rev 1
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Register description
8
LPS001WP
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
pressure and temperature data. The registers address, made up of 7 bits, is used to identify
them and to read/write the data through the serial interface.
8.1
WHO_AM_I (0Fh)
Table 15.
WHO_AM_I (0Fh) register
1
0
1
1
1
0
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Device identification register.
1
0
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This read only register contains the device identifier which, for LPS001WP, is set to BAh.
8.2
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CTRL_REG1 (20h)
Table 16.
X
CTRL_REG1 (20h) register
PD
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Table 17.
s
b
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ODR0
DIFF_EN
BDU
BLE
SIM
CTRL_REG1 (20h) register description
Reserved
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Low power functionality. Default value: 0
(0: normal mode; 1: low-power activated)
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PD
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Power down control. Default value: 0
(0: power-down mode; 1: active mode)
ODR1
ODR0
Output data rate selection. Default value: 00
(see Table 18)
DIFF_EN
Interrupt circuit enable. Default value: 0
(0: interrupt generation disabled; 1: interrupt circuit enabled)
BDU
Block data update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB reading)
BLE
Big/little endian selection. Default value: 0
(0: little endian; 1: big endian)
SIM
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
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ODR1
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PD bit allows to turn on the device. The device is in power-down mode when PD = ‘0’
(default value after boot). The device is active when PD is set to ‘1’.
ODR1 - ODR0 bits allow to change the output data rates of pressure and temperature
samples. The default value is “00” which corresponds to a data rate of 7 Hz for pressure
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Doc ID 18171 Rev 1
LPS001WP
Register description
output and 1Hz for temperature output. ODR1 and ODR2 bits can be configured as
described in Table 18.
Table 18.
Output data rate bit configurations
ODR1(1)
ODR0
Pressure output data rate
Temperature output data rate
0
0
7 Hz
1 Hz
0
1
7 Hz
7 Hz
1
1
12.5 Hz
12.5 Hz
1. “10” bit configuration is not allowed and may cause incorrect device functionality.
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DIFF_EN bit is used to enable the circuitry for the computing of delta pressure output,
DELTA_P. In default mode (DIFF_EN = ‘0’) this circuitry is turned off.
It is suggested to turn on the circuitry only after the configuration of the REF_P_L,
REF_P_H, THS_P_L and THS_P_H registers used by the circuitry.
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BDU bit is used to inhibit output registers update between the reading of upper and lower
register parts. In default mode (BDU = ‘0’) the lower and upper register parts are updated
continuously. If it doesn’t read the output fast enough, the data update is blocked until the
two registers have been read. In this way, after the reading of the lower (upper) register part,
the content of that output register is not updated until the upper (lower) part is read too.
This feature avoids reading LSB and MSB related to different samples.
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BLE bit is used to select big endian or little endian representation for output registers.
In the big endian one, MSB values are located in PRESS_OUT_L (pressure),
TEMP_OUT_L (temperature) and DELTA_P_L (delta pressure), while LSB values are
located in PRESS_OUT_H, TEMP_OUT_H and DELTA_P_H. In little endian representation
the order is inverted (refer to data registers description for more details).
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SIM bit selects the SPI serial interface mode. When SIM is ‘0’ (default value) the 4-wire
interface mode is selected and data coming from the device are sent to pin #4 (SDO).
In 3-wire interface mode, output data are sent to pin #5 (SDI/SDO).
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8.3
CTRL_REG2 (21h)
Table 19.
BOOT
CTRL_REG2 (21h) register
X
X
X
X
X
X
0(1)
1. Bit to be kept to ‘0’ for correct device functionality
Table 20.
BOOT
CTRL_REG2 (21h) register description
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
BOOT bit is used to refresh the content of internal registers stored in the flash memory
block. At device power-up, the content of the flash memory block is transferred to the
internal registers related to trimming functions to permit a good behavior of the device itself.
If for any reason the content of trimming registers was changed, it is sufficient to use this bit
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Register description
LPS001WP
to restore the correct values. When the BOOT bit is set to ‘1’ the content of internal flash is
copied inside the corresponding internal registers and is used to calibrate the device. These
values are factory trimmed and they are different for every device. They permit a good
behavior of the device and normally they do not have to be changed. At the end of the boot
process the BOOT bit is set again to ‘0’.
The BOOT bit takes effect after one ODR clock cycle.
8.4
STATUS_REG (27h)
0
0
P_OR
T_OR
0
0
P_DA
P_OR
Pressure data overrun. Default value: 0
(0: no overrun has occurred;
1: new data for pressure has overwritten the previous one)
T_OR
Temperature data overrun. Default value: 0
(0: no overrun has occurred;
1: new data for temperature has overwritten the previous one)
P_DA
Pressure data available. Default value: 0
(0: new data for pressure is not yet available;
1: new data for pressure is available)
T_DA
Temperature data available. Default value: 0
(0: new data for temperature is not yet available;
1: new data for temperature is available)
T_DA
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
The content of this register is updated every ODR cycle, regardless of the BDU value in
CTRL_REG1.
t
c
u
P_DA is set to '1' whenever a new pressure sample is available. P_DA is cleared anytime
the PRESS_OUT_H (29h) register is read.
d
o
r
P
e
T_DA is set to '1' whenever a new temperature sample is available. T_DA is cleared anytime
the TEMP_OUT_H (2Bh) register is read.
t
e
l
o
s
b
O
8.5
P_OR bit is set to '1' whenever new pressure data is available and P_DA was set in the
previous ODR cycle and not cleared. P_OR is cleared anytime the PRESS_OUT_H (29h)
register is read.
T_OR is set to '1' whenever new temperature data is available and T_DA was set in the
previous ODR cycle and not cleared. T_OR is cleared anytime the TEMP_OUT_H (2Bh)
register is read.
PRESS_OUT_L (28h)
Table 21.
POUT7
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PRESS_OUT_L (28h) register
POUT6
POUT5
POUT4
POUT3
Doc ID 18171 Rev 1
POUT2
POUT1
POUT0
LPS001WP
Register description
Table 22.
POUT7 POUT0
RESS_OUT_L (28h) register description
Pressure data LSB (when BLE bit in the CTRL_REG1 is set to ‘0’, little endian)
Pressure data are expressed as absolute values. Values exceeding the operating pressure
range (see Table 3) are clipped.
In big endian mode (BLE bit in CTRL_REG1 set to ‘1’) the content of this register is the MSB
pressure data.
8.6
)
s
(
ct
PRESS_OUT_H (29h)
Table 23.
PRESS_OUT_H (29h) register
POUT15
Table 24.
POUT14
POUT13
POUT12
POUT11
POUT10
PRESS_OUT_H (29h) register description
e
t
e
ol
POUT15 POUT8
du
POUT9
POUT8
o
r
P
Pressure data MSB (when BLE bit in CTRL_REG1 is set to ‘0’)
s
b
O
In big endian mode (BLE bit in CTRL_REG1 set to ‘1’) the content of this register is the LSB
pressure data.
)
(s
8.7
TEMP_OUT_L (2Ah)
Table 25.
d
o
r
TOUT7
P
e
Table 26.
t
e
l
o
s
b
O
8.8
TOUT7 TOUT0
t
c
u
TEMP_OUT_L (2Ah) register
TOUT6
TOUT5
TOUT4
TOUT3
TOUT2
TOUT1
TOUT0
TEMP_OUT_L (2Ah) register description
Temperature data LSB (when BLE bit in CTRL_REG1 register is set to ‘0’, little
endian)
Temperature data are expressed as 2s complement numbers.
In big endian mode (BLE bit in CTRL_REG1 set to ‘1’) the content of this register is the MSB
temperature data.
TEMP_OUT_H (2Bh)
Table 27.
TOUT15
TEMP_OUT_H (2Bh) register
TOUT14
TOUT13
TOUT12
TOUT11
Doc ID 18171 Rev 1
TOUT10
TOUT9
TOUT8
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Register description
Table 28.
LPS001WP
TOUT8 TOUT15
TEMP_OUT_H (2Bh) register description
Temperature data MSB (when BLE bit in CTRL_REG1 register is set to ‘0’)
Temperature data are expressed as 2s complement numbers.
In big endian mode (BLE bit in CTRL_REG1 set to ‘1’) the content of this register is the LSB
temperature data.
8.9
DELTA_P_L (2Ch)
Table 29.
DP7
)
s
(
ct
DELTA_P_L (2Ch) register
Table 30.
DP6
DP5
DP4
DP3
DP2
DP0
u
d
o
r
P
e
DELTA_P_L (2Ch) register description
DP7 - DP0
DP1
Delta pressure data LSB (when BLE bit in CTRL_REG1 register is set to ‘0’)
t
e
l
o
DELTA_P registers store a delta pressure representing the difference between a constant
reference value, REF_P registers, and the actual pressure measured, PRESS_OUT
registers.
s
b
O
)
(s
In big endian mode (BLE bit in CTRL_REG1 set to ‘1’) the content of this register is the MSB
delta pressure data.
t
c
u
8.10
DELTA_P_H (2Dh)
Table 31.
P
e
d
o
r
DP15
t
e
l
o
s
b
O
8.11
Table 32.
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DELTA_P_H (2Dh) register description
DP15 - DP8 Delta pressure data MSB (when BLE bit in CTRL_REG1 register is set to ‘0’).
In big endian mode (BLE bit in CTRL_REG1 set to ‘1’) the content of this register is the LSB
delta pressure data.
REF_P_L (30h)
Table 33.
REFL7
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DELTA_P_H (2Dh) register
REF_P_L (30h) register
REFL6
REFL5
REFL4
REFL3
Doc ID 18171 Rev 1
REFL2
REFL1
REFL0
LPS001WP
Register description
Table 34.
REFL7 REFL0
REF_P_L (30h) register description
Reference pressure LSB data. Default value: 00h.
This register contains the lower part of the reference pressure for computing of delta
pressure.
Full value is REF_P_H & REF_P_L and it is represented as an unsigned number.
8.12
REF_P_H (31h)
Table 35.
REFL15
REF_P_H (31h) register
Table 36.
REFL14
REFL13
REFL12
REFL11
REFL10
)
s
(
ct
REFL9
REFL8
u
d
o
REF_P_H (31h) register description
r
P
e
REFL15 REFL8
Reference pressure MSB data. Default value: 00h.
t
e
l
o
This register contains the higher part of the reference pressure for computing of delta
pressure.
Full value is REF_P_H & REF_P_L and it is represented as an unsigned number.
8.13
Table 37.
Table 38.
t
e
l
o
bs
8.14
THS6
d
o
r
P
e
THS7 THS0
t
c
u
THS_P_L (32h) register
THS7
O
)
(s
THS_P_L (32h)
s
b
O
THS5
THS4
THS3
THS2
THS1
THS0
THS_P_L (32h) register description
Threshold pressure LSB. Default value: 00h.
This register contains the low part of threshold value for pressure interrupt generation.
The complete threshold value is given by THS_P_H & THS_P_L and is expressed as an
unsigned number.
THS_P_H (33h)
Table 39.
THS15
Table 40.
THS15 THS8
THS_P_H (33h) register
THS14
THS13
THS12
THS11
THS10
THS9
THS8
THS_P_H (33h) register description
Threshold pressure MSB. Default value: 00h.
Doc ID 18171 Rev 1
25/30
Register description
LPS001WP
This register contains the high part of threshold value for pressure interrupt generation.
The complete threshold value is given by THS_P_H & THS_P_L and is expressed as an
unsigned number.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
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Doc ID 18171 Rev 1
LPS001WP
9
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions, and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 41.
HCLGA-8L mechanical data
Dimensions
mm
)
s
(
ct
Ref.
E1
Min.
Typ.
2.850
3.0
E3
4.850
5.0
D3
1.200
e
t
e
ol
R1
N1
N2
)
(s
L1
P1
s
b
O
s
b
O
t
c
u
L2
e
t
e
ol
Pr
3.150
5.150
1.0
A1
od
Pr
T1
u
d
o
0
D1
P2
Max.
1.0
1.0
0.625
2.0
3.750
1.300
2.300
0.800
d
0.200
T2
0.500
K
0.050
M1
0.100
Doc ID 18171 Rev 1
27/30
Package information
LPS001WP
Figure 10. HCLGA-8L mechanical drawing
Pin 1 Indicator
A1
E1
P1
E3
K
KC
d
T1
P2
R1
L2
D1
N2
D3
T2
D
)
s
(
ct
u
d
o
KE
E
let
KD
o
s
b
TOP VIEW
O
)
s
(
t
c
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P
e
t
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s
b
O
28/30
r
P
e
K
C
Doc ID 18171 Rev 1
N1
L1
M1
BOTTOM VIEW
LPS001WP
10
Revision history
Revision history
Table 42.
Document revision history
Date
Revision
05-Nov-2010
1
Changes
Initial release.
)
s
(
ct
u
d
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r
P
e
t
e
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o
)
(s
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Doc ID 18171 Rev 1
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LPS001WP
)
s
(
ct
Please Read Carefully:
u
d
o
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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r
P
e
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t
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l
o
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)
(s
s
b
O
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t
c
u
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d
o
r
P
e
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l
o
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
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s
b
O
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