PT2831 15W x 2, Class-D Audio Power Amplifier DESCRIPTION FEATURES Supports Multiple Output Configurations (THD=10%) --- 2 x 5W into a 8Ω BTL at 9V --- 2 x 10W into a 8Ω BTL at 12V --- 2 x 15W into a 8Ω BTL at 15V 4Ω minimum load Single power supply reduces component count (Built-in 5V regulator) Master/Slave Synchronization 4 voltage gains setting Power ON de-pop enable Integrated Self-Protection Circuits including Under / Over supply voltage, short circuit and over temperature protection Stereo and Mono mode with Single Filter Mono configuration Wide Voltage Range: 4.5V~16V Small size 28 Pins HT-SSOP package with thermal pad The PT2831 is a Class-D power amplifier designs for audio system; the maximum output power could up to 15W x 2. It is housing in a small, thermal enhanced package, the best benefits of the PT2831 are high efficiency and less external components. Fabricated by high voltage BCD process to improve ESD and electro stress handling capabilities. APPLICATIONS Sound Bar Mini Audio System Docking Speaker System Consumer Audio Applications BLOCK DIAGRAM BYPASS VREG VDDP SVCC HVSS VREG Regulator HVSS Regulator SGND PVCC SVC VREG C VREG Driver-H VCMfb CVCM PWM Logic Level Shift HVS S VDDP OUTN Driver-L INN PGND PVCC INP VREG Driver-H GAIN0 Gain Adj PWM Logic GAIN1 SYNCLK Level Shift HVS S VDDP OUTP Driver-L OSC PGND ROSC OE Protection & Function STBY MUTE *Shows the block diagram of one of the two identical channels Tel: 886-3-5752191‧Fax: 886-3-5752566‧http:// www.core-technology.com.tw‧6F, No. 47, Lane 2, Sec. 2, Guangfu Rd., Hsinchu City 30071, Taiwan PT2831 APPLICATION CIRCUIT DIAGRAM C8 C21 1 SVCC 2 HVSS BYPASS 28 INNB 27 C2 C12 C1 L1 C17 R3 C15 3 SUB_GND INPB 26 4 OUTPB GAIN1 25 5 PGNDB GAIN0 24 6 PVCCB CVCM 23 7 OUTNB OE 22 VREG VREG C10 C13 C24 C18 L2 VCC C23 8 OUTNA SGND 21 9 PVCCA VREG 20 10 PGNDA SYNCLK 19 11 OUTPA ROSC 18 12 PGND INNA 17 13 VDDP INPA 16 14 STBY MUTE 15 L3 GND C25 PT2831 C7 C19 R4 C16 C11 C14 C20 C5 L4 R1 VREG R5 SVCC C4 C3 C9 SVCC R6 R2 C22 R_load 4Ω 6Ω 8Ω C6 LC Filter components L1, L2, L3, L4 C15, C16 15uH 470nF 22uH 220nF 33uH 220nF PARTS RECOMMENDATION Capacitor C1, C2, C3, C4---0.47uF C5, C10, C11, C12, C17~C21---0.1uF C6, C8, C22 ---2.2uF C7, C9,---1uF C13, C14---330pF C23---1000uF C25---0.22uF C24—4.7uF Resistor R1---39KΩ R2, R6---33KΩ R3, R4, R5---22Ω For better THD+N performance the X7R material SMD capacitor is recommended. V1.1 2 August 2015 PT2831 ORDER INFORMATION Part Number Package Type Top Code PT2831-HT 28 pins, HTSSOP, 173mil PT2831-HT PIN CONFIGURATION 1 SVCC 2 HVSS BYPASS 28 INNB 27 3 SUB_GND INPB 26 4 OUTPB GAIN1 25 5 PGNDB GAIN0 24 6 PVCCB CVCM 23 OE 22 7 OUTNB PT2831 8 OUTNA SGND 21 9 PVCCA VREG 20 10 PGNDA SYNCLK 19 11 OUTPA ROSC 18 12 PGND INNA 17 INPA 16 MUTE 15 13 14 V1.1 VDDP STBY 3 August 2015 PT2831 PIN DESCRIPTION Pin Name SVCC HVSS SUB_GND OUTPB PGNDB PVCCB OUTNB OUTNA PVCCA PGNDA OUTPA PGND VDDP STBY MUTE INPA INNA ROSC SYNCLK VREG SGND OE CVCM GAIN0 GAIN1 INPB INNB BYPASS V1.1 I/O Power O Power O Power Power O O Power Power O Power O I I I I O I/O O Power O O I I I I O Description Signal power supply Regulator output referred to power supply Connect to the frame Positive PWM for right channel Power stage ground for right channel Power supply for right channel Negative PWM output for right channel Negative PWM output for left channel Power supply for left channel Power stage ground for left channel Positive PWM for left channel Power stage ground Regulator output referred to ground for power stage Standby mode control Mute mode control Positive differential input of left channel Negative differential input of left channel Master Oscillator frequency-setting pin Clock in/out for external oscillator Regulator output referred to ground for power stage Signal ground Open-drain diagnostic output Supply voltage rejection Gain setting input 1 Gain setting input 2 Positive differential input of right channel Negative differential input of right channel Half VREG referred to ground 4 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 August 2015 PT2831 FUNCTIONAL DESCRIPTION POWER REQUIREMENT Operating voltage range of the PT2831 is from 4.5V to 16V, all of PVDD pins should add bypass cap to absorb ripples and noises, using a 0.1μF+10μF capacitors for bypassing is recommended. The power supply monitor (UV/OV) block will always monitor the supply voltage. It have 2 window limits; one for the under voltage (UV) and another one for over voltage (OV), refer to electric spec for detail specifications. When supply voltage variation exceeds the window, the amplifier will be muted to eliminate pop-noise. Built-in 5V regulator provides a clean, filtered DC power source to the analog and control logic circuitry to improve PSRR. The STBY pin is use to cut-off current consumption of whole chip. Total supply current will drop under 20uA typically when shutdown is active even PVDD is still powered. CLASS-D GAIN SETTING The gain of the PT2831 is set by the two inputs, GAIN0 (pin 24) and GAIN1 (pin 25). Internally, the gain is set by changing the feedback resistors of the amplifier. Class-D Amp Gain CLASS-D GAIN1 GAIN0 GAIN 20dB 0 0 26dB 1 0 30dB 0 1 32dB 1 1 V1.1 5 August 2015 PT2831 INTERNAL AND EXTERNAL CLOCKS The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one PT2831 as master clock, while the other devices are in slave mode (that is, externally clocked). The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. MASTER MODE (INTERNAL CLOCK) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC. In master mode, pin SYNCLK is used as a clock output pin, whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60kΩ. SLAVE MODE (EXTERNAL CLOCK) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This force pin SYNCLK to be internally configured. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Mode Master Slave ROSC ROSC < 60KΩ Floating (no connect) Master Slave PT2831 PT2831 ROSC SYNCLK ROSC Output V1.1 SYNCLK Output Input SYNCLK Input 6 August 2015 PT2831 MODE SELECTION STANDBY MODE All of circuits are turned off, very low current consumption. MUTE MODE: Pull Mute pin to GND, the class-D output PWM waveform will stay on 50% duty cycle but the output audio signal was muted. NORMAL MODE: The amplifiers are active. The OE has internally pull up resistance to 5V supply, in general condition connect a cap on OE pin could help delay the turn on time to prevent pop noise. PROTECTION MODE: During power-on period---OE stay “Logic Low”, OV/UV, OC, & OT, there would be no output. Mode STBY Mute OE Standby L X X Mute 1 H L X Mute 2 X X L Normal H H H* *Drive level defined in Electrical specifications POWER-ON SEQUENCE FOR MINIMIZING SPEAKER “POP” SVCC VREG STBY BYPASS To mute 2.1V OE If external mute OE 22 0.22uF INPUT OUTPUT Hardware mute configuration V1.1 Power-on & Mute timing 7 August 2015 PT2831 MONO MODE (PBTL) The PT2831 family can be connected in MONO mode enabling up to 28W output power. This is done by: • Connect INPB and INNB directly to Ground (without capacitors) this sets the device in Mono mode during power up. • Connect OUTPA and OUTNA together for the positive speaker terminal and OUTNB and OUTPB together for the negative terminal • Analog input signal is applied to INPA and INNA PT2831 CHA PSU 4.5V~16V OUTPA OUTNA LC Filter OUTPB OUTNB CHB PBTL Detect PROTECTION FUNCTION The PT2831 is fully protected against over-voltage, under-voltage, over-current and thermal overload. OVER-VOLTAGE PROTECTION (OVP) If the supply voltage exceeds the value for VOVP, the over-voltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage drops to below the threshold value the device restarts. UNDER-VOLTAGE PROTECTION (UVP) If the supply voltage drops below the value for VUVP, the under-voltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage recovers the device restarts. OVER-CURRENT PROTECTION (OCP) If the output current exceeds the value for IOCP, the over-current protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the over-current condition is still present then the OCP remains active. The restart time, TOC, is determined by the Capacitor components connected to pin OE. THERMAL PROTECTION (OTP) If the junction temperature, Tj, reaches 145°C (nominal), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj, the device shuts down and the output is forced to the high impedance state. When the device cools sufficiently the device restarts. V1.1 8 August 2015 PT2831 PCB LAYOUT The heat dissipation of the PT2831 is summed up by the following factors: supply voltage, load Impedance, and type of input signal. Because of the amplitude and frequency of the audio signals is not a fixed value during general music broadcasts; thus, the accumulated heat will be less than a continuous sine wave power output. In brief, because the amplitude and frequency of audio signals varies, the average power output is lower than that of a fixed continuous sine wave. Thus, the heat caused by a normal sine wave will accumulate faster because of a higher average power output. Sometimes when testing continuously may activate the overheat protection. The activation of the overheat protection depends on the heat dissipation condition. The larger copper foil area on the PCB, the better heat is dissipated. Please refer to the list below when designing the PCB layout. 1. Large (1000μF or greater) bulk power supply decoupling capacitors should be placed near the PT2831 on the PVCC supplies. The high-frequency bypass capacitors (0.1uF) should be placed as close to the PVCCA/PVCCB pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection. 2. Keep the current loop from each of the outputs through the inductor and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. 3. The copper foil on the PCB must have at least 1.oz thickness. 4. The PCB should 2 layers board is recommended. 5. PCB must have enough via holes below the thermal pad; it is recommended to have 18 holes, the holes diameter is 0.5mm. 6. The copper foil connected with thermal pad should be connected to ground plate and do not connected to any others Voltage LEVEL. The copper foil must be plated in broad and continuously and do not cut off from the midway as possible. V1.1 9 August 2015 PT2831 ABSOLUTE MAXIMUM RATING Characteristic MIN 0 -40 -40 -40 -2 -200 -0.3 -0.3 Supply voltage, PVCC Operating Temperature, Top Storage Temperature, Tstg Junction Temperature, Tj ESD HBM MM LV group HV group All Pins Maximum Input Voltage, Vi max Unit V °C °C °C KV V V V MAX 18 85 150 165 +2 +200 VREG+0.3 PVCC+0.3 ELECTRICAL CHARACTERISTIC Unless Stated Otherwise, PVCC(A/B)=12V, RL(load) =8Ω, ROSC=39KΩ, COSC=100nF, f=1KHz, GV=20dB, Tamb=25°C, TEST BANDWIDTH=22 ~ 22KHZ Symbol Parameter Test Conditions Min Typ Max Unit General PVCC Supply Voltage 4.5 16 V No input, exclude filter 20 35 mA ICC Supply Current STBY=0.8V 20 30 µA VOS1 Output offset voltage Play mode -150 150 mV VOS2 Output offset voltage Mute mode -150 150 mV Over-current RL = 0 Ω, 6 IOCP(BTL) A protection threshold OUTPA, NA, OUTPB, NB Over-current RL = 0 Ω, 13 IOCP(PBTL) A protection threshold OUTPA, NA, OUTPB, NB Junction Temperature at ℃ 165 Over-temperature thermal, Output Off OTP protection threshold ℃ 100 Output On Over Voltage 16.5 OVP V Protection Under Voltage 4 UVP V Protection 2.3 VIH Digital Input High Gain0, Gain1, MUTE, STBY V 0.9 VIL Digital Input Low Gain0, Gain1, MUTE, STBY V Class-D Amplifier KΩ Rin Input Resistance IN+ and IN25 Switch Frequency Fosc PVDD=12V 360 390 420 KHz Range Internal oscillator, Fsw Switch Frequency 780 KHz master mode N + PMOS, Tj=25℃ mΩ Rsw Switch Resistance 400 Total Harmonic Po= 1 W, RL=8Ω THD+N 0.027 0.1 % Distortion GAIN1=0, GAIN0=0 18 20 22 GAIN1=1, GAIN0=0 24 26 28 Gv dB Closed loop gain GAIN1=0, GAIN0=1 28 30 32 GAIN1=1, GAIN0=1 30 32 34 Gmatch Gain matching OUTA and OUTB -1 1 dB CT V1.1 Cross Talk F=1KHz, Po=1W 10 - 90 - dB August 2015 PT2831 Symbol Parameter Pomax Maximum Output Power Test Conditions VCC=12V, THD=1%, RL=8Ω VCC=12V, THD=10%, RL=8Ω VCC=15V,THD=1%, RL=8Ω VCC=15V,THD=10%, RL=8Ω VCC=12V, THD=1%, RL=4Ω VCC=12V, THD=10%, RL=4Ω VCC=15V,THD=1%, RL=4Ω VCC=15V,THD=10%, RL=4Ω A-weighted , Gain=20dB Vno Output Noise 20~22KHz Min - Typ 7.8 10 12 15.4 13 16.7 20 25 Max - Unit - 90 - μV - -81 - dBV - 150 - μV - -76 - dBV W SNR Signal to noise ratio THD+N<1%, A-weighted - 102 - dB AMUTE Mute Attenuation - 88 - dB PD Power Dissipated - 3.8 - W η Efficiency Power Supply Rejection Ratio Rise and fall times 0dB@Po=1W Po=15W+15W, THD=10%, PVCC=15V Po=15W+15W, PVCC=15V - 90 - % Fr=100Hz, Vr=1Vpp, Csvr=1uF - 65 - dB - - 30 - Ns - - 4 - Ω - 4 - Ω PSRR Tr, Tf RL(BTL) RL(PBTL) V1.1 Minimum load Impedance 11 August 2015 PT2831 Test Condition: PVCC=5~15V, RL=8Ω, F=1KHz, Gain=20dB, T=25°C Output Power vs PVCC THD=1% Efficiency THD=10% 9V 16 90 14 80 12 70 10 8 6 15V 60 50 40 30 4 20 2 10 0 0 5 6 7 8 9 10 11 12 13 14 0 15 5 10 15 Output Power Per Channel (W) PVCC (V) THD vs Output Power - PVCC=5V THD vs Output Power - PVCC=9V 10 10 5 5 2 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 100m 0.02 200m 500m 1 2 5 10 20 0.01 100m 40 200m 500m 1 W 2 5 10 20 40 W THD vs Output Power - PVCC=12V THD vs Output Power - PVCC=15V 10 10 5 5 2 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 100m 0.02 200m 500m 1 2 5 10 20 0.01 100m 40 W V1.1 12V 100 Efficiency (%) Output Power (W) 18 200m 500m 1 2 5 10 20 40 W 12 August 2015 PT2831 Test Condition: PVCC=5~15V, RL=6Ω, F=1KHz, Gain=20dB, T=25°C Output Power vs PVCC THD=1% Efficiency THD=10% 9V 20 18 16 15V 90 80 14 12 10 8 70 60 50 40 30 6 4 20 10 2 0 0 5 6 7 8 9 10 11 12 13 14 0 15 5 10 15 20 Output Power Per Channel (W) PVCC (V) THD vs Output Power - PVCC=5V THD vs Output Power - PVCC=9V 10 10 5 5 2 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 70m 100m 200m 500m 1 2 5 10 20 0.01 70m 100m 40 200m 500m 1 W 2 5 10 20 40 20 40 W THD vs Output Power - PVCC=12V THD vs Output Power - PVCC=15V 10 10 5 5 2 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 70m 100m 200m 500m 1 2 5 10 20 40 W V1.1 12V 100 Efficiency (%) Output Power (W) 22 0.01 70m 100m 200m 500m 1 2 5 10 W 13 August 2015 PT2831 Test Condition: PVCC=5~15V, RL=4Ω, F=1KHz, Gain=20dB, T=25°C Output Power vs PVCC THD=10% 9V 26 24 22 20 18 16 14 12 10 8 6 4 2 0 15V 90 80 70 60 50 40 30 20 10 0 5 6 7 8 9 10 11 12 13 14 0 15 5 10 THD vs Output Power - PVCC=5V 10 15 20 25 Output Power Per Channel (W) PVCC (V) THD vs Output Power - PVCC=9V 10 TTTTTTTTTTTT 5 5 2 2 1 1 0.5 0.5 % TTTTTTTTTTTT % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 100m 0.02 200m 500m 1 2 5 10 20 0.01 100m 40 200m 500m 1 W 2 5 10 20 40 20 40 W THD vs Output Power - PVCC=12V 10 THD vs Output Power - PVCC=15V 10 TTTTTTTTTTTT 5 5 2 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 100m 0.02 200m 500m 1 2 5 10 20 40 W V1.1 12V 100 Efficiency (%) Output Power (W) THD=1% Efficiency 0.01 100m 200m 500m 1 2 5 10 W 14 August 2015 PT2831 Test Condition: PBTL, PVCC=5~15V, RL=4Ω, F=1KHz, Gain=20dB, T=25°C Output Power vs PVCC 9V THD=10% 15V 90 80 70 60 50 40 30 20 10 0 4 5 6 7 8 9 10 11 12 13 14 15 0 5 10 PVCC (V) 15 20 25 30 Output Power Per Channel (W) THD vs Output Power - PVCC=5V THD vs Output Power - PVCC=9V 10 10 5 5 2 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 100m 0.02 200m 500m 1 2 5 10 20 0.01 100m 40 200m 500m 1 W 2 5 10 20 40 20 40 W THD vs Output Power - PVCC=12V THD vs Output Power - PVCC=15V 10 10 5 5 2 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 100m 0.02 200m 500m 1 2 5 10 20 40 W V1.1 12V 100 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 Efficiency (%) Output Power (W) THD=1% Efficiency 0.01 100m 200m 500m 1 2 5 10 W 15 August 2015 PT2831 PACKAGE INFORMATION 28-PIN, HTSSOP, 173MIL Symbol Min. Nom. Max. A - - 1.20 A1 0.05 - 0.15 b 0.19 - 0.30 c 0.127 TYP. e 0.65 BSC. D 9.60 9.70 9.80 D1 4.41 - 5.51 6.4 BSC. E E1 4.30 4.40 4.50 E2 2.40 - 3.00 1.00 REF. L1 0° - 8° Notes: 1. Refer to JEDEC MO-153 AET 2. Unit: mm V1.1 16 August 2015 PT2831 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.1 17 August 2015